A semiconductor device includes: a supporting body having first and second principal faces, and semiconductor elements; a thin film metal electrode on the first principal face; a thick film metal body on the thin film metal electrode; and a resin structure on the supporting body. The thick film metal body has a thickness greater than that of the thin film metal electrode. The resin structure includes a first resin body that covers a side of the thick film metal body. The resin structure has at least one of structures 1 and 2 as follows: in the structure 1, the resin structure further includes a second resin body on the second principal face; and in the structure 2, the first resin body includes first and second regions on the first principal face, and the second region has a thickness greater than that of the first region.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
2.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having one principal surface on which a groove portion is formed, a plurality of fuse wirings formed in the groove portion, a metal wiring disposed at a position separated from the groove portion and exposed on the one principal surface, a first insulating film covering the one principal surface and having a first opening that exposes the plurality of fuse wirings and a second opening that exposes the metal wiring, a polymeric insulating film in the first opening burying the plurality of fuse wirings in the groove portion, a first metal portion covering the polymeric insulating film, a second metal portion extending so as to cover a surface of the metal wiring exposed in the second opening and a surface of the first insulating film at a peripheral edge of the second opening, a second insulating film burying the first metal portion on an upper surface of the polymeric insulating film and covering the second metal portion so as to partially expose an upper surface thereof, and a third metal portion ranging from an upper surface of the second metal portion exposed from the second insulating film to an upper surface of the second insulating film.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
3.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a post electrode, and a burying layer. The first semiconductor chip includes a plurality of first metal terminals and external metal terminals formed in different regions, and a bonding layer including an oxide film to fill therebetween. The second semiconductor chip includes a plurality of second metal terminals formed on an opposed surface of the first semiconductor chip and a bonding layer including an oxide film provided to fill therebetween. The second semiconductor chip is mounted on the first semiconductor chip by bonding the bonding layers one another. The post electrode is formed above the one surface of the first semiconductor chip and provided on the external metal terminal of the first semiconductor chip. The burying layer buries the second semiconductor chip and the post electrode on the one surface of the first semiconductor chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
4.
BATTERY MONITORING SYSTEM AND SEMICONDUCTOR DEVICE
A battery monitoring system includes at least one group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; and a first semiconductor device capable of measuring a voltage of the at least one group of the battery cells. The first semiconductor device includes: a first terminal connected to a high potential side of the first battery cell through a first filter, the first filter being connected to a low potential side of the second battery cell; a second terminal connected to the high potential side of the first battery cell through a second filter, the second filter being connected to the low potential side of the second battery cell; a first discharge circuit connected to the first terminal; and a first circuit connected to the second terminal.
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
5.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a thin-film metal electrode provided on a first main surface of a support base, a thin-film resin layer covering an edge of the thin-film metal electrode, a thick-film metal body located above the thin-film metal electrode and containing copper, a thick-film resin body covering a lateral surface of the thick-film metal body, and a structure body including at least one of a first film provided on the first main surface and a second film provided on a second main surface. The thick-film metal body, the thin-film metal electrode, and the support base are arranged along a direction of a first axis. Upper surfaces of the thick-film metal body and the thick-film resin body extend along a reference plane intersecting with the first axis. A thermal expansion coefficient of the first film is between those of the thick-film resin body and a semiconductor of the support base.
A semiconductor device includes a semiconductor chip, a first antenna element and a second antenna element. The semiconductor chip includes a communication circuit. The first antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a first direction parallel to a first surface of the semiconductor chip. The second antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a second direction parallel to a second surface opposite to the first surface of the semiconductor chip.
An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
A semiconductor device, including: an insulating substrate provided with a substrate surface; a first conductive body and a second conductive body provided on the substrate surface; the second conductive body being separated from the first conductive body; an insulating film covering the first conductive body and the second conductive body; and a third conductive body provided on a face of the insulating film at an opposite side thereof from a side at which the substrate surface is disposed, the third conductive body penetrating the insulating film and contacting the second conductive body, wherein the insulating film includes a thinned portion at which a thickness of the insulating film is decreased such that the insulating film can be locally fractured by application of a voltage to the insulating film between the third conductive body and the first conductive body.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/00 - Details of semiconductor or other solid state devices
9.
INDUCTANCE ELEMENT AND INDUCTANCE ELEMENT FABRICATION METHOD
An inductance element including: a support body including a main face including a first area and a second area surrounding the first area; a first resin body disposed within the first area; and an inductor provided at the main face of the support body, wherein the first resin body includes a first soft magnetic body layer and a second soft magnetic body layer that are both disposed inside the first area, wherein the inductor is positioned between the first soft magnetic body layer and the second soft magnetic body layer, wherein the first soft magnetic body layer includes a first insulating resin body and plural first magnetic bodies surrounded by the first insulating resin body, and wherein the second soft magnetic body layer includes a second insulating resin body and plural second magnetic bodies surrounded by the second insulating resin body.
H01F 41/00 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
H01F 41/34 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film in patterns, e.g. by lithography
10.
SEMICONDUCTOR DEVICE, BASE-SIDE SEMICONDUCTOR CHIP, AND BONDING-SIDE SEMICONDUCTOR CHIP
A semiconductor device includes: a first semiconductor chip on which a first alignment mark, a second alignment mark, first and second terminals for measuring conduction, a wiring that electrically connects the first alignment mark and the first terminal, and a wiring that electrically connects the second alignment mark and the second terminal are provided; and a second semiconductor chip on which a third alignment mark, a fourth alignment mark, and a wiring that electrically connects the third alignment mark and the fourth alignment mark are provided and which is bonded to the first semiconductor chip in such a way that the first alignment mark and the third alignment mark overlap each other, and the second alignment mark and the fourth alignment mark overlap each other.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
12.
SUPPORT STAGE, SUPPORT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A support stage includes a base portion, a support portion that is erected at a peripheral edge portion of the base portion and with which one surface of a wafer is to be come into contact, a suction groove that is provided at the support portion and to which a suction force with respect to the one surface is to be given, an ejecting hole that is provided in an inward portion of the base portion and by which a gas is to be ejected toward the one surface, and an exhaust hole that is provided in at least either one of the base portion and the support portion and by which a gas is to be discharged from a space between the base portion, the support portion, and the one surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A detection device including: a laser sensor provided between a supply unit that supplies an inspection object and an inspection unit that inspects the inspection object; and a measurement unit that measures a state of the inspection object by using the laser sensor with respect to the inspection object moving along a transport direction from the supply unit toward the inspection unit.
G01B 11/27 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes for testing the alignment of axes
A pixel 10 is provided with a lower metal electrode 41, an upper metal electrode 43, a capacitor insulation layer 42, contacts 44 and 45 and a contact 46. The lower metal electrode 41, upper metal electrode 43 and capacitor insulation layer 42 are formed on a semiconductor substrate 21, are clear of a region in which a photodiode 11 is formed, and are formed at a region in which a reading circuit 13 is formed. At least the contacts 44 and 45 electrically connect the lower metal electrode 41 with a metal wire 40, and at least the contact 46 electrically connects the upper metal electrode 43 with the metal wire 40.
A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.
A battery monitoring system includes a first group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; a second group of a plurality of battery cells connected in series and including a third battery cell at a highest potential and a fourth battery cell at a lowest potential, the second group of the battery cells being connected to the first group of the battery cells in series; and first and second semiconductor devices capable of measuring a voltage of the first group of the battery cells and a voltage of the second group of the battery cells, respectively.
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
18.
SUBSTRATE PROCESSING APPARATUS AND COVER RING ASSEMBLY
Provided is a cover ring assembly that allows suppressing a dust generation source and reducing adhesion of particles on a substrate. A cover ring assembly for a substrate processing apparatus, which exposes a substrate to processing particles in an internal space to process the substrate, includes an annular flat plate and a cover ring having an annular shape. The annular flat plate has an inner peripheral upper surface and an outer peripheral upper surface. The inner peripheral upper surface is in contact with an outer peripheral lower surface terminating at an outer surface of the substrate. The outer peripheral upper surface is around the inner peripheral upper surface. The cover ring has a lower portion surface having an abutting surface in contact with the outer peripheral upper surface of the annular flat plate. A thermal spraying film covering a surface exposed to the processing particles is disposed to the cover ring except for the abutting surface.
This semiconductor device comprises a substrate, a passivation film that covers the substrate, a first resin film that is provided on the passivation film, a capacitor that is provided on the passivation film and is positioned above the first resin film, and an inductor that is provided on the passivation film and is formed in a layer differing from that of the capacitor.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01G 4/40 - Structural combinations of fixed capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
20.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention comprises: a plurality of pixels each having a semiconductor substrate of a first conductivity type, a photodiode, a transistor that has a well area of the first conductivity type and that amplifies a charge generated in the photodiode, and a MOS-type capacitor portion that has a well area of the same first conductivity type as the semiconductor substrate and that accumulates the charge from the transistor to hold the same; and a plurality of special diffusion layers formed on the semiconductor substrate so as to cover each of the well area of the transistor and the well area of the MOS-type capacitor portion in each pixel, the special diffusion layers containing injected impurities of a second conductivity type different from the first conductivity type.
The present invention forms a reference mark 22 formed in a first process of a photolithography process of semiconductor device manufacturing and a reference mark 24 formed in a second process following the first process as concentric double square frames, and sets, as a detection position XoRi, a middle point of the width of a signal waveform S representing a change in contrast of image data acquired by an imaging device provided to an optical microscope of an alignment measurement device and including the reference mark 22 and the reference mark 24 in a portion of an intersection between the signal waveform S and a predetermined threshold value Th, and the detection position XoRi is used as a reference for positioning of a layer relating to a third process following the second process.
[Solution] This semiconductor device comprises: a semiconductor region including a semiconductor layer of a first conductivity type; a BOX insulating layer extending along the surface of the semiconductor region and having an opening in a BOX window area of the surface of the semiconductor region; a pixel isolation region of a second conductivity type different from the first conductivity type, provided in the semiconductor region so as to surround one pixel area including the BOX window area; a floating semiconductor region of the first conductivity type provided in the semiconductor layer in the BOX window area; and a doped region extending into the semiconductor layer along the surface of the semiconductor region in the BOX window area and containing a p-type or n-type dopant, wherein the doped region has a dopant concentration of the first conductivity type or the second conductivity type that is greater than the dopant concentration of the first conductivity type of the semiconductor layer.
H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
23.
SEMICONDUCTOR DEVICE AND SOLID-STATE IMAGING DEVICE
This semiconductor device comprises: a semiconductor region that includes a semiconductor layer of a first conductivity type; a BOX insulating layer that extends along the surface of the semiconductor region and has openings at BOX window areas of the surface of the semiconductor region; floating semiconductor regions of the first conductivity type that are provided in the BOX window areas in the semiconductor region; and pixel isolation regions of a second conductivity type different from the first conductivity type that are provided in the semiconductor region so as to surround pixel areas containing the BOX window areas. The semiconductor layer forms junctions with the inner side surfaces and bottom surfaces of the pixel isolation regions, and at least one of the following is satisfied: in the surface of the semiconductor region, the width of the BOX window areas is greater than 1 times and at most 1. 5 times the width of the floating semiconductor regions; and in the surface of the semiconductor region, the width of the pixel isolation regions is at least 1 times and at most 2.2 times the width of the floating semiconductor regions.
H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
In this semiconductor device: each of a source that is formed on a main surface of a semiconductor substrate and a floating gate that contacts the main surface with an insulating film therebetween is provided adjacent to a capacitive element portion, the source and the floating gate forming a storage element portion; a first gate polycrystalline silicon layer of the capacitive element portion is extended to form a contact portion of the storage element portion, and a memory poly-layer of the capacitive element portion is extended to form a control gate of the storage element portion; a first contact is provided on the capacitive element portion side of the first gate polycrystalline silicon layer; a second contact is provided in a position spaced apart from the capacitive element portion in the control gate; and a third contact is provided in a position spaced apart from the capacitive element portion in a source wire in contact with the source.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
25.
SEMICONDUCTOR DEVICE, AND SOLID-STATE IMAGING DEVICE
A semiconductor device of the present disclosure: has a sensor element unit and a peripheral circuit unit; and is obtained by laminating a semiconductor layer, an insulating layer, and a first-electroconductivity-type support substrate. The semiconductor device includes: a first-electroconductivity-type first semiconductor layer, in which the potential provided in a region including at least a partial region of the sensor element unit and a region in which a circuit element is formed has been neutralized; a second-electroconductivity-type second semiconductor layer that forms a potential barrier and that is joined to the support substrate to form a photodiode; a third semiconductor layer of the second electroconductivity type that is formed on the sensor element unit and that detects charges from the photodiode; and a transfer electrode for transferring charge to the third semiconductor layer, the transfer electrode being installed on the sensor element unit on the first surface side of the insulating layer. The insulating layer includes a first insulating layer and a second insulating layer that is provided in the region in which the transfer electrode is positioned, the first insulating layer being thinner than the first insulating layer.
This blood vessel determination device is provided with: an image acquisition unit which acquires an image captured upon the irradiation of a part of a body with near infrared light; a luminance value acquisition unit which acquires luminance values of a plurality of pixels constituting the image acquired by the image acquisition unit from the image; a calculation unit which calculates a corrected luminance value of one pixel among the plurality of pixels on the basis of a luminance value of a predetermined pixel in the vicinity of the one pixel which is acquired by the luminance value acquisition unit; and a determination unit which determines that a predetermined number of pixels selected in ascending order with respect to the corrected luminance values among the plurality of pixels constituting the image are blood vessels.
The present invention comprises: a semiconductor substrate which has a groove formed in one principal surface thereof; a plurality of fuse wires which are formed in the groove; metal wiring which is placed in a position at a distance from the groove and is exposed within the one principal surface; a first insulating film which covers the one principal surface and has a first opening through which the plurality of fuse wires are exposed and a second opening through which the metal wiring is exposed; a polymer insulating film in which a plurality of fuses are embedded in the groove in the first opening; a first metal part which covers the polymer insulating film; a second metal part which extends so as to cover the surface of the metal wiring exposed in the second opening and the surface of the first insulating film at the edges of the second opening; a second insulating film which forms a cover such that the first metal part is embedded on the polymer insulating film and the top surface of the second metal part is partially exposed; and a third metal part which reaches from the top surface of the second metal part exposed by the second insulating film to the top surface of the second insulating film.
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
28.
BLOOD VESSEL DETERMINATION DEVICE, BLOOD VESSEL DETERMINATION METHOD AND NON-TRANSITORY STORAGE MEDIUM
A blood vessel judgment device acquires an image captured while near-infrared light is illuminated at a part of a body. Based on brightness values of a plurality of pixels configuring the acquired image, the blood vessel determination device determines that a predetermined number of pixels counted in order of brightness value from a pixel with a lowest brightness value represent blood vessels.
The present invention includes: a first semiconductor chip having a plurality of first metal terminals formed in one region of one surface, a plurality of external metal terminals formed in another region, and a joining layer made of an oxide film provided so as to fill the gaps therebetween; a second semiconductor chip which has a plurality of second metal terminals formed on an opposing surface opposing the one surface of the first semiconductor chip, and a joining layer made of an oxide film provided on the opposing surface so as to fill the gaps therebetween, and which is mounted on the first semiconductor chip by joining the joining layers together such that the respective metal terminals contact each other; a post electrode formed above the one surface of the first semiconductor chip and provided on the external metal terminal of the first semiconductor chip with a metal film therebetween; and an embedding layer that embeds the second semiconductor chip and the post electrode on the one surface of the first semiconductor chip.
H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
30.
Semiconductor package and method for manufacturing semiconductor package
A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
31.
SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT
A semiconductor memory device includes a semiconductor region including an active region for a memory transistor and plural depressions for trench isolation, insulating regions respectively provided at the depressions, a gate electrode and a gate insulation film. The gate electrode extends in a direction from one to the other of a first insulating region and second insulating region, and passes over the active region. The gate insulation film is provided between the gate electrode and the active region provided between the first and second insulating regions. The first and second insulating regions includes an adjacent region and a distant region. The distant region is adjacent to the adjacent region under the gate electrode. The adjacent region is adjacent to the active region under the gate electrode. The adjacent region is provided between the distant region and the active region, and has a smaller thickness than the distant region.
A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
A measuring apparatus, includes: a first and a second ion-sensitive semiconductor elements and a reference electrode disposed so as to contact a medium of which a characteristic value is to be measured; a signal input unit receiving a first and a second signals from the first and the second ion-sensitive semiconductor elements, and generating a sensor signal; a processor processing the sensor signal; and a memory storing first data relating to fluctuations over time of the first and the second ion-sensitive semiconductor elements, and connected to the processor, wherein: the processor processes the sensor signal by using the first data and a cumulative energization time of the first and the second ion-sensitive semiconductor elements, and generate an output signal for the characteristic value, the first ion-sensitive semiconductor element includes a first sensitive film, the second ion-sensitive semiconductor element includes a second sensitive film different from the first material.
There is provided a semiconductor device including: a circuit region formed on a semiconductor substrate; a first insulating film covering at least a portion of a region on the semiconductor substrate that includes an upper portion of the circuit region; redistribution wiring disposed on the first insulating film; a coil formed by the redistribution wiring on the first insulating film, the coil being connected to the circuit region; a first soft magnetic material film disposed in an aperture portion of the first insulating film, the aperture portion being provided at a lower portion of the coil; and a second soft magnetic material film that is disposed on the first soft magnetic material film, the second soft magnetic material film covering at least a portion of the coil.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A support stage (20A) includes: a base portion (21); a supporting portion (25) which is provided projecting from a peripheral edge portion of the base portion (21) and with which one surface (2) of a wafer (W) comes into contact; a suction groove (31) which is provided in the supporting portion (25), and with which a suction force with respect to the one surface (2) is imparted; an ejection hole (35) which is provided in an inner portion of the base portion (21), and which ejects gas toward the one surface (2); and a vent hole (36) which is provided in at least one of the base portion (21) and the supporting portion (25), and which vents gas from a space between the base portion (21), the supporting portion (25), and the one surface (2).
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/3275 - Details of drivers for data electrodes
A semiconductor device including a first inverter circuit connected in parallel to a crystal vibrating element; a second inverter circuit connected to the first inverter circuit so as to share an input therewith, and outputting an oscillation signal; and a wave filter connected to the second inverter circuit and having a passband that is determined in advance and includes an oscillation frequency of the oscillation signal.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
A semiconductor device includes a semiconductor chip, a first antenna element and a second antenna element. The semiconductor chip includes a communication circuit. The first antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a first direction parallel to a first surface of the semiconductor chip. The second antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a second direction parallel to a second surface opposite to the first surface of the semiconductor chip.
A semiconductor device includes a semiconductor substrate and a first memory cell disposed on the semiconductor substrate. The first memory cell includes a first write and erasure transistor, a first read transistor, and a first charge transfer reduction transistor. The first write and erasure transistor controls data writing and erasing. The first read transistor controls data reading. The first charge transfer reduction transistor reduces injection of an electric charge to the first write and erasure transistor and the first read transistor.
There is provided a semiconductor device including: a circuit region formed on one surface of a semiconductor substrate; a connection portion disposed at the one surface, the connection portion covering the circuit region, being electrically connected to the circuit region, and being used to connect with an exterior device; an annular wire formed at the one surface so as to surround the circuit region; a first protective film covering the annular wire, the first protective film being formed between the connection portion and a peripheral edge portion of the semiconductor substrate; and a second protective film formed at a predetermined partial region on the connection portion.
The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
43.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device including: forming a conductor film for floating gates through a gate insulating film on a semiconductor substrate; etching the conductor film, the gate insulating film, and the semiconductor substrate so as to form an element isolation trench extending in one direction of the semiconductor substrate and having a width and depth that periodically change along an extension direction; and forming an element isolation insulating film by burying the element isolation trench with an insulator.
A semiconductor device in which an SOI substrate having an element region in which circuit elements are formed, an insulation layer having a first surface adjoining the SOI substrate, and a support substrate of a first conductivity type are laminated. On the SOI substrate, a transfer electrode configured to transfer charges generated in the support substrate to a third semiconductor layer is formed in a region different from the element region, and the transfer electrode and the third semiconductor layer are adjacent in plan view.
A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value. The semiconductor integrated circuit includes a reference capacitor having a fixed electrostatic capacitance between the first capacitance and the second capacitance as the reference capacitance value; and an amplifier circuit, charging the capacitance variable capacitor via a first node and charging the reference capacitor via a second node corresponding to a clock signal, amplifying a potential difference between a potential of the first node and a potential of the second node, and outputting a binary determination signal indicating whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed the reference capacitance value based on the amplified potential difference.
An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
A notification response circuit includes a reception coil, a characteristic variable circuit connected to the reception coil, and a switch control circuit. The reception coil is configured to generate a current based on an external electromagnetic field. The characteristic variable circuit includes at least two circuits of a variable capacitor circuit, a voltage output circuit, and a variable resistor circuit. The variable capacitor circuit is configured to change a capacitance. The voltage output circuit is configured to change a voltage value between a pair of connection lines disposed between the reception coil and the voltage output circuit according to a voltage value of a reference voltage. The variable resistor circuit is configured to change a resistance value. The switch control circuit selectively switches any of the at least two circuits and performs control to change impedances of the reception coil and a circuit part connected to the reception coil.
A voltage generation unit includes first to k-th amplifiers that individually receiving first to k-th reference voltages having mutually different voltage values, individually amplify these reference voltages with gain 1, and output the reference voltages. The generation unit generates plural gradation voltages by dividing voltages between respective voltages output from the first to k-th amplifiers. A decoder unit selects one gradation voltage corresponding to the luminance level represented by the pixel data piece among the gradation voltages and generates a signal having the one gradation voltage as the drive signal for driving a display device. Each amplifier includes a response-speed increase circuit that includes at least one transistor in which a source and a back gate are connected to an output terminal of the amplifier, a predetermined electric potential is applied to a drain, and the reference voltage received by the amplifier is received at a gate.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/3258 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
The disclosure provides an information acquisition device capable of accurately acquiring information inside a living body as compared with a transmission type and a reflection type. The information acquisition device includes an output source that irradiates a target living body with a detection wave, and a reception part capable of receiving the detection wave irradiated to the target living body. The output source and the reception part are arranged so that an angle between a direction of irradiating the target living body with the detection wave from the output source and a direction from an irradiation point of the target living body irradiated by the detection wave to the reception part is an obtuse angle.
A61B 5/1455 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value using optical sensors, e.g. spectral photometrical oximeters
A61B 5/00 - Measuring for diagnostic purposes Identification of persons
50.
Combined wave data generation method, combined wave data generation program, storage medium, combined wave data generation device, and waveform data generation method
The present invention generates data series indicating respective combined-wave data pieces by a first step of obtaining a reference time length as a reference of a time length of one combined wave, a sampling interval time, and a frequency fluctuation rate, a second step of calculating a total number of samples in the data series indicating the one combined wave on the basis of the reference time length, the sampling interval time, and the frequency fluctuation rate, a third step of calculating a rotation angle with respect to the sampling interval time on the basis of the total number of samples for each of plural sound data pieces, a fourth step of calculating combined values for the total number of samples, the combined values being obtained by combining respective values of the plural sound data pieces, the values being calculated on the basis of the rotation angles for the respective sampling interval times, a fifth step of generating a series of the combined values for the total number of samples for the respective sampling time intervals as a data series of the one combined-wave data piece, and performing a sequence of the processes of the second to the fifth steps by a predetermined times while changing the frequency fluctuation rate every time when the sequence of the processes is executed once.
A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A display driver drives a display device including a plurality of data lines and a demultiplexer. The demultiplexer includes a plurality of first switches connected to the respective plurality of data lines, and a series of driving voltages including a plurality of driving voltages is supplied via a first wiring. The demultiplexer supplies the plurality of driving voltages to the respective plurality of data lines via the plurality of first switches. The display driver includes: a voltage multiplexing part that generates the series of driving voltages; a second switch connected between the voltage multiplexing part and the first wiring; and a controller connected to the plurality of first switches and the second switch. The controller switches the second switch from an on state to an off state during a first period and sets the two first switches corresponding to the two data lines to the on state such that the two data lines and the first wiring are connected during a second period that is a part of the first period and in which the second switch is in the off state.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
54.
Image processing device for detecting horizontal direction of photographing angle
An imaging device and a horizontal direction detection method capable of detecting a horizontal angle of a camera with high accuracy in a simple configuration are provided. The imaging device includes an imaging unit configured to obtain image data by photographing a predetermined subject, an image rotation unit configured to cause a display image based on the image data to be rotated on a display plane step by step, a count unit configured to count the number of pixels of a specific color included in the display image in a scanning line direction within the display plane and obtain a count value for each of rotated display images, and a determination unit configured to determine a horizontal direction of a photographing angle of the imaging unit based on the count value for each of the rotated display images.
An output circuit is provided, including: a positive polarity voltage signal supplying circuit to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch of which a source is connected to the first node and a drain is connected to a first output terminal; a second switch of which a source is connected to the second node and a drain is connected to the first output terminal; and third and fourth switches; a first and a second voltage control circuits respectively performing on-off control of the first and second switches.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
A display driving device includes a high voltage operating unit obtaining an operating current according to the application of the high power supply voltage from the first voltage application line; a low voltage operating unit that operates according to an application of a low power supply voltage to control the high voltage operating unit; a recycling circuit that receives the operating current from the high voltage operating unit via a relay coupling line and applies the low power supply voltage to the low voltage operating unit while supplying the received operating current to a reference potential line via the low voltage operating unit; and a current bypass circuit that flows a part of the operating current flowing through the relay coupling line into the reference potential line without supplying the part of the operating current to the recycling circuit according to a voltage increase in the low power supply voltage.
G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.
A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
59.
Method for manufacturing a semiconductor device with reduced variation of the impurity concentration near the surface of the semiconductor film
A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.
A high-density source region is formed along a surface of a semiconductor substrate and is connected to either one of a power source line and ground line. A low-density source region has an exposed surface at a surface of the semiconductor substrate and is in contact with the high-density source region. A high-density drain region is formed along the surface of the semiconductor substrate and is connected to the other one of the power source line and the ground line. A low-density drain region has an exposed surface at the surface of the semiconductor substrate, is in contact with the high-density drain region, and extends to a deeper region from the surface of the semiconductor substrate than does the low-density source region. A gate electrode is connected to either one of the power source line and the ground line.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
61.
Semiconductor device and semiconductor device fabrication method
A semiconductor device, including: a first well of a first polarity formed in a semiconductor substrate; a source region and a drain region of a second polarity formed in the first well so as to be separated from each other by a predetermined spacing; an impurity region of the first polarity formed so as to surround the source region and the drain region; a first gate oxide film formed on the semiconductor substrate at a position between the source region and the drain region; a second gate oxide film formed on the first gate oxide film; a gate electrode formed on the second gate oxide film; and an impurity layer of the first polarity formed below the first gate oxide film.
The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.
A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/097 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
A semiconductor device has a semiconductor substrate and a semiconductor film doped with impurities that is formed so as to cover an inner wall surface of a trench formed so as to extend from a first surface of the semiconductor substrate towards an interior thereof. The semiconductor film is formed so as to extend continuously from the inner wall surface to the first surface of the semiconductor substrate. The semiconductor device further has an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench. The semiconductor device further has an insulating film that insulates the semiconductor film from the opposite electrode.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
67.
Semiconductor storage element, semiconductor storage device and system-on-chip
The disclosure provides a semiconductor storage element which is provided with an error detection and correction circuit and, when an uncorrectable error occurs in the semiconductor storage element, capable of promptly transferring the occurrence to the outside, and provides a semiconductor storage device and a system-on-chip using the same. The semiconductor storage element includes a storage part storing data, an error detection and correction part detecting an error in the data stored in the storage part and correcting the error if possible, a monitoring part issuing an uncorrectable error signal when an uncorrectable error occurs in the error detection and correction part, and a terminal transmitting the uncorrectable error signal to the outside.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
68.
Digital-to-analog conversion circuit, data driver, and display device
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H03M 1/76 - Simultaneous conversion using switching tree
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
A display driver according to the present invention generates a plurality of driving voltages based on a video signal and applies the respective driving voltages to a plurality of source lines of a display panel. The display driver includes an overdrive part and an overdrive control circuit. The overdrive part executes an overdrive processing to increase amplitudes of the driving voltages. The overdrive control circuit detects an internal temperature of the display driver and stops the overdrive processing by the overdrive part when the temperature is higher than a predetermined temperature threshold.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H02H 5/04 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
70.
Semiconductor device and manufacturing method for semiconductor device
A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
Provided is a display panel, a source driver that generates a gradation voltage signal based on an image data signal, a timing controller that supplies the image data signal to the source driver, and an illumination drive unit that controls an amount of light of a backlight that illuminates each of a plurality of areas formed by dividing a display screen in the display panel. The source driver or the timing controller calculates feature values of the image data signal corresponding to each of the plurality of areas of the display panel and supplies a dimming data signal representing the amount of light of the backlight according to the feature values of each area to the illumination drive unit. The illumination drive unit controls the amount of light of the backlight for each of the plurality of areas based on the dimming data signal.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
A power source switching device that includes: a switch connected to a signal input terminal via a first resistor element and configured to fix a potential of the signal input terminal at a predetermined potential by adopting an ON state in a case in which a selection signal is not input; and a switch control circuit configured to perform control to place the switch in an OFF state based on a state signal indicating an operational state of a circuit that operates when supplied with power from a power source selected according to the selection signal in a case in which a potential of the selection signal is different from the predetermined potential, and to perform control to place the switch in the ON state in a case in which the selection signal is not input.
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
75.
Battery monitoring system and semiconductor device
A battery monitoring system includes a plurality of battery cells connected in series; a cell voltage measurement circuit for measuring a voltage of the battery cells; a first terminal connected to the cell voltage measurement circuit; a second terminal isolated from the cell voltage measurement circuit; a plurality of protection elements each corresponding to each of the battery cells; and a protection circuit connected to the second terminal for discharging an electric current from the protection elements through the second terminal.
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
A reference electrode including a casing through which one face at one side of a liquid junction that leaches an internal liquid is exposed, the casing being provided with an overhang portion that hangs out on the one face side of the liquid junction and prevents separation of the liquid junction from the casing; and an open portion that leaves a space on the one side of the liquid junction open toward a lateral direction along the one face.
A shield case for covering an electronic component includes a top panel portion made of a metal plate, a plurality of terminal leg portions formed to project in a direction intersecting with the top panel portion from a peripheral edge portion thereof, and a side plate portion formed to project in the direction intersecting with the top panel portion from a peripheral edge portion of the top panel portion other than the plurality of terminal leg portions. Each of the plurality of terminal leg portions includes a leg portion that stretches from the top panel portion, a joint portion that extends in a direction intersecting with the leg portion from a distal end of the leg portion, and a terminal portion with a ring-shaped cross-sectional surface that has a projecting support abutting on the leg portion from a distal end of the joint portion.
An image distortion correction circuit according to the present invention comprises; a first distortion correction circuit that performs a mapping process on an input image signal to generate a distortion-corrected image signal; an inspection region defining circuit that defines an inspection image region in the one-frame image; an inspection region extraction circuit that extracts a part corresponding to the inspection image region from the distortion-corrected image signal and outputs the part of the distortion-corrected image signal as a first inspection image signal; a second distortion correction circuit that outputs a second inspection signal, the second inspection signal being generated by performing the mapping process on the part of the input image signal corresponding to the inspection image region; and a failure determination circuit that determines that a failure occurs and outputs a failure detection signal when the first inspection image signal and the second inspection image signal are mutually different.
A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.
A multilayer substrate includes a first dielectric layer, a first conductive layer, and a conductor portion. The first dielectric layer has a first region. The first conductive layer is laminated on the first dielectric layer, excluding the first region. The conductor portion has one or more auxiliary conductors disposed at a distance from the first conductive layer, and one or more connecting conductors that connect said one or more auxiliary conductors to the first conductive layer.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H01Q 9/42 - Resonant antennas with feed to end of elongated active element, e.g. unipole with folded element, the folded parts being spaced apart a small fraction of the operating wavelength
A shield case, joined to a circuit board on which electronic components are mounted and covering the electronic components, has a top plate portion covering the electronic components, and a plurality of terminal leg portions formed in a way of projecting in a direction intersecting with the top plate portion from a peripheral edge portion of the top plate portion. Each of the plurality of terminal leg portions has: a leg portion stretching from the top plate portion; a terminal portion which extends in a direction intersecting with the leg portion from a front-end of the leg portion and is joined to the circuit board; and an expansion terminal portion which is formed by bending a front-end portion of each of the terminal portions along an end surface of the circuit board and has a length exceeding a thickness of the circuit board.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 9/00 - Screening of apparatus or components against electric or magnetic fields
82.
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
83.
Image distortion correction circuit and display device
An image distortion correction circuit performs a distortion correction process on an image signal on the basis of distortion correction data to generate a distortion-corrected image signal. The distortion correction data is for correcting coordinate positions of display data fragments corresponding to respective N coordinate positions in the display image to first to N-th distortion correction coordinate positions. The image distortion correction circuit determines a distortion correction coordinate position where abnormality occurs as an abnormal coordinate position among the first to N-th distortion correction coordinate positions on the basis of respective intervals between the adjacent first to N-th distortion correction coordinate positions indicated by the distortion correction data. The image distortion correction circuit corrects a part corresponding to the abnormal coordinate position in the distortion correction data on the basis of at least the two distortion correction coordinate positions excluding the abnormal coordinate position among the first to N-th distortion correction coordinate positions.
To provide a semiconductor device having a monitoring function with a higher degree of freedom. The semiconductor device includes: a function part that executes a predetermined process triggered according to an activation signal sent from an external device and outputs a completion signal after the predetermined process is completed; a first clocking part that monitors a first abnormality in the predetermined process based on the activation signal and the completion signal; and a branch part pair including a first branch part and a second branch part, wherein the first branch part branches the activation signal and then sends the branched activation signal to the function part and the first clocking part, and the second branch part branches the completion signal and then sends the branched completion signal to the first clocking part and the external device.
Provided is a traveling direction determination device that determines, using an acceleration sensor that generates acceleration signals indicating acceleration in three axial directions together with a direction of the acceleration, a traveling direction of a moving object mounted with the acceleration sensor, the traveling direction determination device comprising a determination unit that executes a first determination process in which the determination unit selects, using the acceleration signals, any of the three axes as a gravity axis, the gravity axis being closest to an actual gravity direction of the moving object to determine a gravity direction of the moving object and a second determination process in which the determination unit selects either of the two axes excluding the axis selected as the gravity axis, as a travel axis, the travel axis being closest to an actual traveling direction of the moving object based on moving average values of the acceleration signals to determine the traveling direction of the moving object.
H04W 4/02 - Services making use of location information
G01C 21/16 - NavigationNavigational instruments not provided for in groups by using measurement of speed or acceleration executed aboard the object being navigatedDead reckoning by integrating acceleration or speed, i.e. inertial navigation
A semiconductor device includes a first well of a first conductivity type formed to extend inwardly from a first region on one surface of the semiconductor substrate; a second well of a second conductivity type formed to extend inwardly from a second region separated from the first region on said surface of the semiconductor substrate; a third well of the first conductivity type formed to extend inwardly from a third region separated from the second region on said surface of the semiconductor substrate; and a conductive layer formed over the first region, the second region, and the third region on said surface of the semiconductor substrate. A recess is formed to expose a side face of the first well, and the conductive layer is formed to cover a top surface of the first well exposed in the first region and at least part of the side face.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A display device includes a display panel, a display controller configured to output a video data signal, a gate driver, and a plurality of source drivers which are arranged in an extension direction of gate lines and generate a gradation voltage signal to be supplied to each of a plurality of pixel units based on the video data signal supplied from the display controller. Each of the plurality of source drivers includes a data processing unit configured to share an abnormal state sharing signal indicating whether an abnormality has occurred in communication with the display controller with other source drivers, and when the abnormal state sharing signal indicates that an abnormality has occurred in communication with the display controller, supply a gradation voltage signal corresponding to predetermined gradation data different from a gradation voltage signal based on the video data signal to each of the plurality of pixel units.
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/30 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels
89.
SEMICONDUCTOR DEVICE AND MEASUREMENT PROCESSING SYSTEM
An average processing section, a timer, and a control section are provided. The average processing section is configured to compute an average measurement value, this being an average value of plural observed values of each of plural measurement targets as output from a switching section that switches output between measurement values acquired from each of the plural measurement targets. The timer is configured to generate a timer signal configured by timing signals at a predetermined interval. The control section is configured to control the switching section and the average processing section so as to compute the average measurement value for each of the measurement targets according to the timer signal and according to a measurement sequence to set an order of measurement and a number of measurements for the plural measurement targets.
A semiconductor device includes wiring that is formed by a conductive body extending, via an insulating film, on a front surface of a semiconductor substrate, and an insulating layer that covers the front surface of the semiconductor substrate including the wiring. Gaps are provided extending from an upper surface of the wiring to a lower portion of the insulating film.
A semiconductor device including a terminal that is formed using copper, that is electrically connected to a circuit element, and that includes a formation face formed with a silver-tin solder bump such that a nickel layer is interposed between the terminal and the solder bump, wherein the nickel layer is formed on a region corresponding to part of the formation face.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A display device has: a display panel; a source driver group including 2j source drivers that are arranged in the lengthwise direction of gate lines; and a display controller that is connected to the 2j source drivers via j data supply lines provided in common between adjacent pairs of source drivers. The display controller outputs j pixel data piece groups, into which m/2 pixel data pieces were divided, to the data supply lines. The (2k)th source driver receives m/(4j) pixel data pieces via a data supply line, and receives three pixel data pieces from the (2k+1)th source driver. The (2k)th source driver generates m/(2j) of gradation voltage signals on the basis of the pixel data pieces.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/3275 - Details of drivers for data electrodes
An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
An output circuit is provided. The disclosure includes: a positive polarity voltage signal supplying circuit configured to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit configured to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch formed from a P channel transistor of which a source and a back gate are connected to the first node and a drain is connected to a first output terminal; a second switch formed from an N channel transistor of which a source and a back gate are connected to the second node and a drain is connected to the first output terminal; and third and fourth switches.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
95.
Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
96.
Level voltage generation circuit, data driver, and display apparatus
A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
A signal transmission device and a battery monitoring device are provided. The signal transmission device is connected to an operation device including an operation circuit for performing an operation based on a first voltage, a measurement circuit for obtaining measurement data based on the first voltage, and a process control circuit for operating based on a lower voltage and control an operation of the operation circuit based on the measurement data, and transmits and receives signals between the process control circuit and the measurement circuit. The signal transmission device includes a power reception circuit for supplying power from the power transmission circuit to the measurement circuit to acquire measurement data, and a power transmission circuit for transmitting the power from a process control circuit to the power reception circuit to receive the measurement data from the power reception circuit and supply the same to the process control circuit.
B60L 1/00 - Supplying electric power to auxiliary equipment of electrically-propelled vehicles
B60L 3/00 - Electric devices on electrically-propelled vehicles for safety purposesMonitoring operating variables, e.g. speed, deceleration or energy consumption
H02G 3/00 - Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
98.
Source driver that adjusts a timing of outputting of pixel data based on a length of a source line, and display device
A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/3275 - Details of drivers for data electrodes
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
99.
Display driver suppressing color unevenness of liquid crystal display
The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
A semiconductor device constituting a non-volatile memory includes a semiconductor portion of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, an insulating film, and a conductive layer. The first well includes a trench extending from the surface of the semiconductor portion to an inside of the first well. The insulating film extends on a surface inside the trench. A conductive portion formed continuous with the conductive layer is disposed on the insulating film inside the trench.
