The invention describes the solid-state image sensor array and in particular describes in detail the junction gate BCMD pixel sensor array that can be used in the back side illuminated mode as well as in the front side illuminated mode. The pixels generally do not need addressing transistors and the reset is accomplished in a vertical direction to the junction gate, so no additional reset transistor is needed for this purpose. As a result of this innovation the pixel maintains large charge storage capacity when its size is reduced, has low noise due to the nondestructive charge readout, and no RTS noise. The pixel interface generated dark current is also drained to the gate, so the image sensor array operates with very low dark current noise even at high temperatures. The junction gate also serves as a drain for the overflow charge.
The invention describes a solid-state CMOS image sensor array and in particular describes in detail the image sensor array pixels, with global and rolling shutter capabilities, that utilize charge storage gates located on top of a pinned photodiode. The sensor array is illuminated from the back side and the location of the storage gate on top of the pinned photodiode saves valuable pixel area, which does not compromise the Dynamic Range of the image sensor.
A backside illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a front surface of a semiconductor substrate. Silicon inner microlenses may be formed on a back surface of the semiconductor substrate. In particular, positive inner microlenses may be formed over the photodiodes, whereas negative inner microlenses may be formed over the associated pixel circuits. Buried light shielding structures may be formed over the negative inner microlenses to prevent pixel circuitry that is formed in the substrate between two neighboring photodiodes from being exposed to incoming light. The buried light shielding structures may be lined with absorptive antireflective coating material to prevent light from being reflected off the surface of the buried light shielding structures. Forming buried light shielding structures with antireflective coating material can reduce optical pixel crosstalk and enhance global shutter efficiency.
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
An imager may include analog-to-digital converter circuitry that converts an analog input voltage to a digital output value by generating a number of samples of the analog input voltage. The analog input voltage may be formed from the difference between a pixel signal and a reference signal received at first and second inputs of the analog-to-digital converter circuitry. Processing circuitry may control the number of samples generated from the analog input voltage based on a desired gain level. The analog-to-digital converter circuitry may include a counter that counts to a maximum value. Ramp generation circuitry may generate a ramp signal based on the counter value and apply the ramp signal to the pixel signal at the first input of the analog-to-digital converter circuitry. The total time for generating samples for each different desired gain level may be constant while generating the ramp signal with a slope having a constant magnitude.
A fluid sample analyzing system may be formed from an image sensor integrated circuit substrate. A glass wafer may be used to cover a wafer of image sensors. The glass wafer and the image sensor wafer may be attached using oxide bonding. Fluid channels may be formed in a layer that is interposed between the image sensor wafer and the glass wafer. The layer may be deposited on the image sensor wafer and the glass wafer prior to oxide bonding. A spacer may be used to deliver the fluid channel layer to the image sensor wafer before the glass wafer is bonded to the image sensor wafer. The spacer may be formed from a silicon wafer. The silicon wafer may be bonded to the image sensor wafer and thinned, leaving a thin spacer wafer layer on the image sensor wafer in which fluid channels may be formed.
Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.
A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.
Electronic devices may be provided with image sensors. Image sensors may be configured to capture images during imaging operations and monitor ambient light levels during non-imaging operations. An image sensor may include image pixels that receive light and dark pixels that are prevented from receiving light. An image sensor may include an ambient light detection circuit. The ambient light detection circuit may include an oscillator, timing and control circuitry, and a counter. The oscillator may be switchably coupled to the image pixels and the dark pixels. The counter may be configured to count up oscillator cycles of the oscillator while the oscillator is coupled to the image pixels and to count down oscillator cycles of the oscillator while the oscillator is coupled to the dark pixels. The counter may provide a count value that depends on a signal from the image pixels and a signal from the dark pixels.
The invention describes a solid-state CMOS image sensor array and in particular describes in detail image sensor array pixels having global and rolling shutter capabilities that are using a dual channel transfer-storage gate for charge transfer from a PD to a TX gate well and from the TX gate well onto a FD. The dual channels are stacked above each other where a shallow charge channel is used to drain surface generated dark current away from the pixel structure, while a buried bulk channel provides for standard charge transfer and storage functions. This feature thus improves the sensor noise performance and prevents signal contamination and various shading effects caused by the dark current buildup during a prolonged charge storage sequence in pixels of image sensor arrays using the global shutter mode of operation. Several embodiment of this concept are described including pixels which utilize shared circuitry, a complete PD reset capability, and an efficient anti-blooming control.
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
10.
Image sensor pixels with junction gate photodiodes
Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.
An image sensor pixel (200) suitable for use in a back-side-illuminated or a front-side-illuminated sensor arrangement is provided. The image sensor pixel may be a small size pixel that includes a source fol¬ lower (300) implemented using a vertical junction field effect (JFET) transistor. The vertical JFET source follower may be integrated directly into the floating diffusion node (302), thereby eliminating excess metal routing and pixel area typically allocated for the source follower in conventional pixel configurations. Pixel area may instead be al¬ located for increasing the charge storage capacity of the photodiode (207) or can be used to reduce pixel size while maintaining pixel performance. Using a vertical junction field effect transistor in this way simplifies pixel addressing operations and minimizes random telegraph signal (RTS) noise associated with small size metal-oxide-semiconductor (MOS) transistors.
A backside illumination (BSI) image sensor pixel that includes microlenses with elevated refractive indices is provided. The image sensor pixel may include a photodiode formed in a silicon substrate, a first microlens formed in a back surface of the substrate, a second microlens formed over a front surface of the substrate, a dielectric stack formed on the front surface of the substrate, and a reflective structure formed in the dielectric stack above the second microlens. The first microlens may be fabricated by forming shallow trench isolation structures in the back surface. The second microlens may be fabricated by depositing polysilicon on the front substrate of the substrate. The first microlens may serve to concentrate light towards the photodiode, whereas the second microlens may serve to collimate light that traverses through the substrate so that light exiting the second microlens will reflect off the reflective structure and back into the photodiode.
A backside illumination (BSI) image sensor pixel (200) that includes microlenses (216, 226) with elevated refractive indices is provided. The image sensor pixel may include a photodiode (208) formed in a silicon substrate (202), a first microlens (216) formed in a back surface (206) of the substrate, a second microlens (226) formed over a front surface (204) of the substrate, a dielectric stack (223) formed on the front surface of the substrate, and a reflective structure (250) formed in the dielectric stack above the second microlens. The first microlens may be fabricated by forming shallow trench isolation structures (214) in the back surface. The second microlens may be fabricated by depositing polysilicon on the front substrate of the substrate. The first microlens may serve to concentrate light towards the photo-diode, whereas the second microlens may serve to collimate light that traverses through the substrate so that light exiting the second microlens will reflect off the reflective structure and back into the photo-diode.
Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source- follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.
Electronic devices may include imaging systems with camera modules and light sources. A camera module may be used to capture images while operating one or more light sources. Operating the light sources may generate changing illumination patterns on surfaces of objects to be imaged. Images of an object may be captured under one or more different illumination conditions generated using the light sources. Shadow patterns in the captured images may change from one image captured under one illumination condition to another image captured under a different illumination condition. The electronic device may detect changes in the shadow patterns between multiple captured images. The detected changes in shadow patterns may be used to determine whether an object in an image is a planar object or an object having protruding features. A user authentication system in the device may permit or deny access to the device based, in part, on that determination.
Electronic devices may include image sensors. Image sensors may be used to capture images having rows of long-exposure image pixel values that are interleaved with rows of short-exposure image pixel values. The long-exposure and short-exposure values in each interleaved image frame may be interpolated to form interpolated values. A combined long-exposure image and a combined short-exposure image may be generated using the long-exposure and the short-exposure values from the interleaved image frames and the interpolated values from a selected one of the interleaved image frames. The combined long-exposure and short-exposure images may each include image pixel values from either of the interleaved image frames in a non-motion edge region and image pixel values based only on the image pixel values or the interpolated values from the selected one of the interleaved images in a motion or non-edge region. High-dynamic-range images may be generated using the combined long-exposure and short-exposure images.
Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits.
H04N 5/345 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by partially reading an SSIS array
18.
Self test of image signal chain while running in streaming mode
An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.
Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.
H04N 5/345 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by partially reading an SSIS array
An electronic device may have a camera module. The camera module may include a camera sensor divided into two or more regions. The various regions of the camera sensor may include lenses that filter different polarizations of incident light. As one example, a first half of the camera sensor may include a lens that passes unpolarized light to the first half of the camera sensor, while a second half of the camera sensor may include a lens that passes light of a particular polarization to the second half of the camera sensor. If desired, the camera sensor may include microlenses over individual image sensing pixels. Some of the microlenses may select for particular polarizations of incident light. The electronic device may include a component that emits structured or polarized light and the camera sensor may have lenses that are mapped to the light emitted by the component.
Row-control signal monitoring system for an electronic imager includes signal processing circuitry coupled a pixel array of the electronic imager which receives at least one row control signal from the pixel array and provides an output signal corresponding to the selected row control signal. Monitoring circuitry compares the output signal to a target value to test the at least one row-control signal.
Imaging systems may be provided with image sensors for capturing images. An Image sensor may include storage and processing circuitry having a conferral image buffer to be used in performing various types of image transformations on captured input images, The storage and processing circuitry may perform the image transformations in part, by storing a portion of a captured input image in the conformal image buffer, A conformal image buffer may include a buffer for storing input image pixel values specific to various types of image transformations and memory for storing a pixel buffer lookup fable, The pixel buffer lookup table may be used bv the storage and processing circuitry to determine which input image pixel values should be stored in the conformal image buffer for each type of image transformation and to provide random read access to the stored input image pixel values in the conformal image buffer.
H04N 5/345 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by partially reading an SSIS array
An electronic device may have a camera module. The camera module may include a camera sensor capable of capturing foveated images. The camera sensor may be hardwired to capture foveated images with fixed regions of different quality levels or may be dynamically-reconfigurable to capture foveated images with selected regions of different quality levels. As one example, the camera module may be hardwired to capture a center region of an image at full resolution and peripheral regions at reduced resolutions, so that a user can merely center objects of interest in the image to capture a foveated image. As another example, the camera module may analyze previous images to identify objects of interest and may then reconfigure itself to capture the identified objects of interest at a high quality level, while capturing other regions at reduced quality levels.
H04N 5/347 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by combining or binning pixels in SSIS
Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H04N 5/345 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by partially reading an SSIS array
Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
26.
Comparator noise reduction by means of a programmable bandwidth
A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.
Electronic devices may include super-resolution imaging systems for capturing multiple relatively low-resolution images and combining the captured images to form a high-resolution image. The imaging system may include image sensors configured to capture information above the Nyquist frequency of the image sensor by providing each image sensor pixel in an array of image sensor pixels with structures for reducing the size of the clear pixel aperture below the size of the image sensor pixel. The structures may be configured to pass light that is incident on a central region of the image sensor pixel to a photo-sensitive element through a color filter element and to reject light that is incident on a surrounding edge region. The structures may include a microlens configured to reject light that is incident on the edge region or a combination of a microlens and masking structures. Masking structures may be absorbing, reflecting, or interfering structures.
An integrated circuit may contain image sensor pixels. Channels ( 16 ) containing a fluid with samples such as cells may be formed on top of the image sensor ( 302 ). Control circuitry ( 17 ) may be formed on the integrated circuit. The image sensor pixels may form light sensors and imagers. Portions of the channel may have multiple chambers ( 66 ) such as fluorescence detection chambers. Gating structures and other fluid control structures may control the flow of fluid through the channels and chambers. Portions of the channel may be used to form chambers. The chambers may each be provided with one or more light sensors, light sources ( 76 ), and color filters to alter the color of illumination form a light source, one or more reactants such as dyes, antigens, and antibodies, and heaters. The control circuitry may be configured to control the imagers, the gating structures, the fluid control structures, the light source, the heaters, etc.
Imaging systems may be provided with image sensors and verification circuitry. Verification circuitry may be configured to continuously verify proper operation of the image sensor during operation. Verification circuitry may include one or more heating elements formed on a common substrate with image pixels of the image sensor. Verification data may be generated by powering on the heating elements and collecting charges generated in image pixels of the image sensor in response to heat generated by the powered heating element. Heat image charges may be read out using the same readout circuitry that is used to readout imaging data generated in response to incoming light. Heat image data may be used to verify proper operation of all components of an imaging system. Based on a comparison of the verification data with a predetermined standard, an imaging system may continue to operate normally or corrective action may be taken.
Imaging systems may be provided with image sensors having verification circuitry. Verification circuitry may be configured to verify proper operation of the image sensor during operation. Verification circuitry may include one or more switchable voltage contacts configured to generate a voltage drop across a power supply network of a pixel array during verification operations. Verification circuitry may include a controllable voltage supply coupled to the power supply network of the pixel array. Verification image data may be generated by applying the voltage drop or by using the controllable voltage supply to supply a different supply voltage to each row of pixels prior to readout of that row. Verification image data may be read out using the same circuitry that is used to readout imaging data. Based on a comparison of the verification data with a predetermined standard, imaging systems may continue to operate normally or corrective action may be taken.
An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a “golden” image or other predetermined set of expected output signals.
Imaging systems may be provided with image sensors having verification circuitry. Verification circuitry may be configured to continuously or occasionally verify that the image sensor is functioning properly. For example, verification circuitry may be configured to monitor levels of leakage current during standby mode. Verification circuitry may be coupled between a power supply and circuitry that is powered by that power supply. When the imaging system is in standby mode, circuitry associated with the imaging system such as pixel circuitry may draw a standby leakage current. Verification circuitry may be configured to measure the amount of standby leakage current drawn by associated imaging system circuitry. If the measured level of standby leakage current exceeds a maximum acceptable level of standby leakage current, a warning signal may be generated. Standby leakage current levels on multiple power supply lines may be monitored with associated verification circuitry.
An image sensor may be provided in which a pixel array includes imaging pixels and application-specific pixels. The application-specific pixels may include depth-sensing pixels, infrared imaging pixels, or other types of application-specific pixels. A color filter array may be formed over the pixel array. The color filter array may include Bayer color filter array formed over the imaging pixels. The color filter array may also include a plurality of green color filter elements formed over the application-specific pixels. Barrier structures may be interposed between imaging pixels and application-specific pixels. The barrier structures may be configured to reduce or eliminate optical crosstalk between imaging pixels and adjacent application-specific pixels. The barrier structures may include an opaque photodefinable material such as black or blue photodefinable material that may be configured to filter out wavelength bands of interest. The barrier structures may be formed during the color filter array fabrication process.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
Imaging systems may be provided with image sensors having verification circuitry. Verification circuitry may be configured to verify proper operation of the image sensor during operation. Verification circuitry may include one or more switchable voltage contacts configured to generate a voltage drop across a power supply network of a pixel array during verification operations. Verification circuitry may include a controllable voltage supply coupled to the power supply network of the pixel array. Verification image data may be generated by applying the voltage drop or by using the controllable voltage supply to supply a different supply voltage to each row of pixels prior to readout of that row. Verification image data may be read out using the same circuitry that is used to readout imaging data. Based on a comparison of the verification data with a predetermined standard, imaging systems may continue to operate normally or corrective action may be taken.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
35.
IMAGING SYSTEMS WITH DIGITALLY CONTROLLED ANALOG OFFSET COMPENSATION
An Image sensor may be provided that includes an image pixel array, analog column circuitry and digital column circuitry. The digital column circuitry may extract a systematic analog signal offset from data received from the analog column circuitry. The digital column circuitry may generate analog signal offset correction values based on the systematic analog signal offsets and provide the analog signal offset correction values to the analog column circuitry. The analog column circuitry may remove signal offsets from subsequently read out image data from, the image pixel array using the analog signal offset correction values provided by the digital column circuitry. The image pixel array may include image pixels having color filters of various colors. The digital column circuitry may generate analog signal offset correction values corresponding to each of the various colors.
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
36.
METHOD AND APPARATUS FOR ARRAY CAMERA PIXEL READOUT
Imaging systems may include camera modules that include an array of image sensors. An image sensor may include multiple image pixel arrays arranged in rows and columns, multiple control circuits for operating the image pixels of that image sensor, and shared readout circuitry for reading out the image pixels of the image pixel arrays of that image sensor. Each control circuit may be operable to select rows of image pixels that extend across a row of image pixel arrays. Shared readout circuitry may include one or more line buffers configured to temporarily store image data captured by image pixels in the selected rows of image pixels. Shared readout circuitry may include selection circuitry configured to readout image data from groups of associated pixels located in separate image pixel arrays. An imaging system may include processing circuitry for processing the image data from each group of pixels.
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to an active and an inactive current supply circuit. Each active current supply circuit may form a portion of a current mirror circuit that includes a common current source and a common input transistor. Each active current supply circuit may include a mirror transistor for mirroring current that flows through the common input transistor and a permanently enabled enabling transistor for activating that mirror transistor. Mirrored current that flows through a particular active mirror transistor may be supplied to image pixels in the pixel column associated with that particular mirror transistor. Each inactive current supply circuit may include a mirror transistor coupled to the input transistor and a permanently disabled enabling transistor.
H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 5/367 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response applied to defects, e.g. non-responsive pixels
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors
38.
COLOR IMAGING USING TIME-MULTIPLEXED LIGHT SOURCES AND MONOCHROME IMAGE SENSORS WITH MULTI-STORAGE-NODE PIXELS
Electronic devices may include monochrome image sensors having multi-storage-node image sensor pixels (190). A multi-storage-node image pixel may be synchronized with artificial light sources of different colors and may include a floating diffusion region (126) and multiple storage regions. The image pixels may be sequentially exposed to each light color and may store charge associated with each color in each of the different storage regions. After exposure, the stored charge may be transferred to the floating diffusion region and subsequently read out using readout circuitry (142). The image pixel may have one set of storage gates (145-1, 145-2, 145-3, 145-4) that can perform both storage and transfer functions. Alternatively, the image pixel may have a first set of transfer gates for transferring charge to the storage regions and a second set of transfer gates for transferring charge from the storage regions to the floating diffusion region.
An image sensor may be provided that includes an image pixel array, analog column circuitry and digital column circuitry. The digital column circuitry may extract a systematic analog signal offset from data received from the analog column circuitry. The digital column circuitry may generate analog signal offset correction values based on the systematic analog signal offsets and provide the analog signal offset correction values to the analog column circuitry. The analog column circuitry may remove signal offsets from subsequently read out image data from the image pixel array using the analog signal offset correction values provided by the digital column circuitry. The image pixel array may include image pixels having color filters of various colors. The digital column circuitry may generate analog signal offset correction values corresponding to each of the various colors.
H04N 9/64 - Circuits for processing colour signals
H04N 5/217 - Circuitry for suppressing or minimising disturbance, e.g. moire or halo in picture signal generation
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
40.
METHOD AND APPARATUS FOR VERIFICATION OF IMAGING SYSTEMS
Imaging systems may be provided with image sensors and verification circuitry. Verification circuitry may be configured to continuously verify proper operation of the image sensor during operation. Verification circuitry may include one or more heating elements formed on a common substrate with image pixels of the image sensor. Verification data may be generated by powering on the heating elements and collecting charges generated in image pixels of the image sensor in response to heat generated by the powered heating element. Heat image charges may be read out using the same readout circuitry that is used to readout imaging data generated in response to incoming light. Heat image data may be used to verify proper operation of all components of an imaging system. Based on a comparison of the verification data with a predetermined standard, an imaging system may continue to operate normally or corrective action may be taken.
Imaging systems may be provided with image sensors having verification circuitry. Verification circuitry may be configured to continuously or occasionally verify that the image sensor is functioning properly. For example, verification circuitry may be configured to monitor levels of leakage current during standby mode. Verification circuitry may be coupled between a power supply and circuitry that is powered by that power supply. When the imaging system is in standby mode, circuitry associated with the imaging system such as pixel circuitry may draw a standby leakage current. Verification circuitry may be configured to measure the amount of standby leakage current drawn by associated imaging system circuitry. If the measured level of standby leakage current exceeds a maximum acceptable level of standby leakage current, a warning signal may be generated. Standby leakage current levels on multiple power supply lines may be monitored with associated verification circuitry.
An imaging system may include an array of image pixels. The array of image pixels may be provided with one or more rows and columns of optically shielded dark image pixels. The dark image pixels may be used to produce verification image data that follows the same pixel-to-output data path of light-receiving pixels. The output signals from dark pixels may be continuously or intermittently compared with a set of expected output signals to verify that the imaging system is functioning properly. In some arrangements, verification image data may include a current frame number that is encoded into the dark pixels. The encoded current frame number may be compared with an expected current frame number. In other arrangements, dark pixels may be configured to have a predetermined pattern of conversion gain levels. The output signals may be compared with a "golden" image or other predetermined set of expected output signals.
A microfluidic system may include an image sensor integrated circuit containing image sensor pixels. A channel containing a fluid with particles such as cells may be formed on top of the image sensor. Flow control components may be mounted to the image sensor integrated circuit for controlling the flow of fluids through the channel. The flow control components may include a chemically powered pump. The chemical pump may include one or more chambers and a valve between the chambers. The valve may be operable to allow chemical reactants stored in the chambers to be mixed to produce gasses for generating pressure in the channel. The pressure in the channel may be used to control the flow of the fluid. As the fluid and particles flow through the channel, the image sensor pixels may be used to capture images of the particles.
Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.
An image sensor may be provided in which a pixel array includes imaging pixels and application-specific pixels. The application-specific pixels may include depth-sensing pixels, infrared imaging pixels, or other types of application- specific pixels. A color filter array may be formed over the pixel array. The color filter array may include Bayer color filter array formed over the imaging pixels. The color filter array may also include a plurality of green color filter elements formed over the application-specific pixels. Barrier structures may be interposed between imaging pixels and application-specific pixels. The barrier structures may be configured to reduce or eliminate optical crosstalk between imaging pixels and adjacent application- specific pixels. The barrier structures may include an opaque photodefinable material such as black or blue photodefinable material that may be configured to filter out wavelength bands of interest. The barrier structures may be formed during the color filter array fabrication process.
An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes.
An electronic device may be provided with imaging modules or communications modules. Imaging modules and communications modules may be improved with the use of plasmonic light collectors. Plasmonic light collectors exploit the interaction between incoming light and plasmons in the plasmonic light collector to redirect the path of the incoming light. Plasmonic light collectors may be used to form lenses for image pixels in an imaging module or to form light pipes or lenses for use in injecting optical communications into a fiber optic cable. Plasmonic lenses may be formed by lithography of metallic surfaces, by implantation or by stacking and patterning of layers of materials having different dielectric properties. Plasmonic image pixels may be smaller and more efficient than conventional image pixels. Plasmonic light guides may have significantly less signal loss than conventional lenses and light guides.
Electronic devices may be provided with imaging modules that include plasmonic light collectors. Plasmonic light collectors may be configured to exploit an interaction between incoming light and plasmons in the plasmonic light collector to alter the path of the incoming light. Plasmonic light collectors may include one or more spectrally tuned plasmonic image pixels configured to preferentially trap light of a given frequency. Spectrally tuned plasmonic image pixels may include plasmonic structures formed form a patterned metal layer over doped silicon layers. Doped silicon layers may be interposed between plasmonic structures and a reflective layer. Plasmonic image pixels may be used to absorb and detect as much as, or more than, ninety percent of incident light at wavelengths ranging from the infrared to the ultraviolet. Plasmonic image pixels that capture light of different colors may be arranged in patterned arrays to form imager modules or imaging spectrometers for optofluidic microscopes.
Methods and devices that incorporate microlens arrays are disclosed. An image sensor includes a pixel layer and a dielectric layer. The pixel layer has a photodetector portion configured to convert light absorbed by the pixel layer into an electrical signal. The dielectric layer is formed on a surface of the pixel layer. The dielectric layer has a refractive index that varies along a length of the dielectric layer. A method for fabricating an image sensor includes forming an array of microlenses on a surface of the dielectric layer, emitting ions through the array of microlenses to implant the ions in the dielectric layer, and removing the array of microlenses from the surface of the dielectric layer.
Double pass back side image (BSI) sensor systems and methods are disclosed. The BSI sensor may include a substrate, pixel reflectors formed on the substrate, and pixel photodiodes fabricated in the substrate, each pixel photodiode positioned over a respective one of the pixel reflectors. Micro-lenses may be formed over each photodiode and an image filter may be formed between the photodiodes and the micro-lenses. The pixels reflectors, photodiodes, micro-lenses, and filter may be formed using CMOS fabrication.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
A compact image sensor for imaging radiation emitted by fluorescing objects exposed to excitation light is disclosed. The compact image sensor includes a light guide defining a longitudinal axis for channeling radiation emitted by the fluorescing object; a reflective surface defined on the light guide that is oriented at an angle with respect to the longitudinal axis of the light guide to reflect the excitation light away from a detector of the image sensor; and the detector positioned at an end of the light guide for imaging radiation emitted by the fluorescing object. Also disclosed is a fluorescence imaging system for imaging radiation emitted by a fluorescing object to be imaged by compact image sensor and a method of fluorescence imaging.
An imager includes an array of pixels arranged in rows and a control circuit for sequentially capturing first and second image frames from the array of pixels. The control circuit is configured to sequentially capture first and second pairs of adjacent rows of pixels during first and second exposure times, respectively, when capturing the first image frame. The control circuit is also configured to sequentially capture first and second pairs of adjacent rows of pixels during second and first exposure times, respectively, when capturing the second image frame. The first exposure times during the first and second frames are of similar duration; and the second exposure times during the first and second frames are of similar duration. The control circuit is configured to detect motion of an object upon combining the first and second image frames and, then, correct for the motion of the object.
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
Systems and methods for generating efficient transformed input image address sets for producing a multi-pane output image from an input image are disclosed. The input address sets may be generated by applying a first transformation corresponding to one pane of the output image to output pixel addresses to create first transformed input addresses, applying a second transformation corresponding to another pane to the output image pixel addresses to create second transformed input addresses, and storing, for one output pixel address, a first transformed image pixel address and a second transformed input pixel address and, for another output pixel address, including a first transformed input pixel address, but no second transformed address.
The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.
Online ordering systems allow a user to submit sensitive information such as payment card information to a merchant in encrypted form. A payment card processor server may be used to provide the user's web browser with code for an encryption function, a cryptographic key, and a key identifier. The web browser may encrypt the payment card information by executing the encryption function and using the key. The encrypted payment card information may be supplied to the merchant over the internet. A key identifier that identifies which cryptographic key was used in encrypting the payment card information may be provided to the merchant without providing the merchant with access to the key. The merchant can forward the encrypted payment card information to the credit card processor server with the key identifier. The processor server can use the key identifier to obtain the key and decrypt the payment card information for authorization.
Disclosed herein is a stacked chip package including an image sensor including a recess formed on a surface thereof, and a digital signal processor chip that is positioned within the recess. Also disclosed herein is a method of fabricating a stacked chip package including the steps of forming a recess on a surface of an image sensor and positioning a digital signal processor in the recess of the image sensor.
A hologram projecting system includes a coherent light source for emitting a reference beam onto a real object; and an image sensor for receiving the reference beam and a scattered beam reflected from the real object, and recording a Fourier image of the real object. Also included is a modulator for receiving the Fourier image. The reference beam is passed through the modulator, and configured to interact with the Fourier image to form a virtual image of the real object. The image sensor includes an n×m pixel array, where n and m are numbers of rows and columns, respectively. The modulator includes an n×m pixel array corresponding to the n×m pixel array of the image sensor. The pixels in the n×m pixel array of the image sensor control transmissivity of light in corresponding pixels of the n×m pixel array of the modulator.
A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
Dual conversion gain pixel methods, system, and apparatus are disclosed. Dual conversion gain may be obtained by configuring an active pixel having a storage node, a first connection region, a second connection region, and a capacitor coupled between the storage node and the second connection region to introduce a first conversion gain by connecting the first connection region to a power source and connecting the second connection region to a current bias source and reconfiguring the active pixel to introduce a second conversion gain by connecting the second connection region to the power source and connecting the first connection region to the current bias source.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
60.
Image sensor array for back side illumination with global shutter using a junction gate photodiode
The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.
Apparatus and a method for generating a rectified image. First pixel information corresponding to a first image is received from a first imager. Second pixel information corresponding to a second image is received from a second imager. A plurality of facial feature points of a portrait in each of the first and second images are identified. A fundamental matrix is generated based on the detected facial features. An essential matrix is generated based on the fundamental matrix. Rotational and translational information corresponding to the first and second imagers are generated based on the essential matrix. The rotational and translational information are applied to at least one of the first and second images to generate at least one rectified image.
A method of processing an image includes the steps of separating an image into multiple color channels, and dividing the image into multiple zones, in which each zone includes a sub-array of pixels. The method then calculates a color shading profile for each zone. The color shading profile is calculated as a linear function, typically a straight line. If a linear function cannot be determined for that zone, the method interprets a function for that zone using the nearest zone neighbors. The method corrects the color shading using the functions calculated for the respective zones.
A method of classifying pixels in an image is described that includes calculating for each target pixel in the image, a functional value based on a median value of a block of pixels including the target pixel and storing the functional value for each pixel. Pixels in the image are then analyzed to determine if they correspond to edges in the image and if so, are classified as edge pixels. Next the stored functional values are analyzed to define a flat area delimiting function for the image. The stored functional values that do not correspond to edge pixels are then analyzed to define an image detail delimiting function and the non-flat area pixels are classified as being either flat area pixels or detail pixels based on the flat area delimiting function and the detail delimiting function.
A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
65.
Blooming filter for multiple exposure high dynamic range image sensors
Multiple-exposure high dynamic range image processing may be performed that filters pixel values that are distorted by blooming from nearby saturated pixels. Pixel values that are near saturated pixels may be identified as pixels that may be affected by blooming. The contributions from those pixels may be minimized when producing a final image. Multiple-exposure images may be linearly combined to produce a final high dynamic range image. Pixel values that may be distorted by blooming may be given less weight in the linear combination.
An imaging system may include imaging pixels. Each imaging pixel may include a reset transistor and a dummy transistor coupled to a floating diffusion storage node. When reset signals control are deasserted, capacitive coupling between the gate terminal of the reset transistor and the source-drain terminals of the reset transistor may lead to reset charge injection. The dummy transistor may have both of its source-drain terminals shorted together and shorted to the floating diffusion region. Dummy control signals, which may be provided by separate dummy control lines or may be provided using row-select signals, may be asserted on the dummy transistors at approximately the same time that the reset signals are deasserted. With arrangements of this type, the dummy control signals may inject an approximately equal and opposite charge onto the floating diffusion region, thereby reducing the reset charge injection caused by deasserting the reset control signals.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
H04N 5/217 - Circuitry for suppressing or minimising disturbance, e.g. moire or halo in picture signal generation
This describes color filter arrangements for image sensor arrays that are formed using image sensor pixels with stacked photo-diodes. The stacked photo-diodes may include first and second photo-diodes and may have the ability to separate color signal according to the depth of carrier generation in a silicon substrate. A single color filter may be formed over the stacked photo-diodes to provide full red-green-blue sensing capability. Charge drain regions may also be formed at different depths in the silicon substrate. If the charge drain regions are formed beneath the stacked photo-diodes in the substrate, full red-green-blue color sensing may be achieved without the use of color filters.
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
A light-based input device may have multiple branches each based on a respective light-guide structure. A light source may launch light into the light-guide structures. A light sensor may detect light reflected from the light-guide structures or transmitted through the light-guide structures. The light-based input device may be used to gather user input from a user of an electronic device. The user may move an object into contact with the light-guide structures. The light sensor may monitor light intensity fluctuations from the light-guide structures to determine where the light-guide structures have been contacted by the object. Multiple wavelengths of light may be used by the light source and light sensor to reduce crosstalk between adjacent branches of the light-based input device.
An imager may be configured to perform pixel binning on captured images. Pixel binning may be performed by forming groups of pixels and combining sampled values from the pixels in each group. The sampled values from the pixels may be combined by assigning weights to each pixel, scaling the sampled values by the corresponding weights, and summing the scaled values. The groups of pixels and pixel weights may be selected to produce binned images with even spatial distribution. The pixel binning operation may be performed by processing circuitry that receives captured image data from the imager. The pixel binning operation may also be separated into a horizontal binning step and a vertical binning step that are performed by image readout circuitry during image readout. During the horizontal binning step, pixels of a particular row may be combined. During the vertical binning step, pixel rows may be combined.
H04N 9/083 - Picture signal generators with one pick-up device only whereby the colour signals are characterised by their frequency
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns.
Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer.
Electronic devices may include image sensors and processing circuitry. Image sensors may be used to capture multiple exposure images. Processing circuitry may be used to combine multiple exposure images into high-dynamic-range images. A motion correction method is provided that detects motion between multiple exposure images without using a frame buffer. A noise model is used to separate noise from motion for more accurate motion detection. A dilation operator may be used to enlarge a motion mask generated by the motion detector. Motion-corrected images may be generated from the multiple exposure images using a soft switch based on the motion strength. Motion-corrected multiple exposure images may be combined to generate a motion-corrected HDR image. A smoothing filter may be applied to the motion region of the motion-corrected HDR image. A blooming correction may be used to eliminate color artifacts in the motion-corrected HDR image.
An electronic device may have an image sensor for capturing digital image data of a scene. The image sensor may have an array of image sensor pixels. The image sensor pixels may have photosensitive elements for capturing image data signals. The image data signal from each photosensitive element may be conveyed to an output line associated with a column of the array using a source-follower transistor. The source-follower transistors may be provided with a current bias using current source coupled to each output line. The current source may include a configurable current source transistor that has multiple branches that can be selectively switched into use to adjust transconductance and drain saturation voltage characteristics for the current source. Gate structures in the configurable current source transistor may be supplied with a reference voltage from an adjustable voltage reference circuit.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
74.
Flicker detection for imaging devices with high frame rates
Common electronic devices having imaging systems that use a rolling shutter scheme suffer from flicker due to the oscillating brightness of an illuminating light source. Some imaging systems use fast frame rates that result in less than two cycles of the illuminating light source occurring during a single frame capture. For devices that employ rolling shutter schemes and fast frame rates, a method of data collection and processing is provided that utilizes a combination of multiple sets of more than two image data frames to automatically detect flicker. Measured patterns of energy differences between various image frames and a reference image frame may be compared with an expected pattern of energy differences to determine a probability of flicker detection due to a given flicker frequency. This probability of flicker detection may be used to activate flicker avoidance procedures in an electronic device.
H04N 9/73 - Colour balance circuits, e.g. white balance circuits or colour temperature control
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
75.
Systems and methods for synchronizing and controlling multiple image sensors
An Electronic device may include a master camera module, a slave camera module, and host subsystems. The master camera module may control some of the operations of the slave camera module. The master camera module may transmit data to the slave camera module. The master camera module may interrupt data transmission to the slave camera module, when a delay-sensitive event occurs, to transmit information corresponding to the delay-sensitive event. The slave camera module may respond to the event information with a predetermined fixed delay relative to the occurrence of the event at the master camera module.
Apparatus and a method for processing image data where row data is received corresponding to a target row of pixels and to one or more reference rows of pixels. A target row average is generated based on the target row data and a reference row average is generated for each of the one or more reference rows based on each reference row's respective row data. A row correction value is generated based on the target row average of the target row and the reference row average of the one or more reference rows. Corrected target row data is generated by applying the row correction value to the target row data.
Electronic devices may include camera modules. A camera module may include an array camera having an array of lenses and an array of corresponding image sensors. Parallax correction and depth mapping methods may be provided for array cameras. A parallax correction method may include a global and a local parallax correction. A global parallax correction may be determined based on one-dimensional horizontal and vertical projections of edge images. Local parallax corrections may be determined using a block matching procedure. Further improvements to local parallax corrections may be generated using a relative block color saturation test, a smoothing of parallax correction vectors and, if desired, using a cross-check between parallax correction vectors determined for multiple image sensors. Three dimensional depth maps may be generated based on parallax correction vectors.
The present invention relates to an imager for improving image quality. The imager includes a pixel array of a plurality of pixels arranged in rows and columns. The imager also includes a color filter array (CFA) including a color pattern of a first color filter allowing a first pixel to detect a first color of light, and a second color filter allowing a second pixel to detect a second color of light and a third color of light. Each of the color filters in the color pattern are included in each row of the pixel array.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
Electronic devices may include camera modules. A camera module may be formed from an array of lenses and corresponding image sensors. The array of image sensors may include three color image sensors for color imaging and a fourth image sensor positioned to improve image depth mapping. Providing a camera module with a fourth image sensor may increase the baseline distance between the two most distant image sensors, allowing parallax and depth information to be determined for objects a greater distance from the camera than in a conventional electronic device. The fourth image sensor may be a second green image sensor positioned at a maximal distance from the green color image sensor used for color imaging. The fourth image sensor may also be a clear image sensor, allowing capture of improved image depth information and enhanced image resolution and low-light performance.
Systems and methods for multi-exposure imaging are provided. Multiple images may be captured having different exposure times. The multiple images may be processed to produce an output image. Multi-exposure images may be summed prior to linearization. Pixel values in multi-exposure images may be summed to nonlinear pixel values. The nonlinear pixel values may be linearized using one or more knee points. Multi-exposure imaging may be used to motion-intensive application such as automotive applications.
Image sensors may contain arrays of image sensor pixels, each of which includes a microlens and a photosensitive element. A multisection light guide that is made up of multiple light guide layers may be interposed between the microlens and the photosensitive element. The light guide layers may have alternating indicies of refraction to form a spectral filter. The lateral dimensions of the light guide layers may also be configured so that the light guide layers perform spectral filtering. Light guide shapes and sizes may be altered as a function of the lateral position of each image sensor pixel within the image sensor array. The uppermost light guide may be aligned with the microlens and the lowermost light guide may be aligned with the photosensitive element. The lateral positions of each light guide may be laterally shifted with respect to the next to form a staggered stack of light guides.
H04N 9/083 - Picture signal generators with one pick-up device only whereby the colour signals are characterised by their frequency
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H01L 31/0232 - Optical elements or arrangements associated with the device
82.
Imaging system with multiple sensors for producing high-dynamic-range images
An electronic device may have an array of image sensors that capture image data using different exposure times. Processing circuitry may be used to combine image data with a first exposure time and image data with a second exposure time to create a high-dynamic-range image. The image sensors may use electronic rolling shutter and global shutter image capture schemes. Using the electronic rolling shutter scheme, the reset signals for each sensor may be staggered and the read signals for each sensor may be aligned to allow synchronized readout from the image sensors. When using the global shutter scheme, image capture operations associated with a shorter exposure time may be centered in time within image capture operation associated with a longer exposure time to minimize motion artifacts. Multiple image sensors may also be used to capture short-exposure-time data that is spaced evenly in time within the longer exposure time data.
Apparatus and a method for performing neutral density filtering in a digital camera. The camera includes a pixel array having rows and columns of pixels. The pixels in the array may be reset and read with variable timing between the reset operation and the read operation. The timing between the reset and read operations is controlled to implement a neutral density filtering operation.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
84.
System and method for biasing analog circuitry in a distributed power delivery network for image sensors and other circuit structures
A distributed power supply delivery network includes an analog biased circuit array having current sources for delivering current to adjacent circuits, and a resistive ladder of resistor elements, where each resistor element is disposed between adjacent current sources. A tuned IR voltage drop network is included to match voltage drops across the resistive ladder. The tuned IR voltage drop network includes series connected resistors and a static current draw to induce the IR drop. The resistors may be matched with respect to the distributed power supply delivery system. The current source providing the static current for the IR drop may be programmed based on the power supply delivery load, in order to adjust the voltage drop across the biasing delivery route and match the voltage drop in the referenced power supply.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
An integrated circuit may have rows and columns of imaging pixel arrays. Row driver circuitry and column readout circuitry may be shared between the imaging pixel arrays. Control circuit blocks may bypass inactive pixel arrays and may shift signals between different signal paths on the integrated circuit. The control circuit blocks may include synchronizing circuitry for deskewing control signals and buffer circuitry for regenerating weak signals as they are distributed across the integrated circuit. An array of lenses may be associated with the integrated circuit. The spacing between imaging pixel arrays may differ at different parts of the integrated circuit. Images from multiple image sensor pixel arrays may be combined to form a single digital image. Image sensors may be provided with unique lenses, different color responses, different image pixels, different image pixel patterns, and other differences. Reference pixels may be interposed in the gaps between image sensor arrays.
High-dynamic-range images may be produced by combining multiple integration periods of varying duration, wherein each integration is obtained using a global shutter operation. Charge accumulated during a first integration period may be stored on a first storage node while charge accumulated during a second and third integration time are carried out. Storage of charges accumulated during the second and third integration periods on a second storage node within a pixel while charge is stored on the first storage node allows capture of a global-shutter-based, high-dynamic-range image. A global-shutter-based image capture base on at least three integration time periods may provide enhanced dynamic range.
Imaging systems with image sensors and image processing circuitry are provided. The image processing circuitry may calculate sharpness values for a window within an image captured by the image sensors. The window may be divided into zones. A first filter may be applied to each row of each zone. A first sharpness value may be calculated by averaging the absolute values of the outputs of the first filter that are greater than a first threshold. A second sharpness value may be calculated by averaging the absolute values of the outputs of the second filter that are greater than a second threshold. A final sharpness value for each zone may be calculated by dividing the second sharpness value by the first sharpness value and multiplying the result by corresponding scalar weights. A window sharpness value may be calculated from the weighted sum of the final sharpness values of each zone.
An array camera may be formed from an array of lenses, an array of corresponding apertures, and an array of corresponding image sensors. The array of apertures may be configured so that some image sensors receive light through apertures of different size than other image sensors. Providing apertures of smaller size increases the F/# of an array camera and increases the depth-of-field in a captured image. The array of image sensors may include a near-infrared image sensor. Providing an image sensor array with a near-infrared image sensor may enhance depth information in captured images or increase night vision capabilities of an array camera. Combining an array of image sensors that includes a near-infrared sensor with an array of apertures having different aperture diameters may allow increased depth-of-field imaging, enhanced extraction of depth information from an image, improved night vision, enhanced image clarity or other improvements.
Stereoscopic imaging devices may include stereoscopic imagers, stereoscopic displays, and processing circuitry. The processing circuitry may be used to collect auto white balance (AWB) statistics for each image captured by the stereoscopic imager. A stereoscopic imager may include two image modules that may be color calibrated relative to each other or relative to a standard calibrator. AWB statistics may be used by the processing circuitry to determine global, local and spatial offset gain adjustments to provide intensity matched stereoscopic images for display. AWB statistics may be combined by the processing circuitry with color correction offsets determined during color calibration to determine color-transformation matrices for displaying color matched stereoscopic images using the stereoscopic display. Gain and color-transformation corrections may be continuously applied during operation of a stereoscopic imaging device to provide intensity-matched, color-matched stereoscopic images in any lighting condition.
Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.
An image sensor may include an image pixel array. The image sensor may be provided with automatic conversion gain selection on a pixel-by-pixel basis to produce a high-dynamic-range image. Each image pixel may include a capacitor and a conversion gain transistor coupled in series between a power supply line and a floating diffusion node. The conversion gain transistor may be coupled to a control line through a gating transistor. The gating transistor may have a gate connected to a row select line. The image pixel may have an output line that is coupled to a column amplifier and a comparator. The column amplifier may generate a difference voltage based on reset and image signals. The comparator may compare the difference voltage with a predetermined threshold to determine whether to place the selected pixel in a high or low conversion gain mode.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 9/64 - Circuits for processing colour signals
An imaging system may include an array of lenses, each of which is aligned over a respective one of a plurality of imaging pixels. The array of lenses may be formed in two layers. The first layer may include a first set of non-adjacent lenses and centering structures between the first lenses. The centering structures may be aligned with the first set of lenses as part of a mask design with a high level of accuracy. The second layer may include a second set of lenses, each of which is formed on a respective one of the centering structures. Forming the second set of lenses may include a reflow process in which surface tension forces center the second set of lenses on their respective centering structures, thereby aligning the second set of lenses with the first set of lenses with a high level of accuracy.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H01L 31/0232 - Optical elements or arrangements associated with the device
93.
Imager pixel architecture with enhanced column discharge and method of operation
A pixel circuit includes a photosensor and a floating diffusion node. A circuit is coupled to the floating diffusion node, for selectively providing a pixel output signal to a column line. A reset circuit, which resets the floating diffusion node, is configured to be activated by the column line. A pullup circuit is included for controlling the reset circuit through a signal on the column line. A discharge circuit, which is separate from the reset circuit, is used for discharging the pixel output signal on the column line. The discharge circuit includes a transistor having a first source/drain terminal coupled to the column line and a second source/drain terminal coupled to a fixed voltage level. The gate of the transistor activates the discharging of the column line.
The present invention relates to a backside illuminated (BSI) imager having a plurality of layers. A plurality of pixel sensors are positioned on a first layer of a substrate. Pixel select conductors are positioned on the substrate in front of the first layer. Pixel readout conductors including a plurality of output lines, pixel power conductors, and a ground conductor are positioned on the substrate in front of the pixel select conductors. A plurality of sample and hold capacitors coupled to the pixel output lines are positioned vertically and/or horizontally on the substrate in front of the ground conductor.
Interest points are markers anchored to a specific position in a digital image of an object. They are mathematically extracted in such a way that, in another image of the object, they will appear in the same position on the object, even though the object may be presented at a different position in the image, a different orientation, a different distance or under different lighting conditions. The goal is to match interest points in one image with corresponding interest points in another image. Typically, this involves the construction of a descriptor, which is both computationally expensive and resource-intensive. Methods and devices are described that match interest points without the construction of conventional descriptors and that permit the use of spatial coherency information to increase the accuracy of the match.
Image sensor arrays may include bulk-charge-modulated-device (BCMD) sensor pixels. The BCMD sensor pixels may be used in back-side-illuminated (BSI) image sensors. A BCMD sensor pixel need not include a dedicated addressing transistor. The BCMD sensor pixel may include a gated drain reset (GDR) structure that is used to perform reset operations. The GDR structure may be shared among multiple pixels, which provides increased charge storage capacity for high resolution image sensors. A negative back body bias may be applied to the BCMD pixel array, allowing the depletion region under each BCMD pixel to extend all the way to the back silicon surface. Extending the depletion region by negatively biasing the back silicon surface may serve to minimize pixel crosstalk.
Interest points are markers anchored to a specific position in a digital image of an object. They are mathematically extracted in such a way that, in another image of the object, they will appear in the same position on the object, even though the object may be presented at a different position in the image, a different orientation, a different distance or under different lighting conditions. Methods are disclosed that are susceptible to implementation in hardware and corresponding hardware circuits are described.
G06K 9/46 - Extraction of features or characteristics of the image
G06K 9/66 - Methods or arrangements for recognition using electronic means using simultaneous comparisons or correlations of the image signals with a plurality of references, e.g. resistor matrix references adjustable by an adaptive method, e.g. learning
98.
Image sensor pixels with back-gate-modulated vertical transistor
Image sensor arrays may include image sensor pixels each having at least one back-gate-modulated vertical transistor. The back-gate-modulated vertical transistor may be used as a source follower amplifier. An image sensor pixel need not include an address transistor. The image sensor pixel with the back-gate-modulated vertical source follower transistor may exhibit high fill factor, large charge storage capacity, and has as few as two row control lines and two column control lines per pixel. This can be accomplished without pixel circuit sharing. The pixel may also provide direct photo-current sensing capabilities. The ability to directly sense photo-current may facilitate fast adjustment of sensor integration time. Fast adjustment of sensor integration time may be advantageous in automotive and endoscopic applications in which the time available for the correction of integration time is limited.
Adaptive local tone mapping may be used to convert a high dynamic range image to a low dynamic range image. Tone mapping may be performed on an on a Bayer domain image. A high dynamic range image may be filtered to produce a luminance signal. An illumination component of the luminance signal may be compressed. A reflectance component of the luminance signal may be sharpened. After the luminance signal has been processed, it may be used in producing an output image in the Bayer domain that has a lower dynamic range than the input image. The output Bayer domain image may be demosaiced to produce an RGB image. Tone-mapping may be performed with a tone-mapping processor.
An imaging system may include an image sensor array formed from imaging pixels with feedback loops. Each imaging pixel may include an amplifier transistor that is controlled by a voltage on a floating diffusion node and may include a feedback transistor connected between the floating diffusion node and column readout circuitry. The amplifier transistor, together with a current source in the image sensor array, may form a common-source amplifier that inversely amplifies the voltage on the floating diffusion node and provides control signals to the feedback transistor. The common-source amplifier and the feedback transistor may create a feedback loop during image readout operations and during image reset operations that clamps the voltage on the floating diffusion node.
H04N 3/14 - Scanning details of television systemsCombination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
