A surface finish structure of a multi-layer substrate includes: a dielectric layer; at least one pad layer formed on the dielectric layer or embedded in the dielectric layer; at least one protective metal layer formed on the at least one pad layer and contacting the pad layer, wherein the at least one protective metal layer only covers a top surface of the at least one pad layer, and the at least one protective metal layer is configured to be soldered to or contact an external element; and a solder mask layer formed on the dielectric layer and including at least one opening to expose the at least one protective metal layer. A method for manufacturing a surface finish structure of a multi-layer substrate is also provided.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A structure of a package substrate includes: a first multi-layer substrate including a plurality of dielectric layers and a plurality of metal wiring layers and having a first surface and a second surface which are opposite to each other; and a supporting substrate having a first surface and a second surface which are opposite to each other, wherein the first surface of the supporting substrate is disposed on the second surface of the first multi-layer substrate and electrically connected to the first multi-layer substrate, there is no gap between the first surface of the supporting substrate and the second surface of the first multi-layer substrate, the supporting substrate includes a plurality of vertical vias, and the vertical vias are used for electrically connecting the first surface of the supporting substrate to the second surface of the supporting substrate.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
A composite structure of a ceramic substrate, including a first ceramic substrate formed by crystal growth, which has a first surface and a second surface opposite to each other, and has only vertical via holes filled with conductive material, so that the first surface and the second surface of the first ceramic substrate are electrically connected; and a thin film substrate disposed on the second surface of the first ceramic substrate, and one of the surfaces is electrically connected to the second surface of the first ceramic substrate, and an electrical connection point is provided on the other surface of the thin film substrate to electrically connect an external element or another circuit board.
H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
A probe device is provided, including a thin film substrate having opposite first and second surfaces; a plurality of probes disposed over the first substrate of the thin film substrate, wherein the probes are not deformable, and the probes and the thin film substrate are integrally formed; a ceramic substrate or glass substrate formed by a crystal growth method, having a first surface and a second surface opposite to each other which are electrically connected, the first surface of the ceramic substrate or the glass substrate is disposed on the second surface of the thin film substrate, and is electrically connected to the thin film substrate; and the second surface of the ceramic substrate or the glass substrate are electrically connected to the second surface for electrical connection to another circuit board.
A surface finish structure of a multi-layer substrate includes: a dielectric layer; at least one pad layer formed in the dielectric layer; and at least one protective metal layer formed on the at least one pad layer and bonded to the at least one pad layer, wherein the at least one protective metal layer only covers an upper surface of the at least one pad layer, the at least one protective metal layer is configured to be soldered to or contact an external element, and there is no height difference between an upper surface of the at least one protective metal layer and an upper surface of the dielectric layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A probe card device is provided, including a thin film substrate, a first circuit board, and a plurality of probes. The thin film substrate has opposite first and second surface. The first circuit board is disposed over the second surface of the thin film substrate to electrically connect the thin film substrate. The probes are disposed over the first surface of the thin film substrate and are not deformable.
A metal probe structure and a method for fabricating the same are provided. The metal probe structure includes a multi-layer substrate, a first flexible dielectric layer, a second flexible dielectric layer, and a plurality of first metal components. The first flexible dielectric layer is disposed over the multi-layer substrate and has a conductive layer formed thereover. The second flexible dielectric layer is disposed over the first flexible dielectric layer to cover the conductive layer. The plurality of first metal components is disposed over the conductive layer and partially in the second flexible dielectric layer to serve as a metal probe.
A wristwatch and a method for improving security in electronic payment for a wristwatch are provided. The wristwatch includes a short distance communication module having a security element. The security element provides security information required in implementing the electronic payment. The wristwatch further includes a controller coupled to the short distance communication module for enabling or disabling the electronic payment executed by the short distance communication module, based on a user operation. In the wristwatch, the electronic payment function can be manually launched or terminated by a user, thereby reducing a risk of being stolen for security data.
A wristwatch and a power saving method thereof are provided herein. The wristwatch comprises: a time indicating device, configured to provide time information; a housing, defining a receiving room; a short distance communication module disposed in the receiving room, configured to implement short distance wireless communication with an external device, the communication module comprising: a security element, configured to process user security data; and a first coil, coupled to the security element and configured to transmit electromagnetic signals to communicate with the external device; the wristwatch further comprising: a second coil, coupled to the communication module, configured to sense an external magnetic field to generate a sensing signal, the sensing signal provided for controlling the communication module to be turned on or off to enable or disable transmission of the electromagnetic signals of the first coil. The wristwatch can reduce power consumption.
G04G 19/00 - Electric power supply circuits specially adapted for use in electronic time-pieces
G04G 21/08 - Touch switches specially adapted for time-pieces
G06F 1/16 - Constructional details or arrangements
G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
A probe card device includes a probe head including a plurality of pins, wherein each of the pins includes a body, a first metal layer formed on the body, and a second metal layer covering the first metal layer; a multi-layered flexible board electrically connected to the pins; a support plate, the multi-layered flexible board disposed on a first surface of the support plate; and a circuit board electrically connected to the multi-layered flexible board.
A substrate separation system configured to remove a substrate from a carrier is provided. The substrate separation system includes a stage, an upper fixing portion, a suction portion, a cutting portion and a blowing portion. The stage is configured to carry the carrier. The upper fixing portion is disposed above the stage so as to be movable up and down. The suction portion is disposed above the stage so as to be movable up and down, and has a hollow portion to accommodate the upper fixing portion. The cutting portion is disposed on one side of the stage. The blowing portion is disposed on another side of the stage, and is configured to provide a blowing force to a position between the substrate and the carrier.
B32B 43/00 - Operations specially adapted for layered products and not otherwise provided for, e.g. repairingApparatus therefor
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
12.
Wristwatch and method applicable to wristwatch for controlling magnitude of short distance communication signals
A wristwatch and a method applicable to a wristwatch for controlling the magnitude of short distance communication signals are provided. A short distance communication module is disposed inside the wristwatch, and therefore short distance communication is carried out in the wristwatch. Also, an amplifier is deployed in the wristwatch, thereby carrying out enhancing the magnitude of the short distance communication signals. The magnitude of the short distance communication signals can also increase or decrease through user operations. In another aspect, a magnetic field isolating layer is disposed inside a housing of the wristwatch. The magnetic field isolating layer can reduce interference caused by the housing or other components of the wristwatch, and thus can enhance the magnitude of the short distance communication signals and extend the sensing distance.
G04R 60/12 - Antennas attached to or integrated in clock or watch bodies inside cases inside metal cases
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A communication device and a manufacturing method thereof are disclosed. The communication device includes a top cover, a housing, a bottom cover, a first magnetic isolation layer, and a short distance communication module. The housing is made of a metal material or an electrically conductive material. The top cover, the housing, and the bottom cover are assembled to construct an accommodating space from top to bottom. The first magnetic isolation layer is formed on a surface of the housing facing the accommodating space. The short distance communication module is disposed in the accommodating space. The communication device can prevent electromagnetic waves from being affected by the housing.
G04R 60/06 - Antennas attached to or integrated in clock or watch bodies
G04R 20/26 - Setting the time according to the time information carried or implied by the radio signal the radio signal being a near-field communication signal
H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04M 1/02 - Constructional features of telephone sets
14.
Wristwatch, mobile terminal, and communication reminding system and method
A contact person selecting interface is provided on a mobile terminal for a user. Using such an interface, the user can select one or more contact persons that are desired to transmit reminders. When receiving an incoming call or a new message, the mobile terminal determines whether a person sending the incoming call or the new message is selected by the user. If yes, the mobile terminal makes a wearable device give out a prompt message for remaindering the user. In such a way, it is convenient for the user to trace important calls or messages.
H04M 1/2745 - Devices whereby a plurality of signals may be stored simultaneously with provision for storing more than one subscriber number at a time using static electronic memories, e.g. chips
H04M 3/42 - Systems providing special services or facilities to subscribers
H04W 4/16 - Communication-related supplementary services, e.g. call-transfer or call-hold
H04M 19/04 - Current supply arrangements for telephone systems providing ringing current or supervisory tones, e.g. dialling tone or busy tone the ringing-current being generated at the substations
TEK CROWN TECHNOLOGY CO., LTD. (Taiwan, Province of China)
Inventor
Yang, Chih-Kuang
Guu, Yeong-Yan
Lee, Mou-I
Abstract
A probe card device includes a plurality of pins; a thin film substrate including a plurality of first thin film connecting points and a plurality of second thin film connecting points, wherein at least one of the first thin film connecting points is electrically connected to at least one the second thin film connecting points, and a pitch of any two adjacent ones of the first film connecting points is less than a pitch of any two adjacent ones of the second film connecting points; and a circuit board including a plurality of first circuit board connecting points, wherein at least one of the second thin film connecting points is electrically connected to at least one of the first circuit board connecting points. The probe card device can enhance a layout function and a support function at the same time.
A smart wristwatch structure includes a glass, a dial, a watch case, a bottom case, a movement, an antenna, a functional module, and a dedicated battery. The dial, the watch case, and the bottom case construct an accommodating space from top to bottom. The antenna is adhered to a lower surface of the glass. The functional module is disposed in the accommodating space for wirelessly communicating with a mobile terminal. The dedicated battery provides power for the functional module or the movement. In the smart wristwatch structure, signals are not shielded, and the thickness of the watch case is not increased significantly.
Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G01R 31/26 - Testing of individual semiconductor devices
Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
A metal structure manufacture method for a multi-layer substrate comprises coating a photoresist layer on a first dielectric layer; proceeding a photolithography process to the photoresist layer to define a specific position for a first metal layer; removing the photoresist layer at the specific position; and forming the first metal layer at the specific position, wherein a base area of the first metal layer is larger than a top area thereof, and wherein the embedded base and the main body are formed in a same process and are monolithic formed. Said manufacturing method can be employed to manufacture a pad or a metal line of the flexible multi-layer substrate, and the manufactured metal structure cannot easily be delaminated or separated from the contacted dielectric layer.
H01R 9/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, e.g. terminal strips or terminal blocksTerminals or binding posts mounted upon a base or in a caseBases therefor
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
22.
Manufacturing method of metal structure in multi-layer substrate
Disclosed is a manufacturing method of metal structure in multi-layer substrate. The manufacturing method includes following steps: coating at least one photoresist layer on a surface of a dielectric layer; exposing the photoresist dielectric layer to define a predetermined position of the metal structure; removing the photoresist layer at the predetermined position to undercut an edge of the photoresist layer adjacent to the predetermined position by a horizontal distance of at least 0.1 μm between a top and a bottom of the edge; forming the metal structure at the predetermined position; and forming at least one top-cover metal layer to cover a top surface and two side surfaces of the metal structure. The present invention can form a cover metal layer covering the top surface and the two side surfaces by one single photomask.
B05D 5/12 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain a coating with specific electrical properties
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall.
Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process. Significantly, the multi-layer substrate having thin dielectric layers according to the present invention can satisfy the concern of impedance matching therefore, and can reduce crosstalk influence to keep good signal integrity therein.
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.
A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.
Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the embedded base. The base area of the embedded base is larger than the base area of the main body. After the dielectric layer covers the main body and the embedded base, the dielectric layer is opened at the specific position of the first metal layer for connecting the first metal layer with a second metal layer above the dielectric layer. When the metal structure is employed as a pad or a metal line of the flexible multi-layer substrate according to the present invention, the metal structure cannot easily be delaminated or separated from the contacted dielectric layer. Therefore, a higher reliability for the flexible multi-layer substrate can be achieved.
Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.
H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
29.
Manufacturing method of metal structure in multi-layer substrate and structure thereof
Disclosed is a manufacturing method of metal structure in multi-layer substrate and structure thereof. The manufacturing method of the present invention comprises following steps: coating at least one photoresist layer on a surface of a dielectric layer, and then exposing the photoresist dielectric layer to define a predetermined position of the metal structure; therefore, removing the photoresist layer at the predetermined position and forming the metal structure at the predetermined position before forming at least one top-cover metal layer on a surface of the metal structure. The present invention can form a cover metal layer covering over the top surface and the two side surfaces, even the under surface of the metal structure, by one single photomask. Moreover, a finer metal structure with higher reliability can be manufactured. Furthermore, a metal structure can be used as a coaxial structure is also realized.
B32B 15/08 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance of synthetic resin
H01B 5/14 - Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
30.
Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof
Disclosed is a method of manufacturing a hybrid structure of multi-layer substrates. The method comprises steps of: separating a border district of at least one metal layer connecting with a border district of the corresponding dielectric layer from adjacent metal layers and adjacent dielectric layers for each multi-layer substrate and connecting a separated border of a metal layer of one multi-layer substrate with a separated border district of a metal layer of another multi-layer substrate to form a connection section. The hybrid structure comprises at least a first multi-layer substrate and a second multi-layer substrate. At least one first metal layer is connected with at least one second metal layer to form a connection section.
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.
Disclosed are a multi-layer substrate and a manufacture method thereof. The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer. The surface dielectric layer is located at a surface of the multi-layer substrate. The bond pad layer is embedded in the surface dielectric layer to construct the multi-layer substrate with the surface dielectric layer of the present invention. The manufacture method of the present invention forms at least one bond pad layer on a flat surface of a carrier and then forms the surface dielectric layer to cover the bond pad layer where the bond pad layer is embedded therein. After the multi-layer substrate is separated from the carrier, the bond pad layer and the surface dielectric layer construct a flat surface of the multi-layer substrate.
Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process. Significantly, the multi-layer substrate having thin dielectric layers according to the present invention can satisfy the concern of impedance matching therefore, and can reduce crosstalk influence to keep good signal integrity therein.
A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.
The invention provides a substrate with multi-layer interconnection structure, which includes a substrate and a multi-layer interconnection structure formed on the substrate. The multi-layer interconnection structure is adhered to the substrate in partial areas. The invention also provides a method of manufacturing and recycling such substrate and a method of packaging electronic devices by using such substrate. The invention also provides a method of manufacturing multi-layer interconnection devices.
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.
A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.
Disclosed is a method of manufacturing a hybrid structure of multi-layer substrates. The method comprises steps of: separating a border district of at least one metal layer connecting with a border district of the corresponding dielectric layer from adjacent metal layers and adjacent dielectric layers for each multi-layer substrate and connecting a separated border of a metal layer of one multi-layer substrate with a separated border district of a metal layer of another multi-layer substrate to form a connection section. The hybrid structure comprises at least a first multi-layer substrate and a second multi-layer substrate. At least one first metal layer is connected with at least one second metal layer to form a connection section.
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.
09 - Scientific and electric apparatus and instruments
Goods & Services
Blank optical storage media, namely magnetic optical discs, recordable mini disks, recordable and rewritable compact discs, and recordable and rewritable digital versatile discs, floppy disks, CD-ROMs, blank disks for storage of computer data, disk drives, electronic data storage devices and data reading devices, namely, CD duplicators, DVD duplicators, CD-R recorders, CD-RW recorders, DVD-R recorders, DVD-RW recorders, video disks, sound recording disks, video compact disks
