Abstract

The integrated circuit structure includes a substrate and a first resistive memory string over the substrate. The first resistive memory string includes memory cells, and each of the memory cells includes a word line transistor and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region. The resistor is over the word line transistor and is connected with the word line transistor in parallel. The word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

Systems, devices, methods, and circuits for managing data security in storage devices. In one aspect, a storage device includes at least one memory device and a controller coupled to the at least one memory device. The controller is configured to: encrypt first data with a first type of cryptographic algorithm and encrypt second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level that is higher than the first security level. The second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory
• H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
• H04L 9/08 - Key distribution

Abstract

A semiconductor structure includes a gate, a channel structure, a gate insulating layer, a source, and a drain. The channel structure includes a threshold switching material, in which the channel structure includes a layered channel, a columnar channel, or a plurality of nanosheet channels. The gate insulating layer is disposed between the gate and the channel structure. The source is in direct contact with the channel structure. The drain is in direct contact with the channel structure.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval

Abstract

A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.

IPC Classes  ?

• G06F 16/00 - Information retrievalDatabase structures thereforFile system structures therefor
• G06F 16/2455 - Query execution
• G06F 16/28 - Databases characterised by their database models, e.g. relational or object models

Abstract

Methods, devices, apparatus, and systems for managing phase change materials for memory devices are provided. In one aspect, an integrated circuit (e.g., a memory element) includes: a first electrode, a second electrode, and a body of a phase change material coupled between the first electrode and the second electrode. The phase change material includes SixSbyTez, where x, y, z represent respective atomic ratios for compositions Si, Sb, Te. A bulk stoichiometry of the body of the phase change material includes a Si atomic concentration within a range from about 7% to about 12%.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• C22C 30/00 - Alloys containing less than 50% by weight of each constituent
• H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group and a second group of local bit lines separated from each other, wherein two adjacent local bit lines are disposed between adjacent two local source lines. The second upper conductive layer includes a global bit line. The global bit line is electrically connected to the local bit lines through the conductive pattern. The 3D memory could be a 3D AND flash memory with high capacity and high performance.

IPC Classes  ?

• G11C 16/24 - Bit-line control circuits
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• G11C 11/4076 - Timing circuits

Abstract

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A non-volatile memory cell includes a capacitor which includes a top electrode, a bottom electrode, a ferroelectric layer disposed between the top electrode and the bottom electrode, and an amorphous layer disposed between the top electrode and the bottom electrode, wherein an atomic arrangement of the amorphous layer is different from an atomic arrangement of the top electrode and the bottom electrode. A method of fabricating a non-volatile memory cell and a memory cell array thereof are also disclosed.

IPC Classes  ?

• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Abstract

A TCAM comprises multiple first search lines, multiple second search lines, multiple memory cell strings, and one or more current sensing units coupled to the plurality of memory cell strings. Each memory cell string comprises multiple memory cells. Each memory cell string comprises at least four transistors serially connected as a NAND memory string, and two transistors of the at least four transistors form each memory cell. One, of the two transistors in each memory cell, coupled to one of the first search lines is a first transistor, and the other one, of the two transistors in each memory cell, coupled to one of the second search lines is a second transistor. The multiple first search lines are arranged consecutively, and the multiple second search lines are arranged consecutively.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
• G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A circuit is provided. The circuit includes an array of memory cells including a plurality of bit lines and a plurality of word lines, sensing circuits configured to sense a difference between first and second currents on respective bit lines in selected bit lines and to produce outputs for the selected bit lines as a function of the difference, and a global counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal. Each sensing circuit, of the sensing circuits, can produce an output in dependence on (i) the difference between the first and second currents and (ii) a stored count value received from the global counter, the count value being stored in dependence on a value of the difference between the first and second currents.

IPC Classes  ?

• G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

A control device, for controlling an operation of a memory device, wherein the memory device includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory cells, and each of the memory cells stores a bit-data. The control device comprises the following elements. A processor, for classifying the memory cells into a plurality of groups according to an erase count of each of the memory cells, the groups respectively correspond to a plurality of recovery times. A memory interface control circuit, coupled to the processor and the memory device, and the processor controls the memory device to perform a bit recovery operation through the memory interface control circuit. The processor selects one of the groups according to the recovery times, and performs the bit recovery operation on the bit-data of each of the memory cells in the selected group.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device and a programming method thereof are provided. The memory device has multiple word lines and a dummy word line set. A word line is selected from the word lines and is applied with a program voltage, and unselected word lines and the dummy word line set are applied with a pass voltage. After programming the selected word line, a program verification is performed on the selected word line. When the selected word line passes the program verification, a high bound and/or low bound check for the threshold voltage distribution of at least one of the dummy word lines is performed. When at least one of the dummy word lines fails in the high bound and/or low bound check, the status of the selected word line is shown as fail or a flag is set thereto.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/10 - Programming or data input circuits

Abstract

An operating method of a memory system is disclosed herein. The operating method includes: inputting tracking data to a tracking array; generating tracking logic values by tracking cell columns of the tracking array according to the tracking data; counting the tracking logic values to generate a summation value; adjusting a sensing time of a sensing device according to the summation value; performing a computing operation by a computing array to generate computing signals; and sensing the computing signals by the sensing device according to the adjusted sensing time.

IPC Classes  ?

• G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• G06F 3/06 - Digital input from, or digital output to, record carriers
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• H03K 3/037 - Bistable circuits
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

Abstract

A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

IPC Classes  ?

• H10B 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.

IPC Classes  ?

• H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management

Abstract

A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device is a 3D NAND flash with high capacity and high performance. The calibration apparatus includes an impedance, a strong-arm comparator, a logic circuit, and a calibration controller. The impedance is configured to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares a reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. The calibration controller implements an impedance calibration in the memory device according to the comparison result signal.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A differential amplifier includes an input pair of transistors with a source-side resistor circuit, having a transistor biased in a triode region, and a current source. The resistor circuit in combination with a capacitance, causes source degeneration in the amplifier. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit biases the first MOS transistor and the second MOS transistor in a triode region. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers

Abstract

A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A memory device includes a substrate, a bonding structure and bit lines. The substrate includes adjacent first and second regions. The bonding structure is over the substrate and includes a bonding dielectric layer and first and second bonding pads. The bonding dielectric layer is over the substrate in the first and the second regions. The first and second bonding pads are respectively embedded in the bonding dielectric layer over the substrate in the first and second regions. The bit lines are over the bonding structure and extend from the first region to the second region. A density of the first bonding pads in the first region is greater than a density of the second bonding pads in the second region. The memory device may be 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A method of fabricating a memory device at least includes the following steps. A first stack structure is formed above a substrate. The first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers alternately stacked. A top layer of the first stack structure includes a plurality of anti-oxidation atoms therein. A second stack structure is formed on the first stack structure. The second stack structure includes a plurality of second insulating layers and a plurality of middle layers alternately stacked. A slit trench is formed to extend from the second stack structure to a top first conductor layer of the plurality of first conductor layers. A protective layer is formed on a sidewall of the top first conductive layer exposed by the slit trench. The memory device may be a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device and an operating method for the memory device are provided. The memory device includes a memory array and a control circuit. The memory array includes memory blocks. Each of the memory blocks is, for example a three-dimensional NAND flash memory block. The memory device provides a storage media with high-performance and high-capacity. The control circuit provides a first erasing voltage to perform a first erasing operation on target memory cell strings of a selected memory block in the memory blocks, performs a programming operation on the target memory cell strings after the first erasing operation, and provides a second erasing voltage to perform a second erasing operation on at least one part of memory cells of each of the target memory cell strings after the programming operation. The second erasing voltage is lower than the first erasing voltage.

IPC Classes  ?

• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits

Abstract

A duty cycle correction method and a duty cycle correction apparatus, adapted for correcting a duty cycle of a clock signal by using a duty cycle adjuster in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, the duty cycle is adjusted and input to data pads to generate data signals, wherein the data pads are divided into at least two groups and defined by data patterns that are inverse to each other; DC voltages of the data signals of a first group of data pads are detected to generate a first average DC voltage, and DC voltages of the data signals of a second group of data pads are detected to generate a second average DC voltage, the aforementioned average DC voltages are compared, and the duty cycle adjuster is controlled to adjust the duty cycle of the clock signal.

IPC Classes  ?

• H03K 7/08 - Duration or width modulation
• H03K 5/02 - Shaping pulses by amplifying
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

A memory structure including a memory array is provided. The memory array is a block including six sub-blocks. The memory array includes string select line portions and ground select line portions. The string select line portions are arranged along a first direction. Each of the string select line portions is located in the corresponding sub-block. The ground select line portions are arranged along the first direction. Each of the ground select line portions is shared by only two corresponding sub-blocks. The memory structure may be a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor device includes a substrate, a plurality of memory arrays and a plurality of capacitors. The substrate includes a plurality of memory array regions. Each memory array region includes a plurality of memory blocks and a plurality of dummy blocks. The dummy blocks are located along a boundary of the memory blocks. The plurality of memory arrays are disposed in the plurality of memory blocks. The plurality of capacitors are disposed in the plurality of dummy blocks along the boundary of the plurality of memory blocks. The plurality of memory arrays may include 3D NAND flash memories with high capacity and high performance.

IPC Classes  ?

• H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Abstract

An operation method of a memory device including the following operations is provided. Applying a read voltage to a selected page of a plurality of programmed memory pages. Applying a first pass voltage to unselected pages of the plurality of programmed memory pages. Applying a second pass voltage to at least one unprogrammed memory page, wherein the first pass voltage is larger than the second pass voltage. A memory system including a 3D NAND flash memory with high capacity and high performance is also provided.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/10 - Programming or data input circuits

Abstract

A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

IPC Classes  ?

• H01L 27/115 - Electrically programmable read-only memories; Multistep manufacturing processes therefor
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Systems, devices, methods, and circuits for managing power supply in semiconductor devices are provided. The semiconductor devices can include 3D NAND flash memory devices with high capacity and/or high performance. In one aspect, a semiconductor device includes: a voltage pump, a pump switch circuit configured to be coupled to the voltage pump, and an interface including a voltage pin coupled to the pump switch circuit. The voltage pump has an input, an output, and a series of pump stages coupled between the input and the output. The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at the output of the voltage pump.

IPC Classes  ?

• G11C 16/30 - Power supply circuits

Abstract

The invention provides a storage system and an operation method thereof. The operating method includes: when a first data is written into the storage system, the memory control circuit dividing the first data into a first part and a second part; the memory control circuit writing the first part of the first data to the first type memory; and the memory control circuit writing the second part of the first data to the second type memory. A data amount of the first part of the first data is related to a read latency difference and a data transfer rate of the second type memory. The read latency difference is related to the first read latency of the first type memory and the second read latency of the second type memory.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An overlay mark includes a previous layer mark and a current layer mark. The previous layer mark includes a plurality of first work zones. Each first working zone includes a first sub-region and a second sub-region, wherein the first sub-region is closer to a center point of the previous layer mark than the second sub-region. The previous layer mark includes a first mark and an auxiliary mark respectively in the first sub-region and the second sub-region of each first working zone. The current layer mark includes a plurality of second working zones. Each second working zone includes a first sub-region and a second sub-region. The current layer mark includes a second mark disposed in the second sub-region of each second working zone. The overlay mark may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

A memory system that is based on 3D NAND flash memory of a high capacity and/or capable of high performance is provided, which includes memory planes, each including a plane core and a specific set of resources. For each memory plane of the plurality of memory planes, the technology provides (i) a corresponding plane busy (PRDY) signal indicating a busy or a ready state of the specific set of recourses of the corresponding memory plane, and (ii) a corresponding plane in operation (PIO #) signal indicating an in operation or idle state of resources used by the plane core of the corresponding memory plane. Issuance of memory commands by a controller and execution of memory commands for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PIO # signals.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory device includes, from bottom to top, a substrate, a laminated layer and a stacked structure. Vertical channel pillars penetrate through the stacked structure and the laminated layer. First isolation structures are disposed aside the vertical channel pillars and penetrate through a lower part of the stacked structure. Second isolation structures are disposed over the first isolation structures and penetrate through an upper part of the stacked structure. Common source lines are disposed aside the vertical channel pillars and penetrate through the stacked structure and part of the laminated layer. From a top view, the common source lines extend in a first direction. Each of the first and second isolation structures has, in the first direction, two wide end portions respectively adjacent to two common source lines. The memory device may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Abstract

A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4094 - Bit-line management or control circuits

Abstract

The present disclosure relates to a method for manufacturing a 3D memory device, and particularly, to a method for manufacturing high capacity and high performance 3D NAND flash memory device. The method includes: alternately stacking sacrificial layers and insulating layers; forming a channel through hole through the sacrificial layers and the insulating layers; lining the channel through hole with an initial blocking layer; and performing an oxidation treatment, for turning the initial blocking layer to a blocking oxide layer. A gas source for the oxidation treatment includes a reaction gas having hydrogen and oxygen, and includes an ionization enhancement gas formed by a first type ionization enhancement gas, a second type ionization enhancement gas or a combination thereof. The first type ionization enhancement gas includes at least one in a group consist of tritium, ozone and H2O. The second type ionization enhancement gas includes at least one inert gas.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Disclosed are a multi-circuit control system and a reading method for status information thereof. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example a three dimensional NAND flash memory circuit, and the multi-circuit control system provides a storage media with high-performance and high-capacity. The first circuit provides a read clock signal. The second circuits are coupled in series, and coupled to the first circuit. Each of the second circuits has at least one first data shifter. The at least one data shifter is used to load status information of each of the second circuits, and shift out each of the status information to a second circuit of a previous stage or the first circuit or the first chip obtains the status information of each of the second circuits through a parallel transmission scheme.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A semiconductor device includes a stack including a plurality of insulating layers and a plurality of word plane conductors alternately arranged, a vertical pillar structure disposed in the stack, and a plurality of outer electrodes. The vertical pillar structure includes a conductive core, an inner electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the inner electrode, in which the inner electrode is disposed between the conductive core and the OTS layer. The outer electrodes are disposed between the OTS layer and the word plane conductors, wherein a resistance of a material of the word plane conductors is less than a resistance of a material of the outer electrodes. A method of forming the semiconductor device is also disclosed.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A manufacturing method of a memory device may be applied to a three-dimensional NAND memory device with high capacity and high performance. In a manufacturing process of the three-dimensional NAND memory device, a material of a control gate (word line) is tungsten. The forming method of a tungsten layer includes nucleation and bulk formation performed. In at least one of the nucleation and the bulk formation, hydrogen flow is between 1000 and 20000 sccm. At least one time of soak with nitrogen may also be performed after the nucleation. A tungsten grain size in the tungsten layer is 70 nm or more.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor bonded structure including a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure, and a circuit layer is provided. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The circuit layer is disposed on the at least one second semiconductor chip and the circuit layer is electrically connected to the at least one second semiconductor chip. A fabricating method of the semiconductor bonded structure is also provided. The semiconductor bonded structure may be applied to the fabrication of 3D NAND flash memory with high performance and high capacity.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 16/10 - Programming or data input circuits

Abstract

A semiconductor device includes a stack and a plurality of vertical pillar structures disposed in the stack. The stack includes a plurality of insulating layers and a plurality of conductive layers alternately arranged, each of the conductive layers includes a center portion and a plurality of edge portions at edges of the center portion, wherein a resistance of a material of the edge portions is less than a resistance of a material of the center portion. Each of the vertical pillar structures includes a conductive core, a shell electrode on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer on a sidewall of the shell electrode. A method of forming the semiconductor device is also disclosed.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron

Abstract

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• H03K 21/08 - Output circuits

Abstract

A circuit comprises a plurality of bit lines, a global counter configured to provide a count value, a global reference source, a plurality of capacitors, a comparator, a storage element, and capacitor selector circuitry. The capacitor selector circuitry is configured to select, in dependence on the count value, one or more capacitors from the plurality of capacitors, and wherein the selection of the one or more capacitors is further in dependence on pre-coded codes receivable from an agent separate from the circuit, the pre-coded codes enabling specifying respective first and second sets of the plurality of capacitors as respective one or more capacitors having respective first and second capacitance values, the pre-coded codes further enabling specifying selection of the first set to be performed at an earlier time than selection of the second set, and the second capacitance value is more than the first capacitance value

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/12 - Analogue/digital converters
• H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type

Abstract

The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

IPC Classes  ?

• G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10D 30/01 - Manufacture or treatment
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Abstract

A method of programming a memory includes performing a plurality of programming shots is provided. Each programming shot includes a pre-charge stage and a programming stage and includes the following steps. Applying a common source line voltage to a common source line or applying a bit line voltage to a bit line in the pre-charge stage, wherein the common source line voltage or the bit line voltage is applied by using incremental-step-pulse programming (ISSP) in the plurality of pre-charge stages. Applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using ISSP in the plurality of programming stages.

IPC Classes  ?

• G11C 16/10 - Programming or data input circuits
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/24 - Bit-line control circuits
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A memory device includes a substrate, a bottom source structure, gate layers, dielectric layers, a contact structure and a plurality of support pillar structures. The bottom source structure is located over the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure and a blocking structure. The gate layers and the dielectric layers are alternately stacked over the bottom source structure. The contact structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The support pillar structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. A memory device includes a substrate, a bottom source structure, gate layers, dielectric layers, a contact structure and a plurality of support pillar structures. The bottom source structure is located over the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure and a blocking structure. The gate layers and the dielectric layers are alternately stacked over the bottom source structure. The contact structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The support pillar structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the support pillar structures. The blocking structure of the bottom source structure is located between one of the support pillar structures and the contact structure.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuits and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a circuit distribution area of the high voltage processing circuit accounts for less than 10% of the peripheral substrate area.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The application provides a method and a memory device for performing wear leveling in a memory device. The method includes: receiving data to be written transmitted by a host in the memory device; predicting the data to be written as a first type of data or a second type of data; referencing an erase count table in an erase count table buffer of the memory device; and when the data to be written is predicted as the first type of data, writing the data to be written into the block with a highest erase count among these blocks, and when the data to be written is predicted as the second type of data, writing the data to be written into the block with a lowest erase count among these blocks.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A semiconductor device includes a first substrate, a first chip, a second chip, and a first substrate conductive pillar. The first chip is disposed on the first substrate and has a first lateral surface. The second chip is disposed on the first chip and includes a first protrusion protruding relative to the first lateral surface. The first substrate conductive pillar connects the first protrusion with the first substrate.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

An electrostatic discharge circuit includes a discharge switch, a first trigger circuit and a second trigger circuit. A first terminal of the discharge switch is coupled to a first power domain, and a second terminal of the discharge switch is coupled to a second power domain. The first trigger circuit is coupled between the first terminal and a control terminal of the discharge switch. The second trigger circuit is coupled between the second terminal and the control terminal. When an electrostatic discharge voltage occurs in the first power domain, the second trigger circuit is configured to form a conduction voltage between the second terminal and the control terminal to turn on the discharge switch. When the electrostatic discharge voltage occurs in the second power domain, the second trigger circuit is configured to short the second terminal and the control terminal to turn on the discharge switch.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

Provided are a memory device and a pre-charge method for a memory device. The pre-charge method includes: applying a plurality of independently-controlled pre-charge voltages to a plurality of turned-on word lines, wherein the plurality of pre-charge voltages are selected among a plurality of reference pre-charge voltages; and applying a plurality of turned-off voltages to a plurality of turned-off word lines. On a predetermined direction, a target turned-on word line among the plurality of turned-on word lines is adjacent to a next adjacent target turned-off word line among the plurality of turned-off word lines; and a voltage difference from the target turned-on word line toward the next adjacent target turned-off word line is smaller than a predetermined reference voltage difference.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

Abstract

A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/408 - Address circuits
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.

IPC Classes  ?

• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/10 - Programming or data input circuits
• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.

IPC Classes  ?

• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
• G11C 16/24 - Bit-line control circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

IPC Classes  ?

• G11C 7/24 - Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writingStatus cellsTest cells
• G06F 21/44 - Program or device authentication
• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.

IPC Classes  ?

• G11B 20/10 - Digital recording or reproducing
• G11B 20/14 - Digital recording or reproducing using self-clocking codes

Abstract

A 3D bit cost scalable memory device includes a stack of layers and a via electrode extending vertically through the stack of layers. The layers include a controllable conductivity layer and an electrode layer. The electrode layer has a conductor portion and a separator portion that separates the via electrode from the conductor portion of the electrode layer. At least a storage portion of the controllable conductivity layer is in electrical series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The conductor portion of the electrode layer comprises, for example, carbon (C).

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A system having a data bus, a source node device on the data bus and a group of bus node devices on the data bus. The source node device is configured to transmit a group read status command on the data bus. The bus node devices in the group are configured to respond to the group read status command in sequence, by transmitting status data on the data bus in respective, non-overlapping timing windows. The system can be a memory system.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A non-volatile memory and a programming method thereof are provided. The programming method includes: performing a reading operation on a plurality of first memory cells of an Nth word line, and determining whether an equivalent threshold voltage is greater than a preset threshold value to generate a determination result, where N is a positive integer greater than 0; and in response to performing a programming operation on a plurality of second memory cells of an N+1th word line, deciding whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value according to the determination result.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

IPC Classes  ?

• H10B 99/00 - Subject matter not provided for in other groups of this subclass
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/39 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using thyristors
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action

Abstract

The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.

IPC Classes  ?

• G01K 7/42 - Circuits effecting compensation of thermal inertiaCircuits for predicting the stationary value of a temperature
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region

Abstract

A memory device includes a substrate and first to fourth tiers. The first tier is located on the substrate and includes first transistors and second transistors. The first transistors includes multiple groups. The second tier includes a composite stack structure. The third tier includes local bit lines and local source lines. Each of the local bit lines is connected to a first terminal of one of the first transistors. Each of the local source lines is connected to a first terminal of one of the second transistors. The fourth tier includes multiple global bit lines and a common source line. Each of the global bit lines is connected to second terminals of the first transistors in one of the groups. The common source line is connected to a second terminal of each of the second transistors. Embodiments of the present disclosure may be applied to a 3D AND flash memory.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Abstract

The application discloses a semiconductor memory device and a data storage method. When determining that an input data conforms to a target format, an input data vector is generated based on the input data. When determining that the input data is similar to a stored data in a target block of the memory array, the input data is written to a blank target memory page of the target block of the memory array.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

The application provides a content addressable memory (CAM) device and a method for searching and comparing data thereof. The CAM device comprises: a plurality of memory strings; and a sensing amplifier circuit coupled to the memory strings; wherein in data searching, a search data is compared with a storage data stored in the memory strings, the memory strings generate a plurality of string currents, the sensing amplifier circuit senses the string currents to generate a plurality of sensing results; based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

IPC Classes  ?

• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 16/30 - Power supply circuits

Abstract

A 3D search engine receives searches for application to word lines of a nonvolatile memory array. The engine uses two word lines per bit of information of the searches and two memory devices per bit of stored feature to search against, optionally enabling don't care and/or wildcard encoding. The engine uses respective bit lines of the nonvolatile memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the nonvolatile memory array are usable to store respective data words, e.g., corresponding to features to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. Various encodings of features and searches enable exact, approximate, and range matching. The engine has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

IPC Classes  ?

• G06F 12/02 - Addressing or allocationRelocation

Abstract

A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 7/06 - Sense amplifiersAssociated circuits
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• G11C 16/10 - Programming or data input circuits
• G11C 16/30 - Power supply circuits

Abstract

A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a top isolating member and a common wall, wherein the unprocessed region extends along the first direction, the staircase region is adjacent to a first side of the unprocessed region, the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region. The top isolating member extends along the first direction to separate the conductive layers disposed in a top portion of the stacked structure.

IPC Classes  ?

• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Abstract

An AI inference platform comprises a logic die including an array of AI processing elements. Each AI processing element including an activation memory storing activation data for use in neural network computations. The platform includes a memory die that includes an array of 3D memory cells and a page buffer that facilitates storage and retrieval of neural network weights for use in neural network computations. A plurality of vertical connections can directly connect AI processing elements in the logic die and page buffers of corresponding ones of the memory cells in the memory die, enabling storage or retrieval of a neural network weight to and from a particular page buffer of a corresponding 3D memory cell for use in neural network computations conducted by a corresponding AI processing element in the logic die.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/048 - Activation functions

Abstract

A system based on computational memory and memory systems, such as embodied in computational solid state drive (SSD) technology, as described herein, reduces processor utilization and/or bus bandwidth utilization. The system is enabled to perform computational techniques (e.g., searching, computing, and/or accessing) using resources of the computational SSDs, rather than processor and/or bus resources, thus reducing or minimizing information movement between processing elements and storage devices. Computational SSD technology enables managing, organizing, selecting, and analyzing ever increasing data volume in real time. A computational SSD is enabled to store and to operate on data locally, e.g., using resources of the computational SSD. Thus, processing, storage, and bandwidth requirements of a system are reduced by using the computational SSD.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/24 - Bit-line control circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

An integrated circuit structure includes a substrate, a first memory string, a source line, and a second memory string. The first memory string is over the substrate and comprises first memory cells stacked in a vertical direction. The source line laterally extends over the first memory string. The second memory string is over the source line and comprises second memory cells stacked in the vertical direction.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.

IPC Classes  ?

• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Abstract

A memory device and a reading method thereof are provided. A second word line and a third word line are adjacent to a first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. When a read error occurs, a re-read procedure is executed for some of the memory cells belonging to a state marginal group. The read procedure includes: applying a read voltage to the first word line; applying a first pass voltage to the second word line and the third word line. The re-read procedure includes: applying the read voltage to the first word line; applying a second pass voltage and a third pass voltage different from the first pass voltage to the second word line and the third word line respectively.

IPC Classes  ?

• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents

Abstract

A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line.

IPC Classes  ?

• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents

Abstract

The application provides a panoramic perception method, system and a non-transitory computer readable medium. The panoramic perception method comprises: performing a first pretraining on a plurality of weights of a training model using the source database; performing a second pretraining with data augmentation on the plurality of weights of the training model using the source database; performing a combined training on the plurality of weights of the training model using both the source database and the target database; performing a quantization-aware training on the plurality of weights of the training model using the source database and the target database; performing a post training quantization on the plurality of weights of the training model using the target database; and performing panoramic perception by the training model.

IPC Classes  ?

• G06N 3/0495 - Quantised networksSparse networksCompressed networks
• G06N 3/08 - Learning methods
• G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads

Abstract

Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Abstract

The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

IPC Classes  ?

• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/66 - Types of semiconductor device