Abstract

An adaptive body biasing system for silicon on insulator semiconductor devices includes at least one biased logic domain; at least one adaptive body bias generator for generating variable bias voltage; at least one test pad for accessing the generated bias voltage generated by the at least one adaptive body bias generator; and at least one bias switch cell connecting the at least one adaptive body bias generator to the at least one test pad. The at least one bias switch cell is in high-resistive off state during normal operation of the semiconductor device and can be switched to low-resistive on state during test operation. The at least one adaptive body bias generator is connected to the at least one biased logic domain.

IPC Classes  ?

• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• G01R 31/26 - Testing of individual semiconductor devices
• G01R 31/27 - Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects due to surrounding elements

Goods & Services

Microcontrollers; Computer hardware for data processing; Electronic components for computers; Electronic transistors; Microprocessors; Mobile phones; Integrated circuits; Test and calibration equipment for computer components; Chips being integrated circuits; downloadable computer software for data processing; Electronic encryption devices; Electronic memories; Central processing unit (CPU) clocks; Blank smart cards; Digital-to-analog converters; Electronic telecommunication circuits; System-on-a-chip (SoC) Research in the field of computer hardware; microchip design services; integrated circuit design services; integrated circuit design; research in the field of electrical engineering; consultancy services in the field of control engineering; engineering services relating to the design of electronic systems Licensing of software; licensing of intellectual property and copyrights; licensing of industrial property rights; licensing of technology; licensing of patents

Goods & Services

Microcontrollers; Data processing equipment; Electronic components; Transistors [electronic]; Microprocessors; Mobile telephones; Integrated circuits; Computer component testing and calibrating equipment; Chips [integrated circuits]; Computer programmes for data processing; Electronic encryption units; Control circuits; Firmware; Electronic publications, downloadable; Electronic memories; Central processing unit [CPU] clocks; Integrated circuit cards [smart cards]; Electronic semi-conductors; Electronic sensors; Thermal controls; Analogue to digital converters; Telecommunications switches; System on a Chip [SoC]. Research in the field of computer hardware; Microchip design; Design services relating to integrated circuits; Technical consultancy in relation to the production of semiconductors; Design services relating to integrated circuits; Research in the field of electrical engineering; Control technology consulting services; Engineering services relating to the design of electronic systems. Licensing of computer software [legal services]; Licensing of intellectual property and copyright; Licensing industrial property rights; Licensing of technology; Licensing of patents.

Goods & Services

Electronic components; chips for integrated circuits; microprocessors; electronic memories; transistors; semiconductors; card readers; chipcards; electrical or electronic sensors; integrated circuit piezoelectric sensors; devices, apparatus and instruments for conveying, distributing, transforming, storing, regulating or controlling electric current; data processing programs; operating system software; chargers and systems to charge electric batteries; current transformers; electrical switches; electronic data encryption devices; electronic navigation instruments; telecommunication equipment and parts and accessories; telephones; mobile phones; electronic downloadable publications; electrical adapters; magnets; radios incorporating clocks. Training courses in the field of research and development; training in the field of integrated circuits design; training in the field of design of computer programs. Technical advice relating to technological research; engineering consultancy in the fields of computer software, hardware and telecommunications; design of computer microchips; product research and development; research and development and preparation of project analysis (technical reports), especially in the field of information technology, communications technology and other computer-related technologies. Licensing of software and licensing of intellectual property rights; licensing of technology.

Goods & Services

Electronic components, namely, for computing, communication and control systems; electronic chips for integrated circuits, namely, electronic chips for computing, communication and control circuits; microprocessors; electronic memories; transistors; semiconductors; electronic card readers; chipcards; electrical or electronic sensors for industrial and consumer products for sensing of temperature, pressure, light, motion, distance, and magnetic fields; integrated circuit piezoelectric sensors; devices, apparatus and instruments for conveying, distributing, transforming, storing, regulating or controlling electric current, namely, integrated circuits for automotive, medical, industrial and consumer electronics and devices; downloadable computer programs for data processing; downloadable computer software for operating system programs; chargers for electric batteries; current transformers; electrical switches; electronic data encryption devices, namely, namely, integrated electronic data encryption devices including chip components for Trusted Platform Modules and devices for securing electronic data transmission; electronic navigation instruments; telecommunication equipment and parts and accessories, namely, measurement equipment; telephones; mobile phones; electronic downloadable publications of journals, periodicals and books in the field of electronic devices and circuits; electrical adapters; magnets; radios incorporating clocks Training courses in the field of research and development in the field of integrated circuit design; providing training in the field of integrated circuits design; providing training in the field of design of computer programs Technical advice relating to technological research in the field of integrated circuit design; engineering consultancy in the fields of computer software, hardware and telecommunications; design of computer microchips; product research and development; research and development and preparation of project analysis being technical reporting in the nature of engineering consultancy, especially in the field of information technology, communications technology and other computer-related technologies Licensing of software and licensing of intellectual property rights; licensing of computer software and intellectual property rights of integrated circuit design

Abstract

The invention relates an adaptive body biasing system (1) for silicon on insulator semiconductor devices, comprising: at least one biased logic domain (2, 3); at least one adaptive body bias generator (4, 5) for generating variable bias voltage, wherein the at least one adaptive body bias generator (4, 5) is connected to the at least one biased logic domain (2, 3); at least one test pad (6) for accessing the generated bias voltage generated by the at least one adaptive body bias generator (4, 5); and at least one bias switch cell (7, 8) connecting the at least one adaptive body bias generator (4, 5) to the at least one test pad (6), wherein the at least one bias switch cell (7, 8) is in high-resistive off state during normal operation of the semiconductor device and can be switched to low- resistive on state during test operation.

IPC Classes  ?

• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• G01R 31/26 - Testing of individual semiconductor devices
• G01R 31/27 - Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects due to surrounding elements

Goods & Services

Electronic components for computers and for communication and control systems for industrial and consumer products composed of computers; Electronic chips for the manufacture of integrated circuits for computing, communication and control circuits; Microprocessors; Electronic memories; Transistors; Semiconductors; Electronic card readers; Chipcards; Electrical or electronic sensors for industrial and consumer products for sensing of temperature, pressure, light, motion, distance, and magnetic fields; Integrated circuit piezoelectric sensors; Devices, apparatus and instruments for conveying, distributing, transforming, storing, regulating or controlling electric current; Downloadable computer programs for data processing; Downloadable operating system programs; Chargers for electric batteries; Current transformers; Electrical switches; Electronic data encryption units; Electronic navigation apparatus for navigation by air vehicles; Telecommunication transceivers and component parts therefor; Telephones; Mobile phones; Electronic downloadable publications in the nature of journals, periodicals and books in the field of electronic devices and circuits; Electrical adapters; Magnets; Radios incorporating clocks Licensing of computer software and licensing of intellectual property rights; Licensing of computer software and intellectual property rights of integrated circuit design

Abstract

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IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G11C 5/14 - Power supply arrangements
• G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
• G06F 11/30 - Monitoring
• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/3312 - Timing analysis
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/39 - Circuit design at the physical level
• G06F 30/337 - Design optimisation
• G06F 30/30 - Circuit design
• H03K 3/03 - Astable circuits
• G06F 119/08 - Thermal analysis or thermal optimisation
• G06F 119/06 - Power analysis or power optimisation
• G06F 119/12 - Timing analysis or timing optimisation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

p of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/317 - Testing of digital circuits
• G06F 30/39 - Circuit design at the physical level
• H03K 3/03 - Astable circuits
• G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
• G06F 30/30 - Circuit design
• G06F 30/337 - Design optimisation
• G06F 30/3312 - Timing analysis
• G06F 119/12 - Timing analysis or timing optimisation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A RF frontend interface for a 61 GHz radio powered communication tag device with a built-in antenna includes an IC embedded in a silicon die with a top metallization layer and a dielectric resonant body linked to the silicon die. A high impedance antenna with two feed points is embedded into the top metallization layer and a RF rectifier and multiplier circuit connected to the antenna feed is integrated in the silicon die and symmetrically placed between the antenna feed points configured to stabilize the antenna resonant frequency with its inherent capacity against varying surrounding materials and generate a positive and negative DC output supply voltage against a bulk potential of the silicon die for directly operating a digital circuit in FDSOI technology embedded in the silicon die. The resonant body is configured to work as a wavelength translator in between the antenna and free space.

IPC Classes  ?

• G06K 19/02 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the selection of materials, e.g. to avoid wear during transport through the machine
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
• H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set
• H01Q 13/18 - Resonant slot antennas the slot being backed by, or formed in boundary wall of, a resonant cavity

Abstract

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements
• G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
• G01R 31/317 - Testing of digital circuits
• G06F 11/30 - Monitoring
• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/3312 - Timing analysis
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/39 - Circuit design at the physical level
• G06F 30/337 - Design optimisation
• G06F 30/30 - Circuit design
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H03K 3/03 - Astable circuits
• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
• G06F 119/08 - Thermal analysis or thermal optimisation
• G06F 119/06 - Power analysis or power optimisation
• G06F 119/12 - Timing analysis or timing optimisation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

IPC Classes  ?

• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
• H03K 17/16 - Modifications for eliminating interference voltages or currents
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

IPC Classes  ?

• G11C 5/14 - Power supply arrangements
• G01R 31/317 - Testing of digital circuits
• G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
• G06F 11/30 - Monitoring
• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation

Abstract

nmeann0jnjrefmean00.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

The invention relates to a slew-limited output driver circuit. The object of the invention to find a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD and short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror (P1, P2, respectively N1, N2) providing an output current equal to an input current, wherein the current mirror (P1, P2, respectively N1, N2) is controlled by means of an additional switch (P3, respectively N3), which is switched in response to control signals (prectl, fbe) and/or an output current level (PAD) of the output driver circuit, whereas adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

IPC Classes  ?

• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

Abstract

nomnomnom are considered by determining a reference performance F0 of a cell and a reference hardware performance monitor value C0 at the particular PVT corner, and a virtual regulation and adapting of body bias voltages of the cell set is performed such that said reference performance F0 of the cell or said reference hardware performance monitor value C0 will be reached at each PVT corner of said set of PVT corners and for compensating the static deviation in the supply voltage, and hence defining a set of PVTBB corners for each said PVT corner, and finally providing the results of characterizing the cell with adaptive body biasing in a library file.

IPC Classes  ?

• G06F 17/50 - Computer-aided design

Abstract

The invention discloses an apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit. The object to of the invention to efficiently generate the control voltages for active body biasing and to maintain the control voltages in the parts of the integrated circuit supplied with them will be solved by an apparatus for generation and adaptive regulation of body bias voltages of an integrated circuit comprising a digital circuit, a counter, a control unit and at least one charge pump, whereas the control unit and the digital circuit are connected in a closed control loop, and whereas the digital circuit comprises at least one hardware performance monitor, monitoring a timing of a body bias voltage, and whereas the control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit, whereas the charge pump is controllably connected to the control unit adjusting the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal. The object will also be solved by a method using the inventive apparatus.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems

Abstract

The invention discloses a method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit. The object to provide a method and a circuit for adaptation of the switching speed and hence to find a trade-off between delay time and leakage current consumption of an integrated circuit during operation will be solved by a circuit comprising a digital circuit, a counter, a control unit and a charge pump, whereas a first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors, wherein with a first closed control loop adaptively regulating the performance cn of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cP of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems

Abstract

A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
• H03L 7/08 - Details of the phase-locked loop