Rafael microelectronics, Inc.

Taiwan, Province of China

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        Patent 22
        Trademark 1
Jurisdiction
        United States 22
        Europe 1
Date
2023 3
Before 2021 20
IPC Class
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits 5
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation 4
H03G 3/30 - Automatic control in amplifiers having semiconductor devices 4
H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits 3
H03F 3/45 - Differential amplifiers 3
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1.

Fast automatic gain control circuit

      
Application Number 17693445
Grant Number 11870406
Status In Force
Filing Date 2022-03-14
First Publication Date 2023-09-14
Grant Date 2024-01-09
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor Chen, Kuan-Ming

Abstract

An automatic gain control circuit includes a control circuit for controlling a power detector, wherein the control circuit detects a power level change of an input signal and generates a control signal to the power detector so that the power detector can respond to the power level change of the input signal quickly.

IPC Classes  ?

  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

2.

Method of maximizing power efficiency for power amplifier system and power amplifier system thereof

      
Application Number 17676773
Grant Number 12224712
Status In Force
Filing Date 2022-02-21
First Publication Date 2023-08-24
Grant Date 2025-02-11
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Wang, Chung-Cheng
  • Tien, Kang-Ming
  • Wang, Tzu-Yun

Abstract

A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H04B 1/04 - Circuits

3.

Digital circuit for correcting mismatched IQ signals in a baseband receiver

      
Application Number 17688911
Grant Number 11711248
Status In Force
Filing Date 2022-03-08
First Publication Date 2023-07-25
Grant Date 2023-07-25
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor Lu, Hsin-Yu

Abstract

A digital circuit in a baseband receiver to compensate for the IQ mismatch by aligning the amplitude of Ĩ with {tilde over (Q)} and by aligning the phase of {tilde over (Q)} to be 90 degrees away from Ĩ.

IPC Classes  ?

  • H04L 27/227 - Demodulator circuitsReceiver circuits using coherent demodulation

4.

Adaptive equalizer for high speed serial data and related control method

      
Application Number 16509506
Grant Number 10855242
Status In Force
Filing Date 2019-07-12
First Publication Date 2020-12-01
Grant Date 2020-12-01
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Tang, Hao-Yun
  • Chang, Chia-Kai

Abstract

An equalizer system includes at least one equalizer configured to equalize an input signal to generate an equalized input signal; a limiting amplifier coupled to the at least one equalizer, and configured to amplify the equalized input signal to a saturated level to generate an output signal; and a control circuit coupled to the at least one equalizer and the limiting amplifier, and configured to generate at least one control signal to the at least one equalizer according to the equalized input signal to adjust a peak gain of the at least one equalizer, wherein the peak gain of the at least one equalizer is at a Nyquist frequency.

IPC Classes  ?

  • H04L 27/06 - Demodulator circuitsReceiver circuits
  • H03G 5/16 - Automatic control
  • H03G 5/00 - Tone control or bandwidth control in amplifiers
  • H04R 1/22 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired frequency characteristic only
  • H03G 5/24 - Automatic control in frequency-selective amplifiers

5.

Bias circuit for supplying a bias current to an RF power amplifier

      
Application Number 16402243
Grant Number 10965264
Status In Force
Filing Date 2019-05-03
First Publication Date 2020-11-05
Grant Date 2021-03-30
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Wu, Chih-Wen
  • Lin, Po Chang
  • Tseng, Chun Hua

Abstract

A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.

IPC Classes  ?

  • H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H03F 3/217 - Class D power amplifiersSwitching amplifiers
  • H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

6.

Bias circuit based on BiFET technology for supplying a bias current to an RF power amplifier

      
Application Number 16280050
Grant Number 10903797
Status In Force
Filing Date 2019-02-20
First Publication Date 2020-08-20
Grant Date 2021-01-26
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Wu, Chih-Wen
  • Chu, Szu-Yao

Abstract

A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.

IPC Classes  ?

  • H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
  • H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage

7.

Circuit with co-matching topology for transmitting and receiving RF signals

      
Application Number 16234581
Grant Number 10715089
Status In Force
Filing Date 2018-12-28
First Publication Date 2020-07-02
Grant Date 2020-07-14
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor Chen, Kuan-Ming

Abstract

A circuit with co-matching topology for transmitting and receiving RF signals for return loss improvement, wherein when transmitting RF signals, the LNA is turned off and the capacitance of an adjustable capacitive component is adjusted for transmitting RF signals, and when receiving RF signals, the power amplifier and the adjustable capacitive component are turned off, wherein a matching network is designed in favor of the LNA for receiving RF signals while the adjustable capacitive component can adjust the overall impedance of the circuit including the matching network that is also used when transmitting RF signals and the adjustable capacitive component for improving the transmitting return loss.

IPC Classes  ?

  • H03F 3/191 - Tuned amplifiers
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

8.

Operational transconductance amplifier

      
Application Number 16234595
Grant Number 10658992
Status In Force
Filing Date 2018-12-28
First Publication Date 2020-05-19
Grant Date 2020-05-19
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor Wang, Tzu-Yun

Abstract

A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.

IPC Classes  ?

9.

Single chip for generating multiple differential signals and loop-through signals according to a single-ended RF signal

      
Application Number 16202101
Grant Number 10637417
Status In Force
Filing Date 2018-11-28
First Publication Date 2020-04-28
Grant Date 2020-04-28
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Chen, Kuan-Ming
  • Chen, Yun-Yi
  • Wang, Tzu-Yun

Abstract

A single chip for generating multiple differential signals and loop-through signals according to a single-ended RF signal inputted to the single chip, wherein delays between different channels of the multiple differential signals and loop-through signals can be minimized for supporting picture-in-picture applications; in addition, the single chip can integrate a power detector and an AGC circuit for controlling the gain of an LNA inside the single chip, and the gain of the LNA can be outputted from the single chip for different usages.

IPC Classes  ?

  • H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
  • H03F 3/45 - Differential amplifiers
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices

10.

Laser power control system for laser diode using dual close loops

      
Application Number 16372368
Grant Number 10559940
Status In Force
Filing Date 2019-04-01
First Publication Date 2020-02-11
Grant Date 2020-02-11
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Wang, Kuan-Hsun

Abstract

The present invention discloses a laser power control system includes a laser diode, a monitor photodiode, a bias control circuit, a modulation control circuit, a digital controller, and a laser diode driver. The laser power control system forms an automatic extinction ratio control loop that is configured to control the extinction ratio of the laser diode by comparing a monitor current with a first target current to keep the extinction ratio of the laser diode at the predetermined first target current. The laser power control system forms an automatic power control loop that is configured to control the average power of the laser diode by comparing the monitor current with the second target current to keep the average power of the laser diode at the predetermined second target current.

IPC Classes  ?

  • H01S 5/042 - Electrical excitation
  • H01S 5/0683 - Stabilisation of laser output parameters by monitoring the optical output parameters
  • H01S 5/068 - Stabilisation of laser output parameters
  • H01S 5/06 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium

11.

Automatic gain control circuit with background calibration

      
Application Number 16026055
Grant Number 10601386
Status In Force
Filing Date 2018-07-03
First Publication Date 2020-01-09
Grant Date 2020-03-24
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Chen, Kuan-Ming
  • Chiang, Benjamin
  • Wang, Tzy-Yun

Abstract

An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.

IPC Classes  ?

  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • G01S 7/285 - Receivers

12.

Circuit with co-matching topology for transmitting and receiving RF signals

      
Application Number 15810147
Grant Number 10148239
Status In Force
Filing Date 2017-11-13
First Publication Date 2018-12-04
Grant Date 2018-12-04
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor
  • Lin, Ying Yao
  • Chiang, Tao

Abstract

A circuit with co-matching topology for transmitting and receiving RF signals, said circuit comprising: a first sub-circuit comprising a first inductive component and a first capacitive component to form a low-pass filter for transmitting a first RF signal from a first amplifier to an antenna, wherein the first inductive component is coupled to a ground via a first switch; and a second sub-circuit comprising a second inductive component and a second capacitive component for receiving a second RF signal from the antenna to an input terminal of a second amplifier, wherein said input terminal of the second amplifier is coupled to the ground via a second switch; wherein when the first amplifier is transmitting the first RF signal, the first switch is turned off and the second switch is turned on, and wherein when the second amplifier is receiving the second RF signal, the first switch is turned on and the second switch is turned off.

IPC Classes  ?

  • H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits

13.

Bias circuit for supplying a bias current to a RF power amplifier

      
Application Number 15663843
Grant Number 10141892
Status In Force
Filing Date 2017-07-31
First Publication Date 2018-11-27
Grant Date 2018-11-27
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor Wu, Chih-Wen

Abstract

A bias circuit for supplying a bias current to a RF power amplifier by using at least two voltage reference circuits coupled between the base terminal of a bipolar transistor and a voltage supply for generating a bias current to the RF power amplifier, wherein each of the at least two voltage reference circuits respectively clamps to a reference voltage at a corresponding terminal node of the voltage reference circuit on a conductive path having a current flowing from the voltage supply to the base terminal of the bipolar transistor, wherein when the current flowing out of the voltage supply increases, the current flowing through each of the at least two voltage reference circuits will also increases, so that the variation range of the bias current to the RF power amplifier will be kept in a smaller range compared with the variation range of the current flowing out of the power supply, thereby increasing the linearity of the RF power amplifier.

IPC Classes  ?

  • H03K 3/04 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of vacuum tubes only, with positive feedback
  • H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
  • H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F 3/20 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H04M 1/02 - Constructional features of telephone sets

14.

Signal receiver

      
Application Number 15235129
Grant Number 09647707
Status In Force
Filing Date 2016-08-12
First Publication Date 2017-05-09
Grant Date 2017-05-09
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor Kan, Meng-Ping

Abstract

A signal receiver includes a first mixer configured to mix its first input with its second input associated with an oscillating output of a first synthesizer into an output; a first splitter configured to split its input associated with the output of the first mixer into a first output and a second output; a first switch matrix configured to switch its first input associated with the first output of the first splitter into a first output; a second switch matrix configured to switch its first input associated with the second output of the first splitter into a first output; a second mixer configured to mix its first input associated with the first output of the first switch matrix with its second input associated with an oscillating output of a second synthesizer into an output; and a third mixer configured to mix its first input associated with the first output of the second switch matrix with its second input associated with an oscillating output of a third synthesizer into an output.

IPC Classes  ?

  • H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
  • H04B 1/08 - Constructional details, e.g. cabinet
  • H04B 7/185 - Space-based or airborne stations

15.

Multi-user satellite receiving system and method thereof

      
Application Number 15369816
Grant Number 09825661
Status In Force
Filing Date 2016-12-05
First Publication Date 2017-03-23
Grant Date 2017-11-21
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Tang, Hao-Yun

Abstract

An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the fourth oscillating signal.

IPC Classes  ?

  • H04H 20/74 - Wireless systems of satellite networks
  • H04B 1/26 - Circuits for superheterodyne receivers
  • H04B 15/00 - Suppression or limitation of noise or interference
  • H04B 1/28 - Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
  • H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
  • H04B 7/14 - Relay systems
  • H04N 21/40 - Client devices specifically adapted for the reception of, or interaction with, content, e.g. STB [set-top-box]Operations thereof
  • H04N 21/61 - Network physical structureSignal processing

16.

Rafael Micro

      
Application Number 015241193
Status Registered
Filing Date 2016-03-18
Registration Date 2016-07-07
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Video tuners; Radio tuners; Electronic tuners; Television signal amplifiers; Image amplifiers; Amplifier tuners; Amplifiers; Digital amplifiers; Optical amplifiers; Power amplifiers; Audio amplifiers; Radio-frequency components; Radio-frequency modulators; Radio frequency amplifiers; Chips [integrated circuits]; Semiconductor chips; Equalizers; Converters, electric; Voltage converters; Satellites; Satellite transmitters; Satellite receivers; Satellites for signal transmission.

17.

Integrated circuit chip for receiver collecting signals from satellites

      
Application Number 14884795
Grant Number 09819409
Status In Force
Filing Date 2015-10-16
First Publication Date 2016-02-04
Grant Date 2017-11-14
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Wu, Shi-Ming

Abstract

An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

IPC Classes  ?

  • H04B 7/185 - Space-based or airborne stations
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F 3/45 - Differential amplifiers
  • H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
  • H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

18.

Channel receiving apparatus and related channel receiving method

      
Application Number 14290940
Grant Number 09351036
Status In Force
Filing Date 2014-05-29
First Publication Date 2015-12-03
Grant Date 2016-05-24
Owner Rafael microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Hsieh, Chun-An

Abstract

A channel receiving apparatus includes: a first modulating device converts a first channel into a first predetermined frequency according to a first oscillating signal and a second oscillating signal; and a second modulating device converts a second channel into a second predetermined frequency according to a third oscillating signal and a fourth oscillating signal; wherein the first oscillating signal has a first frequency, the second oscillating signal has a second frequency, the third oscillating signal has a third frequency, and the fourth oscillating signal has a fourth frequency, when the third frequency is substantially equal to the first frequency, the third oscillating signal is arranged to be shifted by a predetermined frequency range to have a fifth frequency different from the first frequency, and when the second frequency is substantially equal to the first frequency, the second frequency and the first frequency are shifted by the predetermined frequency range.

IPC Classes  ?

  • H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
  • H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
  • H04H 40/90 - Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups specially adapted for satellite broadcast receiving
  • H04H 20/63 - Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for local area broadcast, e.g. instore broadcast to plural spots in a confined site, e.g. MATV [Master Antenna Television]
  • H03D 7/16 - Multiple frequency-changing

19.

Multi-user satellite receiving system and method thereof

      
Application Number 14243904
Grant Number 09548779
Status In Force
Filing Date 2014-04-03
First Publication Date 2015-10-08
Grant Date 2017-01-17
Owner RAFAEL MICROELECTRONICS, INC. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Tang, Hao-Yun

Abstract

An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the fourth oscillating signal.

IPC Classes  ?

  • H04H 20/74 - Wireless systems of satellite networks
  • H04B 1/40 - Circuits
  • H04B 7/00 - Radio transmission systems, i.e. using radiation field
  • H04B 1/06 - Receivers
  • H04B 1/26 - Circuits for superheterodyne receivers
  • H04B 15/00 - Suppression or limitation of noise or interference
  • H04B 1/28 - Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes

20.

Universal tuning module

      
Application Number 14287076
Grant Number 10609323
Status In Force
Filing Date 2014-05-26
First Publication Date 2015-01-29
Grant Date 2020-03-31
Owner Rafael Microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Chen, Kuan-Ming
  • Kan, Meng-Ping
  • Tang, Hao-Yun

Abstract

A universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner.

IPC Classes  ?

  • H04L 27/00 - Modulated-carrier systems
  • H03K 9/00 - Demodulating pulses which have been modulated with a continuously-variable signal
  • H04N 5/50 - Tuning indicatorsAutomatic tuning control
  • H04N 21/426 - Internal components of the client

21.

Low-noise signal amplifying circuit and method thereof

      
Application Number 13786464
Grant Number 08872590
Status In Force
Filing Date 2013-03-06
First Publication Date 2014-09-11
Grant Date 2014-10-28
Owner Rafael microelectronics, Inc. (Taiwan, Province of China)
Inventor Kan, Meng-Ping

Abstract

A signal amplifying circuit includes: a first transistor having a first connecting terminal coupled to an input signal, and a controlling terminal coupled to a first reference voltage; an adjustable resistive circuit having a first terminal coupled to a second connecting terminal of the first transistor; and a second transistor having a first connecting terminal coupled to a second terminal of the adjustable resistive circuit, a controlling terminal coupled to a second reference voltage, and a second connecting terminal for outputting an output signal corresponding to the input signal; wherein a resistance of the adjustable resistive circuit is adjusted to make an input impedance looking into the first transistor from the first connecting terminal equal a predetermined impedance.

IPC Classes  ?

  • H03G 3/10 - Manually-operated control in untuned amplifiers having semiconductor devices
  • H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

22.

Signal receiving circuit and the related signal receiving method

      
Application Number 13792244
Grant Number 08781427
Status In Force
Filing Date 2013-03-11
First Publication Date 2014-07-15
Grant Date 2014-07-15
Owner Rafael microelectronics, Inc. (Taiwan, Province of China)
Inventor Kan, Meng-Ping

Abstract

A signal receiving circuit includes an amplifier, a mixer, and a first controlling circuit. The amplifier includes: an input stage for receiving an input signal to generate a first signal; a gain stage coupled to the input stage for generating an output signal according to the first signal; and an output stage coupled to the gain stage for adjusting a spectral response of the amplifier according to a first adjusting signal. The mixer is coupled to the gain stage for generating a converted signal according to the output signal. The first controlling circuit is coupled to the mixer for detecting the converted signal to generate the first adjusting signal to adjust the spectral response of the amplifier.

IPC Classes  ?

23.

Low distortion active balun circuit and method thereof

      
Application Number 12690118
Grant Number 08222947
Status In Force
Filing Date 2010-01-20
First Publication Date 2011-07-21
Grant Date 2012-07-17
Owner Rafael microelectronics, Inc. (Taiwan, Province of China)
Inventor
  • Kan, Meng-Ping
  • Liu, Sheng-Liang

Abstract

A signal converting circuit includes: a first single-to-differential circuit arranged to generate a first signal having a first polarity and a second signal having a second polarity different from the first polarity; a second single-to-differential circuit arranged to generate a third signal having the second polarity and a fourth signal having the first polarity; and a combining circuit arranged to generate a first combined signal having the first polarity according at least two signals from the first signal, the second signal, the third signal, and the fourth signal, and output an output signal according to at least the first combined signal.

IPC Classes  ?

  • G06G 7/14 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for addition or subtraction
  • G06G 7/12 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor