A policy configuration method. The method comprises: a user terminal sending a policy acquisition request to a 4G communication module, wherein the policy acquisition request carries interface information about a first communication interface; the 4G communication module sending the policy acquisition request to a 5G communication module; in response to the policy acquisition request, the 5G communication module determining, on the basis of the interface information, whether to issue initial configuration policy information of the first communication interface; when it is determined to issue the initial configuration policy information, sending the initial configuration policy information to the 4G communication module; the 4G communication module determining calling path information on the basis of the received initial configuration policy information and sending the calling path information to the user terminal; and the user terminal acquiring target configuration policy information of the first communication interface from the 4G communication module on the basis of the received calling path information, and configuring the first communication interface on the basis of the target configuration policy information.
Disclosed are a pipelined successive approximation register analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation register analog-to-digital converter includes: a first-stage successive approximation register analog-to-digital converter (10), a residue amplifier (30), a second-stage successive approximation register analog-to-digital converter (20), and a digital coding unit (40).
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Provided in the embodiments of the present invention are an image glare detection method and apparatus. The method comprises: acquiring the average brightness of the current image block, a variation of the average brightness of the current image block with respect to the average brightness of a previous adjacent image block, and a color gradient difference of the current image block; when the average brightness of the current image block satisfies a preset brightness threshold value and there are marked start points of undetermined types, determining the types of the marked start points according to the variation of the average brightness of the current image block with respect to the average brightness of the previous adjacent image block, or the color gradient difference of the current image block; and reserving start points, the types of which are glare start points, among the marked start points, and after all the image blocks of an image are traversed, determining the boundary of a glare area of the image according to the reserved glare start points. Thus, the detection of a glare area of an arbitrary shape is realized, and the problem in the prior art that the minimum area, which is detected by means of a glare detection method, can only be an entire column, and it is impossible to detect a glare area of an arbitrary shape is solved.
Provided in the embodiments of the present disclosure are a method for determining the frequency of a clock signal, and an apparatus. The method comprises: inputting a clock signal into a frequency meter in a chip and, in response to an enable signal, the frequency meter counting the clock signal; at the end of a measurement window, the frequency meter stopping counting, and reading a count result as the frequency initial value of the clock signal; and, according to the frequency initial value, the reference clock frequency of the frequency meter and the time count value of the measurement window, determining the frequency value of the clock signal.
The present disclosure provides a demosaicing and sharpening combined processing method and apparatus, a device and a readable medium. The method comprises: processing raw data of a target color channel of an image sensor to obtain a full-resolution target color channel layer; sharpening the full-resolution target color channel layer to obtain a sharpening layer; and interpolating raw data of color channels of the image sensor other than the target color channel for demosaicing, and superimposing sharpening values of corresponding positions of the sharpening layer to the full-resolution target color channel layer and the demosaiced color channel layers on the basis of pixel coordinates for sharpening.
Provided are a sampling circuit and a sampling method. The circuit comprises: a generator, configured to generate a first loopback pulse signal; a loopback selection module, configured to establish a plurality of loopback links according to a pre-configured connection combination; a link loopback pulse signal transmission module, configured to receive the first loopback pulse signal, and transmit the first loopback pulse signal in the plurality of loopback links; a loopback sampling module, connected to the link loopback pulse signal transmission module and configured to determine, from the plurality of loopback links, a target loopback link on which sampling is to be performed, and sample first link data that is on the target loopback link and passes through a target sampling point, and a sampling storage module, connected to the loopback sampling module and configured to store sampling data in a random access memory.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
7.
TRAFFIC PROCESSING METHOD AND APPARATUS FOR OPTICAL TRANSPORT NETWORK, AND ELECTRONIC DEVICE AND STORAGE MEDIUM
Embodiments of the present application relate the technical filed of optical communications, in particular to a traffic processing method and an apparatus for an optical transport network, an electronic device, and a storage medium. The traffic processing method includes: obtaining an acquisition mode control signal for designating a type of a payload block (PB) to be acquired; performing data acquisition on a PB of an optical channel payload unit (OPU) frame mapped and multiplexed from an optical service unit (OSU) frame according to the designated type of the PB to be acquired to obtain acquired data; performing data statistics of the designated type of the PB according to the acquired data.
The present disclosure belongs to the technical field of communications. Provided are a method and apparatus for determining data transmission timing, and a device and a readable medium. The method comprises: acquiring the number of data packets corresponding to each data processing process in a data link layer; according to the number of data packets corresponding to each data processing process, determining a predicted consumed duration corresponding to each data processing process; and determining transmission timing of the data link layer according to the predicted consumed duration corresponding to each data processing process and the transmission priority of each data processing process.
Embodiments of the present disclosure provide a low-noise amplifier, a radio frequency receiver, and an electronic device. The amplifier is of a differential input/output structure, and the amplifier comprises: a first main amplifier (110), a second main amplifier (120), a first feedback amplifier (130), and a second feedback amplifier (140), wherein the first main amplifier (110) and the second main amplifier (120) have the same structure, the first feedback amplifier (130) and the second feedback amplifier (140) have the same structure, and the first main amplifier (110), the second main amplifier (120), the first feedback amplifier (130), and the second feedback amplifier (140) are all inverting amplifiers.
Provided in the present application are a switching configuration circuit and a switching configuration method. The switching configuration circuit comprises at least one transceiving configuration unit and at least one transceiving operating channel, wherein one transceiving configuration unit is connected to one transceiving operating channel; the transceiving configuration unit is configured to save a configuration parameter of at least one operation mode of at least one sub-unit of the transceiving operating channel, which is connected to the transceiving configuration unit, and if a configuration validation condition is met, send, to the transceiving operating channel which is connected to the transceiving configuration unit, a configuration parameter of an operation mode, which is required to be validated currently, of the at least one sub-unit of the transceiving operating channel; and the transceiving operating channel is configured to validate the configuration parameter of the operation mode, which is required to be validate currently, of the at least one sub-unit of the transceiving operating channel.
Provided in the present disclosure is a data processing method, which is applied to a first cache unit in a data processing system. The method comprises: predicting a second cache unit as a target cache unit; sending a first data reading request message to the second cache unit, the first data reading request message being used for reading first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data reading request message; and sending a first data reading response message to a node sending the first target data. Further provided in the present disclosure are a data processing system and a computer-readable storage medium.
Provided in the present application are a data detection method and apparatus. The data detection apparatus comprises: a rate de-matching module, a soft merging module, a decoding verification module, a processor and a first memory, wherein a program is stored in the first memory, and when the program is executed by the processor, at least one of the following steps is implemented: controlling whether to input at least one of a synchronization signal block index and a log-likelihood probability of a first synchronization signal block into the rate de-matching module by means of software or a hardware circuit; controlling whether to perform secondary de-scrambling processing and duplication rate de-matching processing on the log-likelihood probability of the first synchronization signal block by means of the rate de-matching module, so as to obtain a log-likelihood probability of a second synchronization signal block, or to perform secondary de-scrambling processing and duplication rate de-matching processing on the log-likelihood probability of the first synchronization signal block by means of the software, so as to obtain the log-likelihood probability of the second synchronization signal block; and controlling whether to input a system frame number index into the soft merging module by means of the software or the hardware circuit.
Provided in the present application are a method and apparatus for implementing a wireless communication algorithm, and a computer-readable medium. The apparatus for implementing a wireless communication algorithm comprises: an algorithm implementation module, the algorithm implementation module comprising a central processing unit, a crossbar switch and operator units. The operator units implement a corresponding data processing algorithm by means of hardware. The central processing unit is configured to: read microcode configuration information corresponding to the wireless communication algorithm, the microcode configuration information comprising hardware connection configuration information and hardware unit configuration information; according to the hardware connection configuration information, control the crossbar switch to connect the operator units into a combined operator unit; and, according to the hardware unit configuration information, configure the operator units in the combined operator unit, such that the combined operator unit can implement the corresponding data processing algorithm. The combined operator unit is configured to, according to the configuration of the combined operator unit, acquire data to be processed and perform corresponding data processing to obtain output data.
Provided in the present disclosure is a data processing method applied to a data processing apparatus in a data processing system. The method comprises: when a data exchange request message sent by a first cache unit is received, acquiring address information carried in the data exchange request, and determining first target data corresponding to address information in a memory; sending a notification message to the first cache unit; receiving second target data and third data which are sent by the first cache unit, wherein the third data is data that is to be subjected to data exchange with the first target data, and the second target data is data that a second cache unit has requested to read; and when the second target data is not equal to the first target data, returning, to the first cache unit, a data exchange response message that carries the third data.
A fault processing system and method, and a storage medium and an electronic apparatus. The system comprises: a fault management unit, which is connected to a security domain system and is configured to, when a fault occurs in the security domain system, perform first fault processing on the fault which occurs in the security domain system, and when the accumulated number of executions of the first fault processing exceeds a preset threshold and the fault has not been processed successfully, send to a central fault management unit fault information of the fault which has not been processed successfully; and the central fault management unit, which is connected to both the fault management unit and a system reset management unit, and is configured to perform second fault processing on the fault according to the fault information.
A semiconductor encapsulation structure, comprising: a substrate (206), an integrated circuit chip (203) arranged on the substrate (206), and a cover structure (201) covering the integrated circuit chip (203), wherein a first thermal interface material (202) fills the space between the inner side of the cover structure (201) and the integrated circuit chip (203); a blocking structure (207) for blocking the first thermal interface material (202) is arranged on the inner side of the cover structure (201); the blocking structure (207) comprises a blocking layer (207a); the blocking layer (207a) extends from a side wall of the integrated circuit chip (203) to the inner side of the cover structure (201); and a first space is formed between an inner wall of the blocking layer (207a) and the side wall of the integrated circuit chip (203). The semiconductor encapsulation structure can solve the problem in the prior art whereby an encapsulation structure deforms during a temperature cycling process and a large tensile stress is generated at a connection interface of a thermal interface material and a chip, which cause layering as a result; and bubbles in the thermal interface material can enter a side wall dam area along the flowing thermal interface material during an encapsulation process, which provides a path for the discharge of the bubbles, thereby reducing the generation of voids, and improving the encapsulation reliability.
Provided in the embodiments of the present disclosure are a chip and an electronic device. The chip comprises: a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, wherein the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to a preset granularity; each group of chip ports is connected to at least one of the plurality of groups of first ports and the plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is configured to control the gating of a path between each of the chip ports and the scanning test logic module according to a control instruction and in the unit of the preset granularity.
The present disclosure provides a multi-core synchronization system and a system component. The system comprises a neural network processor and a system component. The neural network processor comprises a task scheduling processor and a plurality of cores. The system component is connected to the task scheduling processor and the plurality of cores respectively by means of a system bus. The system component is used for performing communication among the plurality of cores under the control of the task scheduling processor, so that the plurality of cores synchronously execute allocated model tasks.
Disclosed in the present invention are a communication network-based service scheduling method, an apparatus, a device and a storage medium. A communication network comprises a service scheduling apparatus and at least one network device, the service scheduling apparatus executing the service scheduling method to schedule service data going to or coming from the network device via the communication network. The method comprises: in response to receiving service data, allocating the service data to a corresponding service queue according to a predetermined traffic allocation policy, and, according to a network device to which the service data belongs or the service type of the service data, allocating the service data to corresponding scheduling queues among a plurality of scheduling queues; and, according to the scheduling priorities of the plurality of scheduling queues, sending the service data in the plurality of scheduling queues.
H04L 41/0273 - Exchanging or transporting network management information using the InternetEmbedding network management web servers in network elementsWeb-services-based protocols using web services for network management, e.g. simple object access protocol [SOAP]
20.
FRONTHAUL MESSAGE PROCESSING METHOD AND APPARATUS, FRONTHAUL INTERFACE, COMMUNICATION DEVICE AND COMPUTER-READABLE STORAGE MEDIUM
The present disclosure provides a fronthaul message processing method, including: determining a type keyword of a fronthaul message according to a type of a transport layer for transmitting the fronthaul message; determining a type of the fronthaul message according to the type keyword; determining a position of service data carried by the fronthaul message according to the type of the fronthaul message; and extracting and processing the service data according to the position of the service data. The present disclosure further provides a fronthaul message processing apparatus, a fronthaul interface, a communication device, and a computer-readable storage medium.
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
21.
CIRCUIT, METHOD, AND APPARATUS FOR ACQUIRING RESISTANCE VALUE OF RESISTOR
A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the encapsulation network resistor Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.
G01R 27/08 - Measuring resistance by measuring both voltage and current
G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments
G01R 31/26 - Testing of individual semiconductor devices
22.
DELAY RIPPLE DETECTION METHOD AND DELAY RIPPLE DETECTION CIRCUIT
The present disclosure provides a delay ripple detection method and a delay ripple detection circuit. The method includes: generating a pulse signal corresponding to a transmission link to be monitored; aligning and transmitting the pulse signal corresponding to the transmission link and data corresponding to the transmission link in the transmission link; and monitoring the pulse signal after being transmitted in the transmission link, and determining whether a delay ripple anomaly is present in the transmission link according to the monitored pulse signal.
Embodiments of the present disclosure provide a coupling device for an integrated circuit package and a motherboard socket, comprising: a carrier and a pre-loading plate. The carrier is configured to mount a target integrated circuit package, and the target integrated circuit package is an integrated circuit package to be coupled to a target motherboard socket. The pre-loading plate is configured to fix the carrier on which the target integrated circuit package is mounted; the pre-loading plate and a plane structure on which the target motherboard socket is arranged are connected by means of a rotating pair; and when the pre-loading plate rotates around a common axis corresponding to the rotating pair to a target position, the target integrated circuit package mounted on the carrier is coupled to the target motherboard socket. By means of the present disclosure, the problem that the accuracy of coupling of the integrated circuit package and the motherboard socket is low is solved, thereby achieving the effect of improving the accuracy of coupling of the integrated circuit package and the motherboard socket.
H01R 13/631 - Additional means for facilitating engagement or disengagement of coupling parts, e.g. aligning or guiding means, levers, gas pressure for engagement only
H01R 33/76 - Holders with sockets, clips or analogous contacts, adapted for axially-sliding engagement with parallely-arranged pins, blades, or analogous contacts on counterpart, e.g. electronic tube socket
H01R 13/629 - Additional means for facilitating engagement or disengagement of coupling parts, e.g. aligning or guiding means, levers, gas pressure
24.
VECTOR OPERATION METHOD, VECTOR OPERATOR, ELECTRONIC DEVICE AND STORAGE MEDIUM
There are provided a vector operation method, a vector operator, an electronic device, and a computer-readable storage medium. The vector operation method includes: splitting a target vector operation to be performed to determine a plurality of basic operations in a predetermined execution order; sequentially generating, according to the predetermined execution order, a plurality of basic operation instructions corresponding to the plurality of basic operations; and sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on initial data to be subjected to the target vector operation, so as to implement the target vector operation on the initial data, wherein in two adjacent basic operations, to-be-calculated data for a latter basic operation is an operation result of a former basic operation.
The present application provides an antenna calibration method and apparatus, and a remote radio unit. The method includes: generating a calibration sequence of a channel to be calibrated; determining, according to obtained calibration configuration information of the channel to be calibrated and an output sequence of the channel to be calibrated, a calibration response sequence of the channel to be calibrated; and calibrating the channel to be calibrated according to the calibration response sequence of the channel to be calibrated and the calibration sequence of the channel to be calibrated.
Provided in the embodiments of the present disclosure are an access control method implemented by means of a hardware firewall, and a hardware firewall in a chip. The method comprises: by means of a firewall filtering layer corresponding to an access end, receiving an access request which is initiated by the access end to an accessed end, wherein the access request carries a permissions identifier and an access address; according to the access address, determining a target access area from among a plurality of access areas of the accessed end corresponding to the firewall filtering layer; and according to the permissions identifier and the target access area, determining access permissions of the access request, wherein each access area is pre-configured with a mapping relationship between permissions identifiers for allowing access and corresponding access permissions.
Provided in the present disclosure is a load scheduling method. The method comprises: receiving a message, and acquiring message flow information and service type information, which are carried in the message; determining a scheduling mapping table corresponding to the service type information, wherein each service type is configured with a scheduling mapping table, and the scheduling mapping table is used for recording a mapping relationship between each message flow and a corresponding processing element for processing the message flow; and determining, according to the scheduling mapping table, a processing element corresponding to the message flow information, and scheduling the message to the determined processing element for processing.
Provided in the present disclosure is a data storage method. Data is stored in a storage module comprising a plurality of RAMs, wherein each RAM comprises a plurality of physical rows. The method comprises: according to the occupation condition of a storage module, determining logical addresses used for storing target data to be stored, wherein each logical address represents a logical row and the locations in the logical row, and each logical row is composed of a plurality of physical rows from different RAMs; according to the determined logical address, determining a real address of said target data, wherein the real address is a physical address of a storage space corresponding to the logical address in each RAM; and storing said target data in the storage module according to the determined real address. Further provided in the present disclosure are a data storage device, and a computer-readable medium.
The present disclosure provides a power supply voltage drop detection device and system. The device comprises a gating unit, a first detection channel, and a second detection channel. In a first duration of a control cycle, the gating unit outputs a power supply voltage to the first detection channel, and outputs a threshold voltage to the second detection channel; and in a second duration, the gating unit outputs a threshold voltage to the first detection channel, and outputs a power supply voltage to the second detection channel. The first detection channel detects a first voltage characterization value of the first duration and a second voltage characterization value of the second duration, and outputs a first alarm signal when the first voltage characterization value is smaller than the second voltage characterization value. The second detection channel detects a third voltage characterization value of the first duration and a fourth voltage characterization value of the second duration, and outputs a second alarm signal when the fourth voltage characterization value is smaller than the third voltage characterization value.
Provided in the present disclosure is a chip. The chip comprises: a plurality of structurally identical multiplexing modules, wherein each multiplexing module is provided with a module input end and a module output end; a detection input pin, which is connected to the module input end of each multiplexing module and is used for inputting a detection signal into the module input end; a comparison module, which is provided with an input end and an output end, wherein the input end of the comparison module is connected to the module output end of each multiplexing module, the comparison module is used for receiving and comparing result signals, which are output by the multiplexing modules on their respective module output ends with respect to a detection signal, and outputting, on the output end of the comparison module, a comparison result for representing whether the result signals of all module output ends connected to the comparison module are completely the same; and a comparison output pin, which is connected to the output end of the comparison module and is used for outputting a signal representing the comparison result. Further provided in the present disclosure is a chip testing method.
The embodiments of the present disclosure provide a radio frequency (RF) signal generation method and device, and an RF transmitter, wherein the method comprises: respectively mixing an initial signal with a first local oscillator signal and a second local oscillator signal to obtain a first output signal, wherein the duty ratio of the first local oscillator signal and the duty ratio of the second local oscillator signal are each a target duty ratio, the phase of the first local oscillator signal differs from the phase of the second local oscillator signal by a target phase, with the exception of the phase, the remaining signal characteristics of the first local oscillator signal and second local oscillator signal are identical, and the target duty ratio and the target phase are set to be used for suppressing first harmonic waves and second harmonic waves generated during the signal transmission process; using a target filtering parameter to perform resonance filtering on the first output signal, to obtain a second output signal, wherein the target filtering parameter is set to be used for suppressing third harmonic waves generated during the signal transmission process, and wherein the first harmonic waves, the second harmonic waves, and the third harmonic waves are harmonic wave components for generating a third-order intermodulation signal and a mirror image signal.
Provided in the present disclosure is a decoding method, comprising: determining N unreliable positions in data to be decoded; determining M initial test sequences according to N unreliable bits, wherein the number of bits of each initial test sequence is N; selecting P final test sequences from among the M initial test sequences according to an initial parity check bit, wherein M>P, the initial parity check bit is a parity check bit corresponding to the first initial test sequence, and the P final test sequences comprise P initial test sequences having parity check bits of 1; and decoding said data by using the P final test sequences. Further provided in the present disclosure are a decoding apparatus, an electronic device and a computer-readable storage medium.
The present disclosure provides a display control method and apparatus for a vehicle, an electronic device and a storage medium. The vehicle has a display device. The display control method comprising: obtaining information related to driving of the vehicle; according to the information related to the driving of the vehicle, determining an area around the vehicle that requires attention; determining an image acquisition device capable of acquiring an image of the area that requires attention; and controlling a display device to display the image acquired by the determined image acquisition device.
B60Q 9/00 - Arrangement or adaptation of signal devices not provided for in one of main groups
B60R 1/22 - Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle
34.
FULL-DUPLEX DIGITAL SELF-INTERFERENCE CLEAR METHOD AND APPARATUS
The present disclosure provides a full-duplex digital self-interference clear method, including: before a signal is transmitted with a peer device in a full-duplex mode, performing a calculation by a self-adaptive algorithm to obtain a pre-distortion processing coefficient; under the condition that the signal is transmitted with the peer device in the full-duplex mode, performing pre-distortion processing on a first signal sent by the transmit link to the peer device according to the pre-distortion processing coefficient to obtain a second reconstructed interference signal; and performing self-interference clear according to the second reconstructed interference signal and a second interference signal of the receive link, with the second interference signal being a signal obtained through superimposition of an interference signal generated by the first signal in the receive link and a second signal received by the receive link from the peer device. The present disclosure further provides a full-duplex digital self-interference clear apparatus.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
Provided in the embodiments of the present disclosure are a data encryption processing method and apparatus. The method is applied to a microprocessor, which is connected to n encryption calculation units, n being a positive integer. The method comprises: acquiring data to be processed and a key; according to the data to be processed and the key, generating first target data consisting of m operators; sending a first operator among the m operators to a target encryption calculation unit for calculation, and storing as a first first result a calculation result returned by the target encryption calculation unit; and sending an ith operator and an (i-1)th first result to the target encryption calculation unit for calculation, and storing as an ith first result a calculation result returned by the target encryption calculation unit, wherein i=2, ..., m.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
Provided in the embodiments of the present disclosure are a package structure and a chip packaging method. The structure comprises: a first plastic packaging body, in which a first chip and a silicon wafer are packaged, wherein the silicon wafer is provided with a silicon through hole, and a bonding pad is connected to at least one end of the silicon through hole; a second plastic packaging body, which is stacked with the first plastic packaging body, wherein a second chip is packaged in the second plastic packaging body, at least one bonding pad of the second chip is connected to the first chip or the bonding pad of the silicon wafer on a first side of the first plastic packaging body by means of a first welding member, and the first side of the first plastic packaging body refers to the side adjacent to the second plastic packaging body; and a first redistribution layer, which is stacked on a second side of the first plastic packaging body, wherein the second side of the first plastic packaging body refers to the side opposite the first side, and the first chip and a bonding pad of the silicon wafer on the second side are connected to the first redistribution layer by means of a second welding member.
The present disclosure provides a method for training an image enhancement model, the image enhancement model includes an enhancement module including convolution branches corresponding to brightness intervals; and the method includes: inputting a sample image to the image enhancement model, and acquire a result image output by the image enhancement model; calculating losses including an image loss of the result image relative to a Ground Truth image, and a first constraint loss of brightness histogram constraint of each of the convolution branches of an image output from each of the convolution branches relative to the Ground Truth image; adjusting the enhancement module according to the losses; and in a case where a training end condition is not met, returning to the operation of inputting the sample image to the image enhancement model. The present disclosure further provides an image enhancement method and a computer-readable medium.
Embodiments of the present disclosure provide an image enhancement processing method and device. The method comprises: determining a gamut conversion matrix coefficient according to a gamut of an input image and a gamut of a display screen of a terminal; performing gamut conversion on the input image according to the gamut conversion matrix coefficient to obtain a converted input image; and performing brightness and saturation enhancement processing on the converted input image to obtain an output image. The problems in the prior art that the display of images exhibit an obvious color difference during image processing, and a color display effect during displaying of a low-gamut terminal is lower than the true colors of an original image a can be solved. Conversion between gamuts of different input images and gamuts of terminals having different gamut coverage rates is realized by means of gamut conversion matrix coefficients, the true colors of images can be better restored, and the image brightness and saturation can be quickly enhanced.
G09G 5/02 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
H04N 9/64 - Circuits for processing colour signals
39.
MESSAGE PROCESSING METHOD, O-RU AND COMPUTER-READABLE STORAGE MEDIUM
A message processing method includes: obtaining frequency-domain in-phase quadrature (IQ) data according to uplink data, and storing the frequency-domain IQ data in a storage space: receiving a control plane message issued by an Open Radio Access Network Distributed Unit (O-DU), analyzing the control plane message to obtain a control plane parameter, and caching the control plane parameter in a queue corresponding to the control plane parameter in a queue group, M queues in the queue group stores control plane parameters of M symbols; reading the control plane parameter, and generating a user plane message transmission scheduling command according to the control plane parameter; reading the frequency-domain IQ data from the storage space according to the user plane message transmission scheduling command; and obtaining an uplink user plane message to be sent according to the read frequency-domain IQ data, and sending the uplink user plane message to the O-DU.
H04W 72/044 - Wireless resource allocation based on the type of the allocated resource
H04L 47/628 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on packet size, e.g. shortest packet first
H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows
Embodiments of the present disclosure provide a sphere decoding detection method and apparatus. The method comprises: performing grouping rearrangement on a channel estimation matrix of a received signal to obtain an interference user group and a target user group; and first detecting the target user group, and then detecting the interference user group.
Provided in the present application are a data security protection method and apparatus, and an electronic device and a computer-readable medium. The data security protection method comprises: segmenting service data of m services according to the supported minimum service parallelism, so as to obtain segmented data units, and determining the number of channels required for processing the m services, wherein m is an integer greater than or equal to 1; sequentially mapping the segmented data units of the m services into channels corresponding to the respective services; and for each service, by using a key corresponding to the service, performing encryption processing or decryption processing on the segmented data units, which have been mapped into the channel corresponding to the service.
Provided in the present disclosure are a chip packaging assembly and an electronic device. The chip packaging assembly comprises an interposer, wherein a target signal line and a compensation inductor are arranged in the interposer, the target signal line is used for being electrically connected to an external device of the chip packaging assembly, and the compensation inductor is connected in series with the target signal line. The interposer comprises an interposer substrate, and at least one redistribution layer, a second via hole and a second trace, which are arranged on the interposer substrate, wherein the target signal line and the compensation inductor are arranged in the at least one redistribution layer, one end of the compensation inductor is electrically connected to the second via hole or the second trace on the interposer, and the other end of the compensation inductor is electrically connected to the target signal line. The compensation inductor is used for at least offsetting parasitic capacitance generated by the redistribution layer, the second via hole and the second trace, so as to improve the characteristic impedance.
Embodiments of the present disclosure provide a cell measurement method and a terminal. According to the embodiments of the present disclosure, a low-power-consumption processing unit can first measure a serving cell on the basis of a measurement object, then determine the relationship between a serving cell measurement result of the low-power-consumption processing unit and a plurality of S criterion signal measurement threshold value pairs, and according to the determination result, determine whether to wake up a main processing unit.
Provided are a power amplification apparatus and a transmitter. The power amplification apparatus includes power amplification modules each including a voltage output unit and a power amplification unit; the voltage output unit outputs a first voltage signal (VIN_A) and a second voltage signal (VIN_B). The power amplification unit includes a selector (MUX), a radio frequency processing circuit, and a first switch transistor (M1), the radio frequency processing circuit processes a baseband signal to output a first radio frequency signal to a source of the first switch transistor (M1), and the selector (MUX) is configured to correspondingly strobe the first voltage signal (VIN_A) or the second voltage signal (VIN_B) according to an operating state of the first switch transistor (M1).
The present application provides a power adjustment method and apparatus, an electronic device, and a computer-readable medium. The power adjustment method comprises: receiving an adjustment instruction issued by a base station, and according to the adjustment instruction and a first power of a terminal, determining a target first power; determining a second power of the terminal; according to the target first power and the second power, determining whether a third power of the terminal is within a defined range; if the third power is outside of the defined range, then according to a terminal final transmission power adjustment range, and according to the first power and the second power, determining a rapid power adjustment amount; and according to the rapid power adjustment amount, the target first power, and the second power, determining the final transmission power of the terminal, such that the final transmission power is within the final transmission power adjustment range.
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
46.
LINEARITY CALIBRATION METHOD AND APPARATUS FOR DTC, AND DIGITAL PHASE LOCK LOOP
The present disclosure provides a linearity calibration method for digital time converter, including: acquiring a phase prediction parameter and a locked phase error, and calculating a control word of a digital time converter according to the phase prediction parameter, the locked phase error, a pre-configured nonlinear predistortion function, and a pre-configured calibration order n, with the control word being configured to enable the digital time converter to adjust a delay of a reference clock, so as to keep the reference clock and a feedback clock which are input to a time digital converter in a tracked state. The present disclosure further provides a linearity calibration apparatus for digital time converter and a digital phase lock loop.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
47.
FREQUENCY OFFSET ESTIMATION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM
There are provided a frequency offset estimation method, a frequency offset estimation apparatus, an electronic device, and a computer-readable storage medium. The frequency offset estimation method includes: adopting a first frequency offset estimation method to perform frequency offset estimation on a demodulation reference signal (DMRS) sent from a terminal, to obtain a first frequency offset estimated value (100); adopting a second frequency offset estimation method to perform frequency offset estimation on the DMRS sent from the terminal, to obtain a second frequency offset estimated value (101); and determining a confidence factor according to the first frequency offset estimated value and the second frequency offset estimated value, and calibrating the second frequency offset estimated value according to the confidence factor to obtain a final frequency offset estimated value (102).
Provided are a signal processing method, an electronic device, and a storage medium. The signal processing method includes: acquiring control signal including a Time Division Duplex (TDD) signal (S110); adjusting time sequence of the TDD signal to target time sequence according to preset adjustment parameter (S120); and obtaining driving signal based on the TDD signal having the target time sequence, with the driving signal being for a Power Amplifier (PA) and a Low Noise Amplifier (LNA) (S130).
Provided in the present application are an image interpolation method and apparatus, and an electronic device and a computer-readable medium. The image interpolation method comprises: converting, into second coordinates in a coordinate system of an original image, first coordinates of a pixel point to be subjected to interpolation that are in a coordinate system of a target image; determining a direction value and direction reliability of a first pixel point corresponding to the second coordinates in the original image; and according to the direction value and direction reliability of the first pixel point, determining a final pixel value of the pixel point to be subjected to interpolation.
The embodiments of the present disclosure provide a neural network model pruning method and apparatus, wherein the method comprises: adding a branch to a convolution connection to be pruned and performing pruning training on the branch, wherein the branch comprises two first convolution layers; according to the pruning training result, judging whether the branch satisfies a pruning condition, and if so, obtaining the maximum number of pruning channels; pruning the branch according to the maximum number of pruning channels, and merging the pruned branch with the convolution connection, thereby completing pruning of the convolution connection.
Provided in the embodiments of the present disclosure are a detection method and apparatus for a primary synchronization signal (PSS) sequence. The detection method comprises: configuring a search parameter according to a search scenario of a primary synchronization signal (PSS) sequence; according to the search parameter, calling a resource for PSS-related calculation; performing periodic accumulation according to a related value of the PSS-related calculation and then performing a peak value search, and selecting a corresponding PSS sequence according to a peak value, so as to complete detection of the PSS sequence.
The present disclosure provides a method for calculating a sampling time offset, comprising: acquiring a plurality of sampling results of each sub-sampling module for an input signal; determining a sampling time offset of a reference sub-sampling module according to a plurality of sampling results of the reference sub-sampling module, first theoretical results corresponding to the sampling results, and second theoretical results corresponding to the sampling results, wherein the first theoretical results are theoretical values of the input signal at predetermined sampling time corresponding to the sampling results, the second theoretical results are theoretical values of a derivation signal at the predetermined sampling time corresponding to the sampling results, and the derivation signal is the derivative of the input signal; and determining a sampling time offset of a non-reference sub-sampling module according to the sampling time offset of the reference sub-sampling module, a plurality of sampling results of the non-reference sub-sampling module, the first theoretical results corresponding to the sampling results, and the second theoretical results corresponding to the sampling results. The present disclosure further provides a time-interleaved sampling device and a computer readable medium.
Provided in the present application are a data processing apparatus, a link training method, an electronic device, and a computer-readable storage medium. The data processing apparatus comprises a sending circuit and a receiving circuit, wherein the sending circuit comprises n parallel physical sending channels, and the receiving circuit comprises n parallel physical receiving channels, n being an integer greater than or equal to 2; each physical sending channel is configured to receive data from an upper layer, and to send the received data according to a first clock and a second clock; and each physical receiving channel is configured to receive, according to a third clock and a fourth clock, the data sent by each physical sending channel, and to cache the received data.
A traffic management system and method, a chip, and a computer-readable storage medium, relating to the technical field of communications. The method comprises: acquiring an inbound packet descriptor, determining a target idle pointer on the basis of the inbound packet descriptor, and writing inbound packet data corresponding to the inbound packet descriptor into an idle sub-cache area corresponding to the target idle pointer; according to a cache area ID corresponding to the idle sub-cache area where the inbound packet data is written into, performing linked list series-connection and linked list updating to generate queue linked list information; and determining an outbound packet descriptor correspondingly carried by a port scheduling instruction, determining, according to the queue linked list information, a target read pointer corresponding to the outbound packet descriptor, and reading, from a target sub-cache area corresponding to the target read pointer, packet data to be dequeued. High-performance and low-latency queue resource sharing can be implemented, and the performance loss caused by read-write conflicts of sharing queue resource in a multi-core forwarding architecture is reduced.
Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.
The present application provides an image denoising method, an image denoising apparatus, an electronic device, and a computer readable storage medium. The image denoising method comprises: determining the orientation value and the orientation reliability of a target pixel point in an original image; and denoising the target pixel point according to the orientation value and the orientation reliability of the target pixel point to obtain a denoised pixel value of the target pixel point.
Embodiments of the present disclosure relate to the technical field of image processing, and provide an image signal processing method and apparatus, a device, and a computer-readable storage medium. The method of the embodiments of the present disclosure comprises: acquiring a first image, and performing multi-channel feature extraction on the first image to obtain a multi-scale shared feature parameter; inputting the multi-scale shared feature parameter into each sub-task functional unit for multi-channel multi-task joint processing to obtain a multi-scale target feature parameter; and performing feature fusion on the multi-scale target feature parameter to obtain a fused feature parameter, and performing image construction according to the fused feature parameter, to obtain a second image for output.
Provided in the embodiments of the present disclosure are a code stream abnormality processing method and apparatus for a quality-of-service (QoS) rule cell. The method comprises: a user equipment (UE) decoding a QoS rule cell in a protocol data unit (PDU) session acceptance message or a PDU session modification command, and checking whether a code stream of the currently decoded QoS rule cell is abnormal; and when the code stream of the currently decoded QoS rule cell is abnormal, according to the current process type and whether the QoS rule cell, the code stream of which is abnormal, is a default QoS rule cell, determining whether to skip the QoS rule cell, the code stream of which is abnormal, so as to continue the decoding of a subsequent QoS rule cell.
The present disclosure provides signal detection method and apparatus, an electronic device, and a computer readable storage medium. The signal detection method includes: dividing nodes in a MT-th transmitting layer into M blocks, with MT representing a number of transmitting layers and M being an integer greater than or equal to 2; searching for a path corresponding to a central node of each block to obtain M paths, with the central node of each block being a node corresponding to a path with a smallest Euclidean distance among all nodes of the block; selecting N paths with smallest Euclidean distances from the M paths, with N being an integer less than M; searching for paths corresponding to all nodes of blocks where N nodes respectively corresponding to the N paths are located to obtain P paths; and selecting a path with a smallest Euclidean distance from the P paths.
Embodiments of the present disclosure provide a synchronization source switching method and apparatus. The method comprises: acquiring a sidelink synchronization signal sent by a reference terminal; acquiring the current frequency offset value every preset reporting period; determining a target sidelink synchronization signal according to the current frequency offset value and the sidelink synchronization signal; and setting a target reference terminal corresponding to the target sidelink synchronization signal as a synchronization source.
Provided in the embodiments of the present disclosure are a method for providing a clock signal in a data link, and an apparatus. The method comprises: in each clock domain among a plurality of clock domains of a data link, generating a reset pulse signal on the basis of an input synchronization reference signal and an input clock signal, generating an output synchronization reference signal on the basis of the input synchronization reference signal and the input clock signal, and generating an output clock signal on the basis of the input clock signal; and, by means of the reset pulse signal, resetting the output synchronization reference signal and the output clock signal, such that after the end of the reset pulse signal, a reset output synchronization reference signal and a reset output clock signal are synchronously generated at the next rising edge of the input clock signal, and are transmitted to the next clock domain via the same time delay, so as to serve as an input synchronization reference signal and an input clock signal of the next clock domain. The present disclosure decreases loads on synchronization reference signals, so as to reduce the uncertainty of time delay between different clock domains, and avoids problems such as being out of beat and metastable states.
Disclosed in the present disclosure are an image glare removal method, an electronic device and a computer storage medium. The image glare removal method comprises: determining a minimum channel image and a maximum channel image that correspond to an image frame in which glare is present; and adjusting the image frame according to the minimum channel image and the maximum channel image, so as to obtain an adjusted image from which color glare has been removed.
An image processing method, comprising: determining a plurality of segmentation areas according to road scene information of the current scene, wherein the road scene information corresponding to the same segmentation area has consistent features (S1); tracking the eyeballs of a driver according to facial information of the driver, so as to determine a focusing area, wherein the focusing area is a segmentation area corresponding to a gaze direction of the driver (S2); and according to the features of the road scene information corresponding to each segmentation area, and the focusing area, processing a head-up display image (S3). Further provided are a head-up display apparatus and a computer-readable medium.
Disclosed in the present disclosure is a switching network chip. The switching network chip comprises a plurality of input ports and a plurality of output ports, and a shared cache and a shared cache management module which are connected to the plurality of input ports and the plurality of output ports. The shared cache management module is configured to write, into the shared cache, cells received by means of the plurality of input ports, and read stored cells from the shared cache, so as to output the stored cells by means of the plurality of output ports. The shared cache management module is configured to measure a cache occupancy depth of each input port, a cache occupancy depth of each output port, and the total cache use depth of the shared cache, determine a load balance signal on the basis of a preset balance threshold and the cache occupancy depth of each input port, and perform load balance adjustment according to the load balance signal; determine a congestion adjustment signal on the basis of at least one of a preset congestion threshold, the cache occupancy depth of each input port, the cache occupancy depth of each output port and the total cache use depth; and perform congestion adjustment according to the congestion adjustment signal.
H04L 49/103 - Packet switching elements characterised by the switching fabric construction using a shared central bufferPacket switching elements characterised by the switching fabric construction using a shared memory
H04L 47/125 - Avoiding congestionRecovering from congestion by balancing the load, e.g. traffic engineering
65.
PAGING METHOD, COMMUNICATION APPARATUS, COMMUNICATION BASE STATION, AND COMPUTER-READABLE MEDIUM
Embodiments of the present application provide a paging method, a communication apparatus, a communication base station, and a computer-readable storage medium. The paging method comprises: receiving first paging information by means of a first processing unit of a communication apparatus, and obtaining a paging target group identifier according to the first paging information, the paging target group identifier being used for indicating at least one group to be paged to which a communication apparatus to be paged pertains; and according to the paging target group identifier, performing first paging by means of the first processing unit of the communication apparatus.
The present application provides a pattern information acquisition method and apparatus, an electronic device, and a readable storage medium. The method includes: sorting, according to reliability weight information of polar codes, a sequence to be processed to obtain a weight-based sequence; performing sequence search on the weight-based sequence to obtain a search result sequence, where the sequence search is used for acquiring a sequence corresponding to data having a reliability weight within a preset reliability threshold range; and mapping the search result sequence to the sequence to be processed to obtain pattern information that indicates position information of data of the search result sequence in the sequence to be processed.
The present disclosure relates to the technical field of wireless communications. Disclosed are a wireless communication method and apparatus, a communication device, and a storage medium. The wireless communication method comprises: acquiring a long-term signal-to-noise ratio measurement value for performing signal-to-noise ratio measurement on a wireless communication signal; adaptively selecting a filter coefficient according to the long-term signal-to-noise ratio measurement value, and performing infinite impulse response low-pass filtering according to the selected filter coefficient to obtain a stable long-term estimation value; and performing signal compensation according to the long-term estimation value, and updating the long-term estimation value according to an actual compensation value.
The present disclosure provides an image color saturation enhancement method, comprising: for each pixel in a first image in a preset color format, calculating an enhancement coefficient of the pixel according to the value of a preset channel of the pixel and a preset threshold; according to the enhancement coefficient of the pixel and the value of the preset channel, calculating the value of the preset channel of the pixel after being enhanced; and according to the value of the preset channel of each pixel after being enhanced, updating the value of the preset channel of the corresponding pixel in the first image, so as to enhance the color saturation of the first image to obtain a second image, wherein under the condition that the value of the preset channel of the pixel and the preset threshold meet a preset condition, the color saturation of the pixel in the second image is equal to the color saturation of the pixel in the first image. The present disclosure further provides a computer device and a computer readable storage medium.
An image processing method, an electronic device, and a computer-readable medium. The image processing method comprises: step S1, obtaining brightness adjustment reference information of a region to be processed in a current image frame, the brightness adjustment reference information representing the brightness state of the region to be processed; step S2, according to the brightness adjustment reference information, adjusting the brightness of each first pixel in the region to be processed, and obtaining a brightness mapping value of each first pixel; and step S3, adjusting a pixel value of each first pixel according to the brightness mapping value of each first pixel, and obtaining a target image corresponding to the current image frame.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
70.
COMMUNICATION CHIP AND OPERATION METHOD THEREFOR, COMMUNICATION DEVICE, AND NON-TRANSITORY COMPUTER STORAGE MEDIUM
Disclosed is a communication chip. The communication chip comprises: a fusion security module configured to perform, according to a plurality of communication security protocols, encryption/decryption processing on data to be processed, wherein the fusion security module comprises: an analysis module configured to receive said data and according to a packet type of said data, determine, from the plurality of communication security protocols, a target communication security protocol corresponding to the packet type; an enqueue module configured to determine, according to flow table information of said data, whether to perform encryption/decryption processing on said data; and an algorithm kernel module configured to perform, when the enqueue module determines to perform encryption/decryption processing on said data, encryption/decryption processing on said data according to the target communication security protocol to obtain encrypted/decrypted data.
Embodiments of the present disclosure provide a packet matching method and apparatus, a storage medium, and an electronic device. The method includes: determining multiple Hash calculation results corresponding to a key value of a packet; indexing addresses in multiple counter groups respectively according to the multiple Hash calculation results, so as to determine multiple counters, wherein one counter is indexed in one counter group; determining one target counter from the multiple counters; acquiring a target entry at a corresponding position of an off-chip memory according to the address of the target counter; in a case where the target entry is equal to the key value, determining that the packet matches the target entry.
Provided are a low-phase-shift variable-gain amplifier and a method for processing a radio frequency signal. The low-phase-shift variable-gain amplifier comprises: a differential cascode amplification circuit, which comprises a common-source transistor and a common-gate transistor, wherein a gate stage of the common-source transistor is connected to a first bias voltage via a target resistor, and a gate stage of the common-gate transistor is connected to a second bias voltage; a current-steering structure, wherein one end of the current-steering structure is connected between the common-source transistor and the common-gate transistor, a third current signal outputted by the current-steering structure is used to adjust a gain of the differential cascode amplification circuit; and a phase compensation circuit, wherein one end of the phase compensation circuit is connected between the common-source transistor and the common-gate transistor.
Provided in the present disclosure is a data processing method, comprising: determining the type of signal data; and performing online processing on the signal data according to the type of the signal data, so as to map the signal data onto a time-frequency resource to carry out transmission. Further provided in the present disclosure is a data processing apparatus.
The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.
Provided are a method and an apparatus for transmitting data, and a storage medium and an electronic device The method includes: compressing data according to a compression control instruction, so as to obtain compressed data, and acquiring a compression exponent; according to the compression exponent and a signal processing scaling exponent, determining a transmission exponent during data transmission; and according to an encapsulation format control instruction, based on an ORAN protocol, encapsulating the compressed data and the transmission exponent, so as to obtain encapsulated data, and sending the encapsulated data, such that after receiving the encapsulated data, a receiving end can perform decapsulation and decompression according to corresponding modes, so as to obtain data transmitted by a sending end.
Provided in the embodiments of the present disclosure are a data processing method and apparatus for a WiFi chip. The method comprises: acquiring from a wired-side interface first data to be processed in a sending direction; carrying out first-stage data processing on said first data by means of a first central processing unit, thereby obtaining first data; when the first central processing unit triggers a first interruption, caching the first data to a data forwarding queue in the sending direction; and when a second central processing unit triggers a data forwarding interruption in the sending direction, extracting second data from the data forwarding queue, and carrying out second-stage data processing on the second data by means of the second central processing unit.
Disclosed in embodiments of the present application are a phase shifter circuit and an electronic device. The phase shifter circuit comprises an impedance matching circuit and a vector synthesis circuit; the impedance matching circuit is connected to an input end and an output end of the vector synthesis circuit, and the impedance matching circuit is used for unifying previous-stage impedance and following-stage impedance of the vector synthesis circuit; the vector synthesis circuit is used for carrying out vector synthesis on input currents of different amplitudes, and the vector synthesis circuit comprises an orthogonal generation amplification circuit and a current multiplexing circuit; an input end of the orthogonal generation amplification circuit is connected to the impedance matching circuit, and an output end of the orthogonal generation amplification circuit is connected to an input end of the current multiplexing circuit; the orthogonal generation amplification circuit is used for carrying out the vector synthesis on the input currents of different amplitudes to obtain output signals having different phases and the same amplitude; an output end of the current multiplexing circuit is connected to the impedance matching circuit; and the current multiplexing circuit is used for providing multiplexed currents to the orthogonal generation amplification circuit to reduce power consumption, and is combined with the impedance matching circuit to optimize output impedance so as to realize ultra-wideband characteristics.
The present application relates to the field of communications, and provides a data retransmission method, an electronic device, and a computer readable storage medium. According to the present application, a packet data group in a current transmission period is sent to a receiving end, wherein the packet data group comprises a plurality of data sub-blocks; whether or not indication information fed back by the receiving end is received within a preset duration is detected, wherein the indication information indicates a serial number ID corresponding to a data sub-block which fails to pass the verification of the receiving end; and after it is determined that the indication information is received within the preset duration, the data sub-block associated with the serial number ID in the indication information is extracted from a retransmission cache region as data to be retransmitted, and said data is sent to the receiving end.
A resource queue management interface verification method includes: generating a verification instance; under a condition that a first resource queue management interface of the verification instance is connected to a second resource queue management interface of a master module to be verified, verifying the second resource queue management interface through the verification instance; under a condition that the first resource queue management interface is connected to a third resource queue management interface of a slave module to be verified, verifying the third resource queue management interface through the verification instance; and under a condition that the first resource queue management interface is connected to both the second resource queue management interface and the third resource queue management interface, verifying an interaction process between the second resource queue management interface and the third resource queue management interface through the verification instance.
Provided in the present application are a gain amplifier and a pipelined successive approximation register analog-to-digital converter. The gain amplifier comprises a passive gain network and a buffer. The passive gain network comprises at least one capacitor sampling array; each capacitor sampling array comprises n capacitors and (3n-2) switches, n being an integer greater than or equal to 1. The passive gain network is configured to, when the (3n-2) switches control the n capacitors to be connected in parallel, sample an input signal to obtain a sampled signal; and to, when the (3n-2) switches control the n capacitors to be connected in series, amplify the sampled signal to obtain an amplified signal. The buffer is configured to store and output the amplified signal.
Disclosed is a test apparatus, including: a connection circuit having a plurality of mounting positions each configured to connect a sample; a detection unit configured to perform a detection on the sample; and a control unit configured to control the detection unit to perform the detection on the sample. Further disclosed is a test method, including: connecting a sample to a mounting position of a test apparatus; and perform a test on the sample with the test apparatus.
G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
82.
MULTI-USER MULTIPLE-INPUT MULTIPLE-OUTPUT DETECTION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND MEDIUM
Provided are a multi-user multiple-input multiple-output detection method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: in a case where it is determined that received data includes data for first user equipment and data for at least one second user equipment, determining a first detection method according to a modulation mode of the first user equipment (100); and performing multi-user joint detection on the received data with the first detection method (101).
Provided are a frequency mixer, including: a transconductance circuit connected to an input signal terminal, and configured to generate a differential signal according to an input signal from the input signal terminal and output the differential signal through first and second output terminals of the transconductance circuit; a switch circuit connected to a local oscillator signal terminal and the first and second output terminals of the transconductance circuit, and configured to perform frequency mixing on a local oscillator signal from the local oscillator signal terminal and the differential signal to generate a mixed signal and output the mixed signal through first and second output terminals of the switch circuit; a load circuit connected to an output signal terminal and configured to provide a load; and an amplification circuit connected between the switch circuit and the load circuit and configured to amplify the mixed signal. A transceiver is also provided.
Disclosed in the present application are a sphere decoding detection method and apparatus, and an electronic device and a readable storage medium. The method comprises: performing orthogonal triangular QR decomposition on a channel response matrix, so as to obtain a Q matrix and an R matrix, wherein columns in the Q matrix are arranged according to the magnitude of channel energy; according to the Q matrix and the R matrix, determining a target equalization signal; executing an ML path search process according to the target equalization signal, so as to select N branches with the minimum metric as survivor paths; performing an ML complement path search on the survivor paths, so as to obtain ML complement paths; and using the survivor path with the minimum metric as an ML path, and obtaining likelihood ratio information of each bit of each symbol of each layer according to the ML path and the ML complement paths.
Provided in the present application is a method for determining a reselection determination parameter. The method includes: acquiring measurement information of a neighboring cell of a cell where a user equipment is currently camping; performing normalization processing of a predetermined rule on the acquired measurement information, and obtaining a reselection determination parameter that meets a predetermined requirement, where a reselection determination parameter obtained by performing the normalization processing of the predetermined rule on cell data of at least one system meets the predetermined requirement. The present disclosure further provides a method for cell reselection, an electronic device and a computer-readable storage medium.
An image processing method, comprising: acquiring a road condition image (S1); identifying at least one target region in the road condition image to obtain category information of each target region (S2); according to the category information of each target region, determining a display enhancement coefficient of each target region (S3); and according to the display enhancement coefficient of each target region, enhancing the road condition image to obtain a target image (S4). Further provided are an electronic device and a computer readable storage medium.
The present disclosure provides a circuit structure (100), an electronic device, and a mutual-capacitance structure design method. The circuit structure (100) comprises a carrier plate (1) and a plurality of signal pads (2) arranged on the carrier plate (1), and the circuit structure (100) further comprises mutual-capacitance structures (3) arranged on the carrier plate (1), wherein each mutual-capacitance structure (3) has a first end (31), a second end (32), and a mutual-capacitance coupling portion (33) located between the first end (31) and the second end (32), and the first end (31) and the second end (32) of each mutual-capacitance structure (3) are respectively connected to two of the plurality of signal pads (2).
H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Provided in the embodiments of the present disclosure are a vehicle fault processing method and a vehicle chip. The vehicle chip comprises: a large-computing-power computing unit, which is configured to perform target sensing on video data, so as to obtain a first target sensing result; and an information fusion unit, which is configured to determine a second target sensing result according to sensing data and the first target sensing result when it is determined according to the sensing data that the first target sensing result of the large-computing-power computing unit is correct. By means of the vehicle chip, the problem in the relevant art of a large-computing-power computing unit of a vehicle chip being unable to meet requirements regarding automotive safety integrity levels can be solved. The large-computing-power computing unit performs target sensing, the information fusion unit fuses the sensing data and the first target sensing result to obtain the second target sensing result, and on the basis of reducing a safety function level of the large-computing-power computing unit, the accuracy of target sensing performed by the large-computing-power computing unit is ensured by means of the information fusion unit, such that the chip can meet requirements regarding automotive safety integrity levels.
Embodiments of the present disclosure provide a base station fault diagnosis method and apparatus. The method comprises: acquiring operation data of a base station; obtaining feature value data of the base station according to the operation data; and inputting the feature value data into a fault diagnosis model for fault diagnosis so as to make a repair decision according to the fault diagnosis result.
A data processing method, comprising: receiving an energy-saving control signal (S110); receiving periodic synchronization signals (S120); in response to the energy-saving control signal being in a valid state, outputting an invalid clock signal, the invalid clock signal being a non-flip signal (S130); and in response to the energy-saving control signal being in an invalid state and the synchronization signals being received, outputting a valid clock signal, and processing data to be processed (S140). Further provided are an energy-saving control method, a chip, an energy-saving control apparatus, a filter, a data processing system and a computer-readable storage medium.
A cabin parameter setting method, and a computer device and a readable medium. The method comprises: acquiring identity feature information of a cabin user, and sending the identity feature information to a cabin parameter processing apparatus (2); and upon receiving a first configuration parameter which is sent by the cabin parameter processing apparatus (2), configuring a first configuration parameter for a preset component in a cabin, wherein the first configuration parameter is a configuration parameter, which is determined by the cabin parameter processing apparatus (2) and corresponds to the identity feature information. Therefore, personalized requirements of drivers and passengers for a cabin are satisfied, and the usage experience of the drivers and passengers is greatly improved.
B60R 16/037 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for occupant comfort
B60N 2/02 - Seats specially adapted for vehiclesArrangement or mounting of seats in vehicles the seat or part thereof being movable, e.g. adjustable
B60H 1/00 - Heating, cooling or ventilating devices
92.
RADIO-FREQUENCY DATA SYNCHRONIZATION METHOD AND APPARATUS, AND ELECTRONIC DEVICE AND READABLE STORAGE MEDIUM
Disclosed in the present application are a radio-frequency data synchronization method, a radio-frequency data synchronization apparatus, an electronic device, and a computer-readable storage medium. The radio-frequency data synchronization method comprises: acquiring a synchronization signal generated by an off-chip reference source, and sampling the synchronization signal on the basis of a high-frequency clock signal, so as to obtain a sampled synchronization signal; performing frequency division on the high-frequency clock signal, so as to obtain first frequency-division clock signals; performing phase synchronization on each of the first frequency-division clock signals on the basis of the sampled synchronization signal, so as to obtain first synchronized frequency-division clock signals; sampling the sampled synchronization signal on the basis of each of the first synchronized frequency-division clock signals, so as to obtain first frequency-division sampled synchronization signal; and on the basis of the first synchronized frequency-division clock signals and the first frequency-division sampled synchronization signals, synchronizing radio-frequency channel data that passes through data converters in radio-frequency transmission channels.
Embodiments of the present disclosure provide an analog-to-digital conversion device and method. The analog-to-digital conversion device comprises: an analog-to-digital converter, wherein the analog-to-digital converter comprises N successive approximation register (SAR) analog-to-digital converters and M slope analog-to-digital converters, N is a positive integer greater than or equal to 1, and M is a positive integer greater than 1; and the output ends of the N SAR analog-to-digital converters are connected to the input ends of the M slope analog-to-digital converters.
Provided in the embodiments of the present application are a calibration method and apparatus for a channel gain mismatch of an ADC, and a circuit. The method comprises: inputting, into a non-reference channel of an ADC, an analog input value determined on the basis of a reference channel, so as to obtain a first digital output code value corresponding to the non-reference channel; respectively comparing the first digital output code value with a first threshold value and a second threshold value, and according to comparison results, adjusting an initial value of a channel gain calibration code corresponding to the non-reference channel; and assigning the adjusted channel gain calibration code to the non-reference channel, so as to complete the operation of channel gain calibration.
Embodiments of the present disclosure provide a time delay circuit synchronization method and apparatus. The method comprises: by taking a synchronous pulse signal generated by an air interface pulse signal as a reference, a radio frequency chip initializes all clock dividers so as to synchronize initial phases of a plurality of system clocks generated by frequency division of a high-frequency clock, and aligns a read pointer or a write pointer on a first buffer random access memory (RAM) of the radio frequency chip on the basis of the synchronous pulse signal so as to synchronize a plurality of transmit channels.
Embodiments of the present disclosure provide a timing adjustment method and apparatus for a clock tree. The method comprises: configuring a plurality of driving units of different timings according to clock tree timing usage requirements of a chip, wherein target layouts of the plurality of driving units are the same; constructing a clock tree according to the plurality of driving units, and performing a timing check on the clock tree to obtain a timing check result; and when the timing check result is that a first target driving unit in the clock tree has a timing violation, replacing the first target driving unit with other driving units, wherein other driving units are driving units other than the first target driving unit among the plurality of driving units. The embodiments of the present disclosure can solve the problems in the related art that clock tree timing adjustment requires multiple placements & routings and thus consumes a lot of time and additional metal layer winding resources, thereby achieving quick adjustment of the clock tree timing, effectively saving the back-end synthesis and placement & routing time, and improving the rear-end synthesis efficiency.
Provided in the present disclosure are an instruction scheduling processing method and apparatus, and a storage medium and an electronic apparatus. The instruction scheduling processing method comprises: according to a data dependency relationship, constructing a directed acyclic graph from instructions to be scheduled of the current basic block to be scheduled, wherein the directed acyclic graph is formed by a plurality of nodes; acquiring a plurality of currently scheduled instructions from top to bottom and from bottom to top; determining a target heuristic value of the plurality of instructions respectively according to scheduled instructions and unscheduled instructions in the directed acyclic graph; and scheduling the plurality of instructions according to the target heuristic value.
Provided in the present application are a defect pixel detection method and apparatus, and a device and a medium. The defect pixel detection method comprises: from a visible neighborhood of a target pixel among pixels to be subjected to detection in an image to be subjected to detection, determining a color filter array (CFA) pattern which contains the target pixel, and a CFA instance block which contains the target pixel (S10); defining a feature space transformation matrix, wherein the feature space transformation matrix is a multi-dimensional matrix, and the size of the feature space transformation matrix in each dimension is the number of pixels of the CFA pattern (S20); performing feature space transformation on the CFA instance block by using the feature space transformation matrix, so as to obtain a feature space transformation result (S30); and determining a defect pixel mask of the target pixel on the basis of the feature space transformation result, and on the basis of the defect pixel mask, determining whether the target pixel is a defect pixel (S40).
The present application provides a clock tree gate delay optimization method and system, and a device and a computer storage medium. The clock tree gate delay optimization method comprises: determining clock trees in chips in a plurality of simulation application scenarios; sequentially providing a simulation test circuit corresponding to the clock tree in each of the simulation application scenarios, and performing a simulation test on each simulation test circuit; according to a simulation test result, determining a target inverting unit corresponding to the clock tree in each of the simulation application scenarios, and storing all the target inverting units in a preset layout in the form of a preset suite; and after it is detected that there is a clock tree to be operated in a chip to be operated, determining a target matching inverting unit that matches the clock tree to be operated and is in the preset layout, and connecting the target matching inverting unit to the clock tree to be operated, so as to perform an operation.
The present disclosure provides a link deterministic delay determination method, applied to a receiving end, comprising: according to a preset frequency division multiple and a preset frequency multiplication multiple, performing frequency division processing and frequency multiplication processing on an initial frame boundary to obtain a frequency multiplication frame boundary, wherein the frequency multiplication frame boundary is used for writing data received from a link into a cache of the link, or is used for reading the data received in the link from the cache; and determining a link deterministic delay according to an estimated link absolute delay and the frequency multiplication frame boundary. A link deterministic delay having a flexible value can be obtained, such that the problem of limited values of a deterministic delay, the problem of delay waste caused by a smaller absolute delay but a larger deterministic delay of a link, and the problem of high complexity of circuit design caused by a larger absolute delay but a smaller deterministic delay of the link are solved, and the complexity of circuit design is reduced. The present disclosure further provides a receiving end, an electronic device, and a computer storage medium.
patents
