42 - Scientific, technological and industrial services, research and design
Goods & Services
Technical support services, namely, 24/7 monitoring of network systems, servers and web and database applications and notification of related events and alerts; Technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; Technical support services, namely, troubleshooting of computer software problems; Computer technology support services, namely, help desk services; Computer technical support services, namely, 24/7 service desk or help desk services for software applications and programs
42 - Scientific, technological and industrial services, research and design
Goods & Services
Technical support services, namely, 24/7 monitoring of network systems, servers and web and database applications and notification of related events and alerts; Technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; Technical support services, namely, troubleshooting of computer software problems; Advisory services in the field of product development and quality improvement of software; Advisory services relating to computer software; Computer technical support services, namely, 24/7 service desk or help desk services for IT infrastructure, operating systems, database systems, and web applications; Computer technology support services, namely, help desk services; Consultation services relating to computer software; Troubleshooting of computer software problems; Troubleshooting of computer database software applications; Updating of computer software relating to computer security and prevention of computer risks
42 - Scientific, technological and industrial services, research and design
Goods & Services
Software as a Service (SaaS) services featuring software for processing data; Software as a Service SaaS) services featuring software for creating risk reports; Software as a Service (SaaS) services featuring software for improving computer security; technical research in the field of information technology hardware and software, security software, and cybersecurity software; technical research in the field of cybersecurity software; computer software technology consulting services in the field of information technology, security technology, and cybersecurity; computer security consultation services in the field of cybersecurity; computer security consultancy in the field of scanning and penetration testing of computers and networks to assess information security risks; Software as a Service (SaaS) services featuring software for improving the security of the software of others; Software as a Services (SaaS) services featuring software for analyzing source code and software code
42 - Scientific, technological and industrial services, research and design
Goods & Services
Software as a Service (SaaS) services featuring software for processing data; Software as a Service SaaS) services featuring software for creating risk reports; Software as a Service (SaaS) services featuring software for improving computer security; research in the field of information technology, security technology, and cybersecurity; cybersecurity research; consulting services in the field of information technology, security technology, and cybersecurity; cyber security consulting services; computer security consultancy in the field of scanning and penetration testing of computers and networks to assess information security risks; Software as a Service (SaaS) services featuring software for improving the security of the software of others
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer software, namely, downloadable computer operating systems software, and recorded software used in connection with computer operating systems
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware, computer software, namely, downloadable computer operating systems software, and recorded computer operating systems software Computer software, namely, providing temporary use of online, non-downloadable computer operating systems software and online, non-downloadable software for analyzing computer programming language used in connection with computer operating systems
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer software, namely, downloadable computer operating systems software, and recorded software used in connection with computer operating systems
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer software, namely, downloadable computer operating systems software, and recorded software used in connection with computer operating systems
9.
Code optimization for connected managed runtime environments
A first instance of a managed runtime environment is provided. An optimized version of a code unit and a corresponding set of one or more speculative assumptions are received at the first instance of the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, and wherein the optimized version of the code unit and the corresponding set of one or more speculative assumptions are generated by an entity that is different from the first instance of the managed runtime environment. The optimized version of the code unit is executed at the first instance of the managed runtime environment. Whether the set of one or more speculative assumptions hold true is monitored at the first instance of the managed runtime environment.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware; computer software, namely, downloadable computer operating systems software, and recorded software used in connection with computer operating systems Providing temporary use of online, non-downloadable computer operating systems software and online, non-downloadable software used in connection with computer operating systems
11.
Code optimization for connected managed runtime environments
A first instance of a managed runtime environment is provided. An optimized version of a code unit and a corresponding set of one or more speculative assumptions are received at the first instance of the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, and wherein the optimized version of the code unit and the corresponding set of one or more speculative assumptions are generated by an entity that is different from the first instance of the managed runtime environment. The optimized version of the code unit is executed at the first instance of the managed runtime environment. Whether the set of one or more speculative assumptions hold true is monitored at the first instance of the managed runtime environment.
42 - Scientific, technological and industrial services, research and design
Goods & Services
Providing information for the open source software development and software engineering communities, namely, analysis of security patches, platform-level updates and backported functionality, and guidance and commentary regarding new and alternative use cases for specific language and runtime features
42 - Scientific, technological and industrial services, research and design
Goods & Services
Providing information for the open source software development and software engineering communities, namely, analysis of security patches, platform-level updates and backported functionality, and guidance and commentary regarding new and alternative use cases for specific language and runtime features
14.
Code optimization conversations for connected managed runtime environments
A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.
A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.
A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and commit at least some of the one or more memory modification instructions. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units is not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and establish an incidentally atomic sequence of instruction units based at least in part on detection of the atomicity terminating event, wherein the incidentally atomic sequence of instruction units correspond to a sequence of instruction units in the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.
G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G06F 9/00 - Arrangements for program control, e.g. control units
G06F 9/44 - Arrangements for executing specific programs
G06F 15/00 - Digital computers in generalData processing equipment in general
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
22.
CPU utilization metering on systems that include multiple hardware threads per core
Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one or more hardware threads to determine an event count; deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count; applying a corrective function to modify the initial measure of usage and determine a modified measure of usage, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.
A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster including a second plurality of processors associated with a second cluster cache, and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster. The first cluster includes a first unshared connection to the cluster communication network and the second cluster includes a second unshared connection to the cluster communication network.
Executing a set one or more instructions is disclosed. A set of one or more register states is saved in a software data structure. The set of instructions is speculatively executed. At least one store made to a memory location during the speculative execution is not committed until the speculative execution is successfully completed. If an abort indication is received, the state of one or more registers restored.
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer software platform for use with computer operating systems and hypervisors for improving elasticity, scalability, visibility and performance consistency benefits to all application programs written in certain programming languages, and for managing the frequency and impact of de-optimization in managed runtimes, and for providing developers and operations personnel with the ability to control the runtime behavior of software running in specific virtual machines, to delay or remove features that are otherwise automatic within the running software, to prevent de-optimization, stalling and poor performance during, for example, financial market opening and dramatic changes in financial market conditions
Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.
Memory management includes identifying a region of virtual memory to be reclaimed, the region including an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; releasing the portion of the memory resource so that the portion of memory resource can be reused; and after the portion of the memory resource is released, replacing a reference of the object that points to the original virtual memory location with a reference of the object that points to the target virtual memory location.
Stitching a proxied connection between a first core virtual machine (VM) and a second core VM is disclosed. Stitching includes determining that a stitched connection should be generated between the first core VM and the second core VM and generating the stitched connection between the first core VM and the second core VM.
Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer software and downloadable computer software, all featuring a runtime system or environment, for use in developing and executing other computer programs
Memory management includes identifying a region of virtual memory to be reclaimed, the region including at an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; remapping one or more references to the object to the target virtual memory location; and releasing the portion of the memory resource prior to or contemporaneously with remapping the one or more references to the target location.
Interacting with an external environment of a segmented virtual machine is disclosed. An indication that a communication with an external environment is desired is received. It is determined whether the communication can be initiated directly from a core virtual machine of the segmented virtual machine without initiating the communication from a shell virtual machine of the segmented virtual machine. An attempt to initiate the communication is made based as at least in part on the determination.
Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.
Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.
Reaching a determination associated with a class of an object is disclosed. An identifier associated with the class of the object is extracted from a pointer to the object. The extracted identifier is compared to a comparison value. At least in part using a result of the comparison a determination is reached.
Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.
Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.
Executing a set one or more instructions atomically is disclosed. Executing includes saving a set of one or more register states in a software data structure, speculatively executing the set of instructions, and restoring the state of one or more registers when an abort indication is received.
Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.
Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.
Executing a set of one or more instructions atomically is disclosed. Executing includes determining whether speculatively executing the instructions is advised based at least in part on dynamic information associated with synchronization data and speculatively executing the instructions when it is determined that speculatively executing the instructions is advised.
A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a set of garbage collection instructions configured to perform one or more garbage collection barrier operations and a subsequent instruction that immediately follows the garbage collection instruction; wherein the processor is configured to execute the set of garbage collection instructions, including by: evaluating a memory reference to determine a condition associated with the set of garbage collection instructions; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.
A technique is disclosed for redirecting information in a segmented virtual machine. The technique includes sending information to a shell VM and redirecting the information to bypass the shell VM. A technique for evaluating whether to redirect information may include sending a discovery packet, receiving a reply to the discovery packet; and determining whether a switch is capable of stitching based on the reply. A technique for responding to a discovery packet may include receiving the discovery packet at a switch and sending a response indicating a capability of the switch.
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer software platform for use with computer operating systems and hypervisors for improving elasticity, scalability, visibility and performance consistency benefits to all application programs written in certain programming languages, all aforementioned goods excluding computer software for gaming
A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's are implemented in a common core space. Each core VM is associated with a shell VM. Resources of the core space are allocated among the core VM's. A core VM is associated with a shell VM configured to perform shell VM functions and communicate with the core VM. VM internal execution functionality is performed on the core VM. The shell VM may be bypassed to communicate with an external application.
A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage collection barrier instruction; wherein the processor is configured to execute the garbage collection barrier instruction, including by: evaluating a memory reference to determine a condition associated with the garbage collection barrier instruction; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.
A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's is implemented in a plurality of core spaces. Each core VM is associated with one of a plurality of shell VM's. Resources of the core spaces are allocated among the core VM's.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.
Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.
Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.
Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.
Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
53.
Memory management based on concurrent garbage collection using safepoints
Managing memory comprises execute a mutator comprising a plurality of mutator threads, and concurrently execute a garbage collector. Each of the plurality of mutator threads is separately stopped and notified, and is interrupted at a respective safepoint. In some cases executing the garbage collector includes remapping one or more references to one or more objects in an existing from-space, releasing the existing from-space, relocating one or more live objects that currently reside in a new from-space to one or more corresponding new locations, and identifying a set of one or more candidate pages suitable for forming next from-space during next garbage collection iteration.
A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.
Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.
A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.
Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.
A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread information with information related to a decreasing ability of the processor core to increase throughput by utilizing additional hardware threads, and indicating the usage in the system based at least in part on both the active thread information and the ability of the processor core to increase throughput by utilizing additional hardware threads.
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread information with information related to a decreasing ability of the processor core to increase throughput by utilizing additional hardware threads, and indicating the usage in the system based at least in part on both the active thread information and the ability of the processor core to increase throughput by utilizing additional hardware threads.
G06F 15/00 - Digital computers in generalData processing equipment in general
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/44 - Arrangements for executing specific programs
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
61.
Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system
A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.
Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag
A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation. All ordering, data, and invalidation acknowledgement messages must be received by the requesting filter pipe before loading the data into its cache.
Variable-length packets transmitted over a serial link do not have packet-start fields or unique symbols to mark the beginning of each packet. Instead, a length field indicates the packet's length, allowing the end of the packet to be located. Packets also do not have sequence numbers. When an error is detected, the receiver sends a control symbol over a reverse channel to signal the transmitter. The control symbol never occurs in a normal packet. Packet buffers in the transmitter and receiver have read and write pointers and also have de-allocation pointers that are synchronized between receiver and transmitter. As packets are error checked, the receiver advances its de-allocation pointer and updates the transmitter's de-allocation pointer, allowing the packets to be discarded from the transmitter's buffer only after the receiver finishes error checking. The transmitter re-transmits packets from its buffer starting from the de-allocation pointer when its receives the control symbol.
Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to all snoop tag partitions on all cluster chips. Each snoop tag partition has all the system's snoop tags for a partition of the main memory space. The snoop index is a subset of the cache index, with remaining chip-select and interleave address bits selecting which of the snoop tag partitions on the multiple cluster chips stores snoop tags for that address. The number of snoop entries in a snoop set is equal to a total number of cache entries in one cache index for all local caches on all cluster chips. Cache coherency request processing is distributed among the snoop tag partitions on different cluster chips, reducing bottlenecks.
A method, system, and computer program product for managing a heap of memory allocated to a program being executed on a data processing system is disclosed. A limited amount of memory is allocated to a program being executed by a mutator on a data processing system. The memory comprises memory objects. The disclosed method identifies memory objects, which are allocated to the program but are not referenced anymore. These dead memory objects are freed and made available for further allocation in the program. The memory objects that are still referenced are organized in compact contiguous blocks. Thus, the disclosed method recycles memory allocated to the program. The disclosed method is executed iteratively and concurrently with the execution of the program. The disclosed method does not interfere with program execution. Amount of memory required is specified before the commencement of the disclosed method and the same amount is freed without any surplus.
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer software for use with computer operating systems for network attached processing, namely, programs for delivering processing and memory resources as well as increased compute capacity; Computer software that delivers CPU and memory resources as a shared network service
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; [ computer software for use with computer operating systems for network attached processing; ] Computer hardware [ and software ] that delivers CPU and memory resources as a shared network service; microprocessors
