The present application discloses a method for making an image sensor, wherein an additional supplementary oxide layer is added in a PD area of a pixel cell before the formation of a gate oxide layer, a layer of a first photoresist is added and photoetching is used to define a PD area of a non-pixel cell, a supplementary oxide layer outside the PD area is removed by etching, retaining the supplementary oxide layer in the PD area. Thus, a relatively thick oxide layer can be formed in the PD area before polysilicon generation, blanket etching can be performed on the surface of the PD area during subsequent DG-ET (double-gate etching) and poly etch, and surface damage can be avoided during etching, reducing the plasma interference, and ultimately, the pixel dark current to improve pixel performance.
This application discloses a unit structure of a silicon photomultiplier tube, including a first conductive type heavily doped first electrode region located on a first side of the shallow trench isolation, a second conductive type heavily doped second electrode region located on a second side, and a quenching resistor located on a top surface of the shallow trench isolation. A photosensitive layer is formed in the silicon substrate at bottoms of the first electrode region, the shallow trench isolation and the second electrode region. The first electrode region, the photosensitive layer and the second electrode region form a Geiger mode avalanche photodiode. A first end of the quenching resistor is connected to the first electrode region through a first metal interconnect structure. A second end of the quenching resistor is connected to a first electrode. The second electrode region is connected to a second electrode.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
This application discloses a non-volatile memory. A device unit structure includes a vertical channel region and a gate structure. The gate structure covers one side surface of the vertical channel region. The gate structure includes a selection gate and a storage gate. The selection gate and the vertical channel region are spaced apart by a first gate dielectric layer. The selection gate and a semiconductor substrate are spaced apart by a first dielectric layer. The storage gate is located at a top of the selection gate, and the storage gate and the selection gate are spaced apart by a second dielectric layer. The storage gate and the vertical channel region are spaced apart by a second gate storage dielectric layer. A surface of the vertical channel region covered by the gate structure is used for forming a vertical channel. A second vertical channel part is controlled by the storage gate.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
This application discloses a nanoscale failure analysis method, including step 1: placing a first sample to be analyzed on a sample stage of an FIB machine, and performing cutting on a selected area of the first sample by using an ion beam in the FIB machine to form a first cross section and expose a metal pattern on the first cross section; step 2: depositing a protective layer on the first cross section by using an electron beam of the FIB machine; step 3: transferring the first sample to a nano prober, the protective layer being used for protecting the metal pattern and preventing metal diffusion in a transfer process; step 4: performing surface micro treatment on the first sample by using an ion source in the nano prober to remove the protective layer; step 5: performing probing on the metal pattern and implementing electrical testing through the nano prober.
H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
5.
Method for Monitoring Ghost Image of Illumination Unit of Lithography Machine
This application discloses a method for monitoring a ghost image of a illumination unit of a lithography machine, which includes step 1: setting a lens area, a peripheral area, and a central area on a moving plane of a measurement platform; light leakage in the peripheral area causing a ghost image; step 2: turning on the illumination unit, moving the measurement platform to move the light intensity uniformity sensor to the central area, measuring first light intensity in the central area, and obtaining a reference value from the first light intensity; step 3: moving the light intensity uniformity sensor to a selected position in the peripheral area and measuring second light intensity at the selected position; and step 4: dividing the second light intensity by the reference value to obtain a first ratio as a scattered light monitoring value for the ghost image.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
The present application provides an injector mounting apparatus of a furnace, wherein a first injector in the furnace has a main injector pipe. The injector mounting apparatus includes a first mounting component. The first mounting component has an injector mounting hole for the first injector to pass through and be disposed therein, a first edge on a side of the main injector pipe close to the inner side surface of the process tube abuts on a second edge on a side of the injector mounting hole close to the inner side surface of the process tube, and there is a first spacing between the second edge and an outer side face of the first mounting component. A flange is disposed at the bottom of the process tube, and the first mounting component is mounted on the flange by means of a first fixing member.
F27B 5/16 - Arrangements of air or gas supply devices
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
7.
FIXING APPARATUS FOR FURNACE WIRE OF FURNACE BODY HEATER
The present application provides a fixing apparatus for a furnace wire of a furnace body heater, which is formed by assembling a plurality of fixing units. A structure of each of the fixing units includes: a front end structure and a tail end structure connected together. The front end structure is provided with a first recess and a second recess. The tail end structure is provided with a third recess and a fourth protrusion block. Two adjacent ones of the fixing units form a first splice structure, in the first splice structure, the fourth protrusion block of the fixing unit at the top is snap fitted in the third recess of the fixing unit at the bottom to achieve fixation. An opening of a first recess of the fixing unit at the bottom and an opening of a second recess of the fixing unit at the top are butt-jointed together.
This application discloses a system for turning off power consumption of an auxiliary startup circuit. An oscillator generates a switch control signal based on a reference current output by a circuit to be started up to generate a working clock of a switch control signal generation circuit after the circuit to be started up works normally. After fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control power consumption of normally open current of the auxiliary startup circuit to be turned off. At the same time, the switch control signal generation circuit stops counting the clock. This application can assist the circuit to be started up having a “degeneracy” bias point to power on normally, and can also turn off the power consumption of the auxiliary startup circuit after the circuit to be started up is powered on.
This application discloses a method for analyzing a wafer angle in semiconductor integrated circuit manufacturing, including step 1: collecting machine angle data; step 2: predicting and forming an angle trajectory map of each analyzed wafer in a process according to the machine angle data; step 3: performing first grouping on defective wafers in an analyzed lot according to defect types; step 4: selecting one first group as a selected group, and performing second grouping on each defective wafer in the selected group according to defect directions; and step 5: calculating a direction difference between defect directions of second groups, and determining a site and a machine where a defect occurs in combination with the direction difference and an angle difference in the angle trajectory map of each detective wafer in the selected group. This application further discloses a system for analyzing a wafer angle in semiconductor integrated circuit manufacturing.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.
The present application discloses a CMOS image sensor. A pixel cell circuit comprises a photodiode and a CMOS pixel readout circuit. The pixel cell circuit is formed on an SOI substrate, and the photodiode is formed on a bottom semiconductor substrate. The CMOS pixel readout circuit is formed on a top semiconductor substrate. A photo-induced carrier of the photodiode is connected to the CMOS pixel readout circuit by means of an electrotransfer structure passing through a dielectric buried layer. The present application also discloses a method for manufacturing a CMOS image sensor. The present application can increase a pixel cell density without reducing a photodiode area, thus achieving an ultra-high CMOS image sensor density and improving the device quality.
A method for manufacturing a SONOS memory discloses forming first a thin oxide layer as a sidewall protection layer and a blocking layer. This layer prevents the high dielectric-constant layer at the bottom of the stacked gate structure from being exposed on the surface. An lightly doped drain (LDD) implantation area is defined by a lateral thickness of a thin oxide layer, so that the channel width may be controlled by controlling the thickness of the thin oxide layer. Thus, the width of a current channel at the bottom of a gate is reduced under the same ion implantation condition into the active area, thereby improving a current capacity of the SONOS memory without adding any mask or photolithography step, and thus bring no additional patterning costs or active area ion implantation costs.
The present application discloses a method for analyzing a layout pattern density, comprising: step 1, providing layouts of a chip, and merging the layouts to form a wafer level layout, wherein the wafer level layout presents a first circle in a top view, and the layout comprises a plurality of mask layers; step 2, segmenting the first circle to form a plurality of check windows; step 3, searching for the mask layer containing the patterns having a height morphology, and combining the found mask layers into a pattern layer combination; step 4, sequentially calculating a pattern density of the pattern layer combination in each check window; and step 5, recording the pattern density in each check window on a third circle to form a wafer level pattern density distribution diagram. The present application can predict a height morphology of a top surface of a wafer related to a layout.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.
The present application discloses an optical waveguide structure, comprising: a lower cladding layer composed of a first dielectric layer; and a core layer which is composed of a patterned structure of a second material layer and presents a strip structure. A first trench is formed in a top region of the core layer. An upper cladding layer fully fills the first trench, extends to a top surface of the core layer outside the first trench, and coats side faces of the core layer in a width direction of the core layer. A refractive index of the second material layer is greater than a refractive index of the first dielectric layer, and the refractive index of the second material layer is greater than a refractive index of the upper cladding layer. The present application also provides a method for manufacturing an optical waveguide structure.
The present application discloses a double-layer stacked CMOS image sensor, photo diode and transfer gate transistor of a pixel cell are formed on the first substrate sequentially along a longitudinal direction, and the other pixel transistors of the pixel cell are formed on the second substrate. The first substrate and the second substrate are packaged separately, and the second substrate is stacked on the top side of the first substrate instead of being in juxtaposition. Since the photo diode and the pixel transistors other than the transfer gate transistor of the pixel cell are located on two separate substrates respectively, the area of a photo diode region may be increased significantly, thereby greatly increasing full well capacitance of the image sensor and increasing a dynamic range, and reduce a dark current and image noise significantly, thereby improving the dark line noise and full well capacitance simultaneously.
The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
18.
Method for automatically detecting wafer backside brightfield image anomaly
The present application provides a method for automatically detecting a wafer backside brightfield image anomaly, at least comprising: processing wafer backside brightfield images by means of histogram equalization, so as to obtain processed images; compiling statistics for a gray histogram of the processed images; calculating the number of abnormal pixels in each of the images; and providing a threshold, and highlighting the image with a score less than the threshold. In the present application, the wafer backside brightfield images are analyzed by means of image preprocessing and a specific calculation method, so as to quickly and automatically detect an abnormal wafer backside image.
G06V 10/50 - Extraction of image or video features by performing operations within image blocksExtraction of image or video features by using histograms, e.g. histogram of oriented gradients [HoG]Extraction of image or video features by summing image-intensity valuesProjection analysis
The present application discloses a method for purge clean of a low pressure furnace, comprising: step 1, providing a process chamber of the low pressure furnace in a standby state, wherein an inner wall thin film formed by a furnace deposition process is accumulated on the surface of an inner wall of the process chamber; step 2, performing temperature ramp-up or temperature ramp-down treatment on the process chamber to generate first thermal stress in the inner wall thin film, wherein thin film particles with poor adhesion in the inner wall thin film peels off; step 3, introducing a cleaning gas in a pulse manner to perform cycle purge clean on the process chamber, so as to remove the peeling thin film particles from the process chamber; and step 4, switching a state of the process chamber to the standby state after the cycle purge clean ends.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
B08B 5/00 - Cleaning by methods involving the use of air flow or gas flow
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
B08B 7/04 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by a combination of operations
The present application discloses a method for improving stability of etching rate of an etching chamber, which includes the following steps: step 1: providing a first focusing ring with a one-piece structure; step 2: performing a fatigue damage test to the first focusing ring; step 3: disposing a second focusing ring with a two-piece structure according to the damage range, the second focusing ring consisting of a first concentration ring and a second outer protection ring, the material of the first concentration ring being the same as the material of the first focusing ring, the diameter of the outer edge of the first concentration ring extending to a position where the damage range is at least completely covered; step 4: performing an etching process by adopting the etching chamber with the second focusing ring.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
21.
Method for locating open circuit failure point of test structure
The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.
The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
23.
Preventive maintenance method for chamber of metal etching machine
The present application discloses a preventive maintenance method for a chamber of a metal etching machine. An optimized burning cleaning recipe is added before the chamber is opened, and metal substances remaining on the surface of an electrostatic chuck are removed by adopting a cleaning/pumping down multi-step alternate method. Before the chamber is opened for preventive maintenance, the phenomenon of metal particles remaining on the surface of the electrostatic chuck can be significantly improved, thus solving the downtime problem caused by abnormal backside helium and ensuring the stability of mass production.
B08B 5/00 - Cleaning by methods involving the use of air flow or gas flow
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
24.
ReRAM Device and Method for Manufacturing the Same
The present application discloses a ReRAM device, the bottom surface of a first resistance switching layer is connected with a bottom electrode, and a first groove is formed in the center of the top surface of the first resistance switching layer. A second resistance switching layer is formed on the first resistance switching layer, the center of the bottom surface of the second resistance switching layer is filled downwards into the first groove, and the top surface of the second resistance switching layer is connected with a top electrode. The material of the second resistance switching layer is more conductive than the material of the first resistance switching layer. The present application can maintain the stability of the central conductive filament in the low resistance state. The present application further discloses a method for manufacturing the ReRAM device.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
The application discloses a method for manufacturing a photomask, firstly determining a main pattern area of a photomask substrate and an auxiliary pattern area around the main pattern area; performing optical intensity simulation on patterns of the main pattern area and the auxiliary pattern area by means of an optical proximity correction (OPC) model, so as to ensure that the pattern of the auxiliary pattern area is not exposed on a photoresist on a wafer and the pattern of the main pattern area is exposed on the photoresist on the wafer during the integrated circuit manufacturing process; screening out a set of auxiliary pattern parameters; and forming the pattern of the main pattern area on the photomask substrate by means of a photomask manufacturing etching process, and forming the pattern of the auxiliary pattern area on the photomask substrate according to the auxiliary pattern parameters. The application also discloses a photomask.
The present application discloses an electro-static discharge protection structure, which includes an N-well and a P-well formed in a substrate. Upper parts and middle parts of the N-well and the P-well are isolated by shallow trench isolation (STI), and lower parts adjoin. The upper part of the N-well to form an N-well P-type heavily doped region adjacent to the STI. The upper part of the N-well to form an N-well N-type heavily doped region far away from the STI. The upper part of the P-well forms a P-well P-type heavily doped region adjacent to the STI. The N-well P-type heavily doped region and the N-well N-type heavily doped region are short-circuited to form an anode of the electro-static discharge protection structure. The P-well P-type heavily doped region is used as a cathode of the electro-static discharge protection structure. The present application can realize no snapback effect.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
27.
Method for measuring stitching overlay accuracy of image sensor stitching manufacturing
The present application discloses a method for measuring stitching overlay accuracy of image sensor stitching manufacturing, forming an A-type overlay pattern mark and a corresponding B-type overlay pattern mark on the edge of each rectangular pixel area to be stitched; after the A-type overlay pattern mark and the B-type overlay pattern mark are stitched and exposed, performing metrology by means of a scanning electron microscope to obtain dimension features; and according to the dimension features of the A-type overlay pattern mark and the B-type overlay pattern mark stitched together and exposed and measured by the scanning electron microscope, determining stitching overlay accuracy of two adjacent rectangular pixel areas. The present application can achieve direct metrology on the overlay pattern mark on the stitched pixel area of a product, facilitating timely and accurate monitoring on the stitching overlay accuracy of image sensor stitching manufacturing.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
28.
Global shutter CMOS image sensor and method for making the same
The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.
The present application discloses a method for preparing a pixel cell of a CMOS image sensor. Process optimization and adjustment for multiple times of ion implantation in a pixel area of the CMOS image sensor are carried out. That is, photodiode N-type ion implantation is performed before formation of a polysilicon gate of each MOS transistor of a CMOS pixel readout circuit, a photoresist open area is enlarged by means of a photoresist dry etching descum process such that an N-type ion implantation area is enlarged, and second photodiode N-type ion implantation is performed on the basis of the photoresist dry etching descum process, so as to achieve two times of photodiode N-type ion implantation using the same mask, with different depths and different pattern sizes, thereby forming an N-type area of the photodiode that tapers to the bottom, saving a mask layer, and reducing photolithography steps.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
30.
Stack capacitor, a flash memory device and a manufacturing method thereof
The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H10B 41/44 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H10B 41/46 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
31.
Semiconductor structure and the manufacturing method thereof
The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.
The disclosure provides a method for manufacturing shallow trench isolations, providing a substrate comprising a storage cell area and a peripheral area of a storage device; etching the upper part of the substrate of the storage cell area using a first etching process to form a first shallow trench, and filling the first shallow trench with silicon oxide using a first deposition process; and etching the upper part of the substrate of the peripheral area using a second etching process to form a second shallow trench, and filling the second shallow trench with silicon oxide using a second deposition process; wherein the depth and characteristic dimension of the first shallow trench are smaller than the depth and characteristic dimension of the second shallow trench. The disclosure can avoid the silicon dislocation defect of the peripheral area and ensure the device shape and characteristic dimension of the storage cell area.
The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas.
Provided in the disclosure is a photomask for detecting flare degree of lens of exposure machine. The photomask includes a central exposure area and a peripheral area, exposure light of the exposure machine passing through the lens and then penetrating the central exposure area to expose photoresist on a wafer, wherein the entire central exposure area is provided with a shading layer to prevent the exposure light from penetrating; and the peripheral area is provided with a plurality of light-transmitting stripes, and stray light formed after the exposure light passes through the lens penetrates the plurality of light-transmitting stripes to expose the photoresist. Further provided in the disclosure is a method for detecting flare degree of lens of exposure machine by using the photomask. According to the disclosure, a lens flare problem of an exposure machine can be found and solved in time.
The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.
H01L 27/11531 - Simultaneous manufacturing of periphery and memory cells
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
36.
Method for forming doped epitaxial layer of contact image sensor
The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.
The disclosure discloses a layout structure of an eFuse unit, comprising pad, link, and shield, wherein: a pad is respectively disposed on both ends of the link in a length direction; the shield and the link are at the same metal layer; the shield comprises a plurality of independent metal wires; the plurality of independent metal wires are arranged on both sides of the link; the length of each independent metal wire is greater than the width thereof; and a length direction of each independent metal wire is perpendicular to the length direction of the link. The disclosure not only forms a barrier protection layer for preventing burst metal spraying from affecting other circuits, but also can prevent spayed metal from reflecting back and connecting to a broken link, so as to improve the programming reliability of the eFuse unit.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.
The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
42.
Method for manufacturing deep trench isolation grid structure
The present disclosure provides a CMOS image sensor and a pixel structure thereof, and a method for manufacturing a deep trench isolation grid structure in the pixel structure. The method for manufacturing the deep trench isolation grid structure comprises: depositing a first isolation layer and a second isolation layer sequentially on the side walls and bottom surface of each deep trench; and depositing a third isolation layer that fills each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches constitute the grid. The deep trench isolation grid structure formed by the method can effectively reduce electrical crosstalk between adjacent grid lines, thereby improving the device performance of the CMOS image sensor which is built upon the deep trench isolation grid structure and the pixel structure thereof.
The invention provides a method for manufacturing a SONOS memory, including: providing a substrate, wherein a selective transistor gate and a storage transistor gate are formed on the substrate of a storage area; forming a silicon epitaxial layer on the upper surface of the substrate of the storage area on both sides of the selective transistor gate and on both sides of the storage transistor gate, wherein the silicon epitaxial layer is used to separately form a source and a drain of a selective transistor and a storage transistor; and forming a metal salicide layer on an upper portion of the silicon epitaxial layer. The present application further provides the SONOS memory. The present application can improve the yield of the formed SONOS memory and effectively improve the device performance of the formed SONOS memory, and the device performance of the formed SONOS memory can be effectively improved.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present invention includes a voltage controlled oscillator circuit and a phase-locked loop device. The voltage controlled oscillator circuit comprises: a voltage-to-current conversion module, used for converting a control voltage of a voltage controlled oscillator into a control current as a linear function of the control voltage; and a current controlled oscillation module, used for outputting a low-amplitude oscillation signal based on the control current, so as to reduce power consumption. Further provided in the present invention is a phase-locked loop device comprising the voltage controlled oscillator circuit. According to the voltage controlled oscillator circuit, design parameters of low power consumption and high linearity may be achieved, thereby making a gain Kvco of the voltage controlled oscillator relatively stable, and it may be ensured that the voltage controlled oscillator and the phase-locked loop comprising the same have relatively excellent device performance.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.
The disclosure discloses a reading reference current automatic regulation circuit of a non-volatile memory. A reading check control module initiates a reading operation, a row reading operation is performed by controlling the memory to switch gate voltage of memory cells to bias gate voltage row by row, a comparison result between a memory cell readout value and an expected value is received, the reading check control module determines whether a reading check is passed according to the comparison result, a reading reference current control module adjusts the digital regulation signal according to whether the reading check is passed, and thus the magnitude of the reading reference current is adjusted through the digital-to-analog conversion module. The disclosure can adaptively regulate the internal reading reference current according to the process threshold voltage deviation in the test and meet the requirements on the function and reliability of the non-volatile memory.
The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
The present application discloses a programmable memory, wherein an anti-fuse unit thereof is formed by adding an efuse between an anti-fuse programming transistor and a control transistor of a conventional anti-fuse unit such that the anti-fuse unit can be programmed twice, that is, normal programming can be implemented by breaking down a gate-source insulation layer of the anti-fuse programming transistor, and correction programming can be further implemented by fusing the efuse such that correction programming can be performed on a normal programming result, thereby changing a logical state of the normally programmed anti-fuse unit. For the programmable memory, a reprogramming method can be directly used to correct an error bit, thereby simplifying circuit and layout designs, resulting in a smaller layout area and higher reliability, increasing the applicability and flexibility, while retaining original features of reliable and safe data of the anti-fuse unit.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.
H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/8228 - Complementary devices, e.g. complementary transistors
51.
Silicon controlled rectifier and method for making the same
The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: a P-type substrate; an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and the N-type well 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode is in mirror symmetry with a second electrode with respect to the P-type heavily doped region 24, and shallow trench isolations are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and the N-type heavily doped region 26.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/8228 - Complementary devices, e.g. complementary transistors
52.
Silicon controlled rectifier and method for making the same
The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.
A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.
G11C 17/00 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
54.
Stack capacitor, a flash memory device and a manufacturing method thereof
The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 27/11536 - Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/11539 - Simultaneous manufacturing of periphery and memory cells including only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
The present invention provides a 1.5T SONOS memory structure and a manufacturing method, comprises a P-well and a storage well on its side, gates of a select transistor and a storage transistor; the height of the select transistor gate is less than the height of the storage transistor gate, an stack layer is between the gats of the select transistor and the storage transistor which height is same as the storage transistor gate; the top of the select transistor gate has a first sidewall; the sidewall of the select transistor gate has a second sidewall. The present invention strengthens the isolation between the gates of the select transistor and the storage transistor, reduces the risk of current leakage, enables the metal silicide to also grow on the gate of the select transistor, reduces the resistance of the select transistor and improves the performance of the device.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
56.
50%-duty-cycle consecutive integer frequency divider and phase-locked loop circuit
Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.
H03L 7/183 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
H03K 23/70 - Pulse counters comprising counting chainsFrequency dividers comprising counting chains with a base or radix other than a power of two with a base which is an odd number
5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A flash device endurance test method is provided. A flash device to be tested, which has a plurality of memory cells, includes multiple ports with the same and different test conditions. The method includes connecting the ports of the same test condition to the same pulse generation unit, and connecting the ports of different test conditions to different pulse generation units; generating by all of the pulse generation units, synchronous pulse voltage signals of N cycles, wherein one time of erasing-writing of the flash device is considered to be one of the cycles; and testing threshold voltages of erasing and writing states in each cycle.
An oscillator comprising an RC oscillator and a bandgap reference source, wherein the bandgap reference source provides a reference current for the RC oscillator, and a temperature coefficient of the reference current is adjustable. Since the oscillation frequency of the RC oscillator has less dependency on a power supply, a clock source having a relatively precise frequency thus can be obtained; and based on the RC oscillator, the bandgap reference source having a temperature compensation function is added, the reference current generated by the bandgap reference source with an adjustable temperature coefficient is used for temperature coefficient compensation to the inherent temperature coefficient of the oscillation frequency of the RC oscillator, thereby reducing the effect of the temperature on the oscillator, so that the output frequency of the oscillator does not change with the temperature as far as possible, which improves the oscillation frequency precision of the oscillator.
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
60.
Classification method for automatically identifying wafer spatial pattern distribution
The present invention provides a classification method for automatically identifying wafer spatial pattern distribution, comprising the following steps: performing statistical analysis to distribution of defects on a wafer, the defects being divided into random defects, repeated defects and cluster defects; performing denoising and signal enhancement to the cluster defects; performing feature extraction to the cluster defects after denoising and signal enhancement; and performing wafer spatial pattern distribution classification to the cluster defects after feature extraction. By performing statistical analysis and neural network training to a great amount of wafer defect distribution, the spatial patterns in defect distribution can be automatically identified, the automatic classification of wafer spatial patterns can be realized, the workload of engineers is effectively reduced and the tracing of the root cause of such spatial pattern is facilitated.
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G06K 9/62 - Methods or arrangements for recognition using electronic means
G06N 3/04 - Architecture, e.g. interconnection topology
G01B 21/20 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring contours or curvatures, e.g. determining profile
The present invention provides a method for detecting an ultra-small defect on a wafer surface, film layer having ultra-small defect that causes abnormalities on the surface of the film layer; form a photoresist pattern with a pattern defect; etching the film layer according to the photoresist pattern to form a film layer pattern with an enlarged defect; and scanning the film layer pattern by using a defect scanner to capture the enlarged defect. In this method, enlarging the size of the ultra-fine particle defect through the exposure defocusing principle; or by adding the photomask consisting of the repeating units, using the repetition pattern as the exposure pattern and combing with the repeating cell to cell comparison method, the capture ability of the detection machine is further improved. Therefore, it can be detected by amplifying the defects of ultrafine particles which cannot be detected by conventional methods.
The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.
The present invention discloses a power supply powering-on structure, which comprises an LDO module, a bandgap reference module, a voltage detection module, a bias module and a switch module; the working voltage of the LDO module, the voltage detection module and the bias module adopts external power supply voltage; the working voltage of the bandgap reference module adopts LDO output voltage; the switch module provides switching connection between the output of the bias module and the output of the bandgap reference module for a reference voltage input end and a bias current input end of the LDO module. The present invention can adopt internal power supply voltage to supply power to the bandgap reference module and can also solve the problem that the internal power supply voltage restricts the powering-on and starting of the bandgap reference module.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
64.
Flash with shallow trench in channel region and method for manufacturing the same
The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
The invention discloses a global shutter CMOS image sensor. Each pixel unit of the global shutter CMOS image sensor includes a photo diode, a storage region and a first reset region, wherein the photo diode includes a first photosensitive doped region; a gate structure of a first transfer transistor is formed between the storage region and the first photosensitive doped region; a gate structure of a global shutter transistor is formed between the first reset region and the first photosensitive doped region; and inhomogeneous potentials are formed in the first photosensitive doped region through a doping structure. According to the invention, photo-induced carriers in the PDs of the pixel units, especially photo-induced carriers in the PDs of large pixel units, can be simultaneously and completely transferred to the storage region and the first reset region, and the overall performance of the device is improved.
The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The invention also provides a manufacturing method for manufacturing the above-mentioned split gate flash memory cell, and the manufacturing method provided by the invention can be compatible with the existing manufacturing process of the split gate flash memory cell without increasing the process cost and the process complexity. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
67.
LDO circuit device and overcurrent protection circuit thereof
Embodiments described herein relate to an LDO circuit device and overcurrent protection circuit of an LDO circuit. An overcurrent protection circuit is added to an LDO circuit to process an output current signal of the LDO circuit. When the output current signal of the LDO circuit increases, a voltage of a gate drive signal of a power switch in the LDO circuit is increased through adjustment performed by the overcurrent protection circuit, thereby declining the current capability of the power switch in the LDO circuit and restricting an output current thereof from continuing to increase. After feedback regulation, the output current of the LDO finally reaches to a stable value.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
68.
Voltage-controlled oscillator circuit and phase-locked loop circuit
The present invention discloses a voltage-controlled oscillator (VCO) circuit, When the VCO circuit works, the DC control voltage is divided into two portions, both of which determine an oscillation frequency of the VCO circuit. One portion of the DC control voltage controls a current provided by the fifth PMOS transistor, and the other portion of the DC control voltage controls the current of the forth PMOS transistor after passing through the third NMOS transistor, thereby controlling oscillation of the VCO circuit. The former plays a leading role when the DC control voltage is relatively low, and the latter plays a leading role when the DC control voltage is relatively high, thereby effectively increasing the use range of the DC control voltage while the high frequency noise interference on the DC control voltage is suppressed. The present invention further discloses a phase-locked loop circuit.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
69.
Semiconductor structure and method of manufacturing the same
The present invention provides a semiconductor structure and method of manufacturing the same. The semiconductor structure includes a substrate and a gate formed on the substrate. The above manufacturing method is used to form a gate on the substrate. The above manufacturing method specifically includes: providing a substrate; forming a trench in an upper portion of the substrate; depositing a gate layer on the substrate, the gate layer including two step portions extending from the outside of the trench to the inside of the trench; etching the gate layer from two ends of the trench along the two step portions toward the center of the trench to form the gate in the trench, wherein the width of the gate is smaller than the width of the trench. The manufacturing method of the present invention can easily and efficiently form a gate having a small critical dimension and precisely controllable on a semiconductor substrate, thereby meeting increasingly stringent gate size requirements.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
70.
Electrostatic protection circuit and a semiconductor structure
The present disclosure relates to the field of integrated circuits protection, and specifically discloses an electrostatic protection circuit and a semiconductor structure. The electrostatic protection circuit is disposed between a first port and a second port that require electrostatic protection, comprising at least one interdigital loop and a control circuit electrically connected to the interdigital loop. The interdigital loop comprises an electrostatic protection transistor having a drain electrically connected to the first port and a source electrically connected to the second port. The control circuit comprises a first transistor and a second transistor. The drain of the first transistor and the gate of the second transistor are electrically connected to the first port. The drain of the second transistor and the gate of the first transistor are electrically connected to the second port.
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
71.
Method of ion implantation and an apparatus for the same
The present disclosure relates to semiconductor devices, specifically discloses a method and an apparatus for ion implantation. The above method may comprise: generating a particle beam that satisfies the implantation energy, wherein the particle beam comprises the target ion and the impurity particle; applying a first deflection magnetic field to the particle beam to deflect the particle beam, and applying a second deflection magnetic field to the deflected particle beam to cause a second deflection of the particle beam to separate the target ion from the impurity particle; and implanting the separated target ion into the semiconductor wafer.
H01J 37/147 - Arrangements for directing or deflecting the discharge along a desired path
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
The present disclosure provides a pattern density analysis method for analyzing a local pattern density of a layout, the method comprising: obtaining a pattern attribute of each layout pattern located on a layout region to be analyzed; setting, for each layout pattern, a relevant window for the layout pattern based on the corresponding pattern attribute; calculating the pattern density of each relevant window; and selecting the maximum value of the pattern densities of the relevant windows as the maximum local pattern density of the layout, and selecting the minimum value of the pattern densities of the relevant windows as the minimum local pattern density of the layout.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
G03F 1/68 - Preparation processes not covered by groups
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
The present invention discloses a design method of a sub resolution assist feature, which comprises the following steps of: S01: forming a sub resolution assist feature in the mask plate, the upper surface of the sub resolution assist feature is aligned with the upper surface of the mask plate; S02: forming a process pattern on one side, which contains the sub resolution assist feature, of the mask plate, the position of the process pattern is not superposed with the sub resolution assist feature in a vertical direction.
The present disclosure provides a pixel structure for a CMOS image sensor and a manufacturing method therefor, the pixel structure comprising a photo diode and a source follow transistor, and an isolation strip is provided between the photo diode and the source follow transistor, and a contact hole is provided in a drain terminal of the source follow transistor, with the width of a part, corresponding to the contact hole portion, of a drain terminal active area of the source follow transistor being smaller than the width of the rest of the drain terminal active area, so that the width of a part, corresponding to the contact hole portion, of the isolation strip is greater than the width of a part, corresponding to the rest of the drain terminal active area, of the isolation strip.
The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
The present disclosure provides a semiconductor device and a manufacturing method therefor. The manufacturing method for a semiconductor device is provided for forming through-holes in a semiconductor device, comprising: forming a plurality of shallow trench isolations in portions of a substrate corresponding to memory cell regions; forming a plurality of gates on surfaces of the portions of the substrate; forming spacers on side walls at both sides of the gates extending in the first direction; depositing a sacrificial layer on the memory cell region; removing portions of the sacrificial layer corresponding to the shallow trench isolations at memory cell drain, and depositing an isolation dielectric on the shallow trench isolations at the memory cell drain to form isolation strips; and removing the remaining sacrificial layer to form bottom through-holes in spaces formed after removing the remaining sacrificial layer.
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
77.
Method of manufacturing a bipolar transistor with trench structure
The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
78.
Methods and systems for reducing dislocation defects in high concentration epitaxy processes
Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
79.
Transistor with SONOS structure having barrier wall over adjacent portions of the select transistor well and memory transistor well
The present disclosure provides a manufacturing method for a transistor with an SONOS structure, including providing a semiconductor substrate, wherein the semiconductor substrate includes a select transistor well and a memory transistor well; depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well, depositing a barrier wall over adjacent portions of the select transistor well and the memory transistor well, depositing polycrystalline silicon covering the oxide layer, the ONO memory layer, and the barrier wall, and etching the polycrystalline silicon, to retain the polycrystalline silicon deposited on both sides of the barrier wall so as to form a select gate and a memory gate, and removing the oxide layer and the ONO layer on a surface of the semiconductor substrate other than the select gate, the barrier wall, and the memory gate.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present invention discloses a design method of a sub resolution assist feature, which comprises the following steps of: S01: forming a sub resolution assist feature in the mask plate, the upper surface of the sub resolution assist feature is aligned with the upper surface of the mask plate; S02: forming a process pattern on one side, which contains the sub resolution assist feature, of the mask plate, the position of the process pattern is not superposed with the sub resolution assist feature in a vertical direction.
A hotspot correction method is provided. The layout patterns in the hotspot regions are accurately corrected by using an ILT method. Then the layout patterns in the extension regions are corrected by using an OPC method. As a result, the layout patterns in the hotspot regions can be accurately corrected while pattern distortion of the extension regions generated due to the regional ILT correction can be prevented. Moreover, high demanding of calculation capability and long calculation time of global ILT correction can be avoided.
The present invention discloses an OPC method for a pattern corner, comprising the following steps of: S01: providing a photomask which has an original layout containing target patterns, wherein the target patterns have at least one convex corner at a vertex of two first adjacent sides with an angle of 90-degree therebetween and at least one concave corner at a vertex of two second adjacent sides with an angle of 270-degree; S02: modifying the original layout to obtain a modified layout by adding at least one first rectangular correction pattern from outside of the convex corner and/or removing at least one second rectangular correction pattern from inside of the concave corner; S03: performing a model-based OPC correction to the modified layout to obtain a corrected photomask.
G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A manufacturing method of a Flash wafer, comprises: fabricating a Flash wafer containing a cell area, a logical area and a capacitance area; adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area; sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area; adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area; depositing an interlayer dielectric layer on the surface of the Flash wafer; removing the rest part in the logical area by protecting the cell area and the capacitance area with a mask.
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
The present invention discloses an OPC method for a shallow ion implanting layer, comprising the following steps of: selecting a valid device region in an implanting active region in a shallow ion implanting original layout; selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region; extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; combining a gap portion which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G and completely fallen in the STI region, with the poly-silicon contacting regions and non poly-silicon contacting regions after extending, to form a correction target layer; performing a model-based OPC routine on the correction target layer, to obtain a mask layer.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 27/11 - Static random access memory structures
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
88.
Method for quickly establishing lithography process condition by a pre-compensation value
The present invention discloses a method for quickly establishing lithography process condition by a pre-compensation value, comprising: firstly determining a reference process condition of masks of which parameters are same, and then determining an optimum process condition of the first mask; thereafter, calculating a ratio of the optimum process condition of the first mask deviating from the reference process condition, wherein if the ratio is equal to or larger than a set threshold, the first mask is inspected, and if the ratio is less than the set threshold, an optimum process condition of the second mask is determined according to the ratio and the reference process condition of the second mask; and by analogy, determining optimum process conditions of the rest masks. The method of the present invention can quickly establish a lithograph process condition, reduce the trial production time for determining the optimum defocus amount and exposure amount.
A method for MOM capacitance value control is disclosed. The method comprises: S01: setting a target thicknesses for each metal layers; S02: after forming a current metal layer, measuring a thickness of the current metal layer; when the thickness of the current metal layer is equal to or less than a threshold value, then turning to step S03; S03: calculating multiple capacitance variations related to the current metal layer according to the thickness of the current metal layer; wherein each of the capacitance variation related to the current metal layer is between an actual capacitance value of a MOM capacitor combination associated with the current metal layer and a target capacitance value of the same MOM capacitor combination; S04: calculating updated target thicknesses for all subsequent metal layers according to the capacitance variations related to the current metal layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
G01R 31/26 - Testing of individual semiconductor devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
90.
Optimization method and system for overlay error compensation
An optimization method for overlay error compensation is disclosed. The method comprises setting process parameters for each semiconductor layer of a semiconductor device corresponding to a run path formed by different lithographic apparatus which sequentially process target semiconductor layers from a first target layer to a latest target layer; measuring overlay errors between an actual and a theoretical exposed patterns of the first semiconductor layer; selecting a group of process parameters corresponding to the run path from the first target layer to the latest target layer aligned by the current semiconductor layer; after exposing the current semiconductor layer using the selected process parameters, measuring overlay errors between the current semiconductor layer and its target layer; and correcting the selected process parameters according to the overlay errors between the current semiconductor layer and its target layer, and the overlay errors between the actual and theoretical exposed patterns of the first semiconductor layer.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/66 - Testing or measuring during manufacture or treatment
91.
Structure and generation method of clock distribution network
The present invention provides a structure of a clock distribution network and generation method thereof. The clock distribution network is distributed in multiple local circuit modules. The clock distribution network comprises a clock tree structure and clock mesh structures, wherein the clock tree structure is distributed at least between or among the multiple local circuit modules and has a root node which is a clock access point of the clock distribution network. The clock mesh structures are distributed within at least one local circuit module at least according to a proportion of clock nodes in the local circuit module, a proportion of sequential circuits connected by clock in the local circuit module, a ratio of a total length of clock routing wirings in the local circuit module to a perimeter of the local circuit module, and a proportion of timing violation paths in the local circuit module.
Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
An inrush current control device for an IC chip having multiple functional units and M power switches comprises a programmable counter unit, a selector unit and an enable signal driving unit. The programmable counter unit counts a clock signal and sets a predetermined counting value. The selector unit is connected to the programmable counter unit and has N output ports for outputting N enable signals. The enable signal driving unit has N enable driving circuits correspondingly connected to the N output ports of the selector unit, and controlling on/off states of N groups of the M power switches. The programmable counter unit controls the selector unit to output the N enable signals to the N enable signal driving circuits at a predetermined time interval determined by the predetermined counting value to switch on the N power switches groups successively to reduce the transient inrush current.
A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 27/11 - Static random access memory structures
95.
SiGe source/drain structure and preparation method thereof
A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
The invention disclosed a method for forming high aspect ratio patterning structure. Firstly, forming a dielectric film ashing stop layer, a first photoresist layer, a first hard mask layer and a second photoresist layer on a semiconductor substrate in turn. A second hard mask layer having a high etch selectivity ratio with the first photoresist layer is formed on top surface and sidewall of the pattern by utilizing a low temperature chemical vapor deposition process, which can be a protect for the pattern sidewall during the later etching process of the first photoresist layer. So, the cone-shaped or the bowling-shaped photoresist morphology caused by plasma bombardment can be avoided. Therefore, the problems of the insufficient of selectivity ratio, burrs at the edge of the pattern and larger critical dimension can be solved, and the implanted ions can be well distributed according to the design of the device.
A simulation method of CMP process comprises: building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; outputting the final CMP simulation results of the whole layout.
The invention disclosed a method for forming shallow trenches of the dual active regions. Firstly, forming an etch stop layer on a semiconductor substrate; secondly, using a first accurate photomask to expose and develop the semiconductor substrate, until the etch stop layer has been exposed on the top of the first shallow trench regions and the second shallow trench regions; thirdly, etching the etch stop layer entirely in the exposed regions; fourthly, using a second photomask to expose and develop the first shallow trench regions which require a deeper etch depth of the trench than that of the second shallow trench regions; fifthly, etching and forming preliminary entirely depth in the first shallow trench regions, and then removing the second photomask; at last, taking the etch stop layer as a mask, and simultaneously etching the first shallow trench regions and the second shallow trench regions to form the first hallow trenches and the second shallow trenches having different depths. The invention has realized a low-cost photomask application and an optimization of the etching process by optimizing the photomask design.
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
A method of etching a shallow trench is disclosed in the present invention. By removing the photoresist layer immediately at the end point of the hard mask layer etching and further using the improved process conditions etch the top of the substrate at the same time of the hard mask layer over-etching, such as a lower bias power, a higher pressure and a bigger polymer gases flow rate, the present invention has formed a smooth morphology on the top of the shallow trench. Therefore, the sharp corner appeared in the prior art is avoided by changing the start point of the silicon substrate etching, so as to fundamentally eliminate the leakage current caused by the sharp corner.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
patents