Abstract

Provided in the present invention is a magnetic control apparatus, comprising: a coil assembly, the coil assembly being sleeved on the outer side of a monocrystalline silicon device, and the coil assembly being movable in the axial direction of the monocrystalline silicon device. The coil assembly comprises a plurality of main coils, the plurality of main coils being arranged in the circumferential direction of the monocrystalline silicon device, and the component intensity of a magnetic field generated by the main coils in the radial direction of the monocrystalline silicon device being greater than the component intensity of same in the axial direction of the monocrystalline silicon device. By means of the configuration, the component intensity of said magnetic field in the radial direction of the monocrystalline silicon device is greater than the component intensity of same in the axial direction of the monocrystalline silicon device, so that the radial component intensity of the magnetic field is improved, thus effectively suppressing natural convection at the edge of a melt and flexibly controlling the content of impurities such as oxygen and carbon in crystals and radial uniformity. In addition, the coil assembly can move in the axial direction of the monocrystalline silicon device, thereby further improving the practicability and flexibility of the magnetic control apparatus.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• H01F 7/06 - Electromagnets; Actuators including electromagnets

Abstract

A process management method and a related electronic device are provided. According to the method, process data in a volatile memory can be migrated to a non-volatile memory in real time in a running process of a system. When the system is asleep, data in a memory does not need to be packaged and backed up. When the system is woken up or restarted, data does not need to be parsed and reconstructed, to implement quick sleeping and waking up of the system. In addition, even if the system is restarted due to an unexpected power failure, a loss of key data in the memory can be avoided, and a speed of waking up or restarting the system can also be improved.

IPC Classes  ?

• G06F 16/11 - File system administration, e.g. details of archiving or snapshots
• G06F 16/18 - File system types
• G06F 16/188 - Virtual file systems

Abstract

The present application discloses a preparation method for a silicon carbide field effect transistor. The method comprises: providing a first silicon carbide substrate, and epitaxially growing a silicon carbide epitaxial layer on the first silicon carbide substrate; implanting light ions into the silicon carbide epitaxial layer, wherein the light ions form an ion gathering area in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer sequentially forms a silicon carbide thin film layer, the ion gathering area, and a silicon carbide bonding layer; providing a second silicon carbide substrate, and performing conductive treatment on the surface of the second silicon carbide substrate in contact with the silicon carbide bonding layer; performing wafer bonding on the second silicon carbide substrate and the silicon carbide bonding layer; separating the silicon carbide bonding layer from the ion gathering area to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer, and the ion gathering area, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, and recycling the first substrate structure; and on the basis of the second substrate structure, preparing a field effect transistor to obtain a silicon carbide field effect transistor.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

An acoustic resonator and a manufacturing method therefor, and a filter, relating to the technical field of semiconductors. The acoustic resonator comprises a support substrate (1), a piezoelectric thin film layer (2), and an interdigital electrode structure (4) which are sequentially arranged from bottom to top; a polygonal cavity (11) is provided in the support substrate (1); the support substrate (1) is a {111} monocrystalline silicon substrate; the peripheral surface of the polygonal cavity (11) comprises a silicon 110 crystal orientation; the piezoelectric thin film layer (2) is close to the polygonal cavity (11), and the piezoelectric thin film layer (2) is provided with a plurality of etching through holes (3); the plurality of etching through holes (3) are in communication with the polygonal cavity (11).The present invention has excellent electrical and mechanical properties.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
• H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material
• H03H 9/64 - Filters using surface acoustic waves

Abstract

The present application relates to the field of microelectronic devices, and particularly relates to a preparation method and structure for a device. The method comprises: performing ion implantation on a first silicon carbide base, so as to obtain a first structure to be bonded; performing a trimming treatment on a second silicon carbide base; bonding with the second silicon carbide base the first structure to be bonded, so as to obtain a first bonded structure; performing silicon carbide stripping on the basis of the first bonded structure, so as to obtain a silicon carbide epitaxial substrate; preparing a silicon carbide epitaxial layer on the silicon carbide epitaxial substrate, so as to obtain a second structure to be bonded; on the basis of a dielectric layer, bonding with a third silicon carbide base the silicon carbide epitaxial layer of the second structure to be bonded, so as to obtain a second bonded structure; removing the silicon carbide epitaxial substrate from the second bonded structure, so as to obtain a composite base; and preparing a modulation device structure in an area to be etched of the composite substrate, so as to obtain a device. The present application can implement a solution for efficient light modulation of silicon carbide on the basis of a carrier dispersion mechanism.

IPC Classes  ?

• G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction

Abstract

A high-frequency acoustic wave resonator and a manufacturing method therefor, relating to the field of microelectronic devices. The high-frequency acoustic wave resonator comprises a support substrate (1), a piezoelectric film (2) and interdigital transducers (3) which are sequentially stacked from bottom to top. The sound velocity of the support substrate (1) is not less than 5000 m/s; a target mode of the high-frequency acoustic wave resonator is a quasi-bulk wave mode generated by longitudinal electric field excitation; the thickness of each interdigital transducer (3) is inversely proportional to the material density of the interdigital transducer (3); the sound velocity in the target mode is less than the sound velocity of the support substrate (1). On the basis of a heterogeneous integrated substrate, the structure of the acoustic wave resonator is simplified, and the ohmic loss is reduced and the electromechanical coupling coefficient in a high-order mode is improved.

IPC Classes  ?

• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/05 - Holders or supports
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks

Abstract

A manufacturing method for an acoustic wave resonator, and an acoustic wave resonator. The manufacturing method comprises: manufacturing two piezoelectric structures by using the same process, wherein each piezoelectric structure comprises a support substrate (1) and a piezoelectric thin film layer (2) which are sequentially provided from bottom to top, the difference between the thicknesses of the two piezoelectric thin film layers (21, 22) is less than or equal to 20% of the thickness of a preset piezoelectric thin film layer, and the preset piezoelectric thin film layer is the thicker piezoelectric thin film layer among the two piezoelectric thin film layers (21, 22) (S101); bonding the two piezoelectric structures to obtain a bonded structure, wherein the two piezoelectric thin film layers (21, 22) are located in a middle layer region of the bonded structure (S103); removing any one support substrate (1) from the bonded structure (S105); and manufacturing a cavity in the region of the support substrate (1) close to the piezoelectric thin film layer (2) in the retained piezoelectric structure, so that the piezoelectric thin film layer (2) is suspended (S107). Symmetrically complementary piezoelectric thin films in a heterogeneous integrated structure provided by the method can counteract the overall internal stress of the two piezoelectric thin film layers (2), thereby improving the device performance.

IPC Classes  ?

• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/05 - Holders or supports

Abstract

The present invention relates to the technical field of semiconductors, and in particular to a heterogeneous integrated body and a preparation method therefor. The method comprises: providing a first wafer and a second wafer, wherein the first wafer comprises a first face, and the second wafer comprises a second face; activating the first face and the second face, so as to respectively obtain a first activated face and a second activated face; providing vapor or a hydroxyl-containing gaseous substance to the first activated face and the second activated face, so as to form a hydrophilic group on the first activated face, and form a hydrophilic group on the second activated face; and performing dehydration bonding treatment on the first wafer and the second wafer, so as to obtain a heterogeneous integrated body. The present invention can significantly reduce defects of a heterogeneous material interface, such that a high-quality heterogeneous interface is formed, thereby improving the performance of a heterogeneous integrated device made of by the heterogeneous integrated body.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/34 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies not provided for in groups , , and with or without impurities, e.g. doping materials
• H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
• H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation
• H01L 21/423 - Bombardment with radiation with high-energy radiation

Abstract

The present application discloses a preparation method for a heterostructure, comprising: providing a single crystal functional material substrate and a heterogeneous base substrate; performing first ion implantation on the single crystal functional material substrate to form a first defect layer, wherein the single crystal functional material substrate forming the first defect layer is in a warped state; performing warpage control processing on the heterogeneous base substrate to form a warpage control layer, wherein the heterogeneous base substrate forming the warpage control layer is in a warped state; bonding the single crystal functional material substrate forming the first defect layer and the heterogeneous base substrate forming the warpage control layer to obtain a heterogeneous bonded body; and cutting the heterogeneous bonded body to obtain a target heterostructure. According to the preparation method for a heterostructure in the present application, a heterogeneous base substrate and a single crystal functional material substrate are both warped to reduce a bonding gap between the heterogeneous base substrate and the single crystal functional material substrate, thereby enhancing the diffusion capability of a bonding wave, and further enhancing the bonding strength.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

Provided in the present invention are a printed circuit board structure with an embedded chip, and a preparation method therefor. The structure comprises: a conductive substrate; a conductive metal layer and a chip, which are bonded to the same surface of the conductive substrate, wherein the upper surface of the conductive metal layer is flush with the upper surface of the chip; an insulating material layer; a rewiring layer; and a conductive through hole. The conductive metal layer and the chip are bonded to the surface of the conductive substrate, and a deep cavity structure for bonding the chip is not required to be prepared, such that the increased manufacturing cost caused by deep cavity preparation and the difficulty of deep cavity preparation are prevented, and the difficulty of a chip mounting process is reduced; in addition, the conductive metal layer with a surface flush with that of the chip is provided, such that defects such as cavities caused during the lamination of an insulating layer are prevented, and since the surface of the chip is flush with the surface of the conductive metal layer, formed through holes are consistent in depth, such that the difficulty of etching the through holes and the difficulty of subsequent hole filling are effectively reduced; and finally, the conductive metal layer is provided, such that the length of the conductive through hole is effectively reduced, and the length of a circuit is reduced, thereby reducing the parasitic inductance and improving the performance of a device.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface to be subjected to a roughness treatment to form an uneven morphology on the first surface; forming a surface treatment layer, wherein the surface treatment layer has an uneven surface morphology; and forming a polysilicon layer on the surface treatment layer. By the roughness treatment to the first substrate, the first surface and the surface treatment layer both have uneven surface morphology, such that the formed polysilicon layer has stable orientation evolution and grain size, and an increased grain boundary density. Thereby a highly efficient charge trapping polysilicon film can be obtained.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/763 - Polycrystalline semiconductor regions

Abstract

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface, and a pinning layer is formed on the first surface by a deposition process, and homogenizing the pinning layer surface by dry etching to adjust a thickness uniformity of the pinning layer. Accordingly, the thickness uniformity of the obtained polysilicon film is able to reach a good state.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/3065 - Plasma etching; Reactive-ion etching
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The present invention provides a metal carrier-based packaging adapter plate and a manufacturing method therefor. A metal carrier is used as a substrate of the packaging adapter plate, and a metal can be directly etched to form a blind hole, thereby avoiding the formation of the blind hole by means of expensive device costs and material costs and a series of complex processes such as photoresist coating, exposure, development, dry etching and wet photoresist removal, and effectively reducing the process complexity and the manufacturing costs; in addition, a metal carrier plate and a filling material in the blind hole are both metals, and the two have similar CTEs and large tensile strength, thereby avoiding the problems of scraps and hidden cracks of the metals in an annealing process; and a metal oxide passivation layer is formed by performing an electroplating process on the metal carrier, and the metal oxide passivation layer has better water absorption resistance and insulation performance than silicon dioxide, thereby effectively improving the insulation performance of a device.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

The present invention relates to a photovoltaic backplate, a manufacturing method for the photovoltaic backplate, and a photovoltaic module. The photovoltaic backplate comprises: successively arranged from inside to outside, an adhesive film layer, an inner protective layer, a metal thin film, and an outer protective layer; the metal thin film has provided therein a plurality of first prefabricated holes, and the adhesive film layer, the inner protective layer, and the outer protective layer are each provided with a plurality of second prefabricated holes in one-to-one correspondence with the first prefabricated holes; the second prefabricated holes pass through the photovoltaic backplate, the centers of the second prefabricated holes are the same as those of the first prefabricated holes, and the dimensions of the first prefabricated holes are larger than the dimensions of the second prefabricated holes; the dimensions of the metal thin film are smaller than the dimensions of the adhesive film layer, the inner protective layer, and the outer protective layer, and a first spacing exists between the edges of the metal thin film and the edges of the adhesive film layer, inner protective layer, and outer protective layer. In the present invention, the photovoltaic backplate, the manufacturing method for the photovoltaic backplate, and the photovoltaic module set the metal film into the adhesive film layer and the inner and outer protective layers so as to avoid short circuits, thereby enhancing operational safety.

IPC Classes  ?

• H01L 31/049 - Protective back sheets
• H01L 31/048 - Encapsulation of modules
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

Provided in the present invention are a Lamb wave resonator and a filter, which improve the matching performance of acoustic impedance by means of adjusting and controlling local thin film thickness. Providing recesses in a piezoelectric thin film in first material areas, or forming a dielectric layer below a piezoelectric thin film in second material areas achieves local thickness adjustment for a Lamb wave resonator constituted by interdigital electrodes and having a thickness difference, such that the first material areas and the second material areas are offset with respect to each other in the thickness direction, thus suppressing a stray mode of the Lamb wave resonator; and the response filter is constructed on the basis of the resonator, so as to suppress the phenomenon of passband performance deterioration caused by the stray mode, thereby facilitating development of high-frequency large-bandwidth acoustic resonators.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details

Abstract

Provided in the embodiments of the present application are a simulation method and apparatus for a surface acoustic wave device, and an electronic device and a storage medium. The method comprises: performing modeling on a surface acoustic wave device, so as to obtain a surface acoustic wave device model; and for each preset frequency among a plurality of preset frequencies, executing the following operations: performing analysis processing on a core unit model on the basis of the preset frequency, so as to obtain a system matrix equation of the core unit model; performing classification and rearrangement processing on parameters in the system matrix equation, so as to obtain an initial target matrix equation of the core unit model; determining a target matrix equation on the basis of the initial target matrix equation of the core unit model; determining an admittance of the surface acoustic wave device at the preset frequency on the basis of the target matrix equation; and determining a frequency-response finite element simulation curve of the admittance of the surface acoustic wave device on the basis of the admittance of the surface acoustic wave device. By means of the simulation method for a surface acoustic wave device provided in the embodiments of the present application, a calculation process can be accelerated, and the occupancy of computer resources and a simulation time can be reduced.

IPC Classes  ?

• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

The present invention provides a chip fan-out packaging structure based on a shielding metal carrier plate and a preparation method therefor. The preparation method comprises: providing a shielding metal carrier plate; forming, on a first surface of the shielding metal carrier plate, at least one groove extending toward a second surface of the shielding metal carrier plate; providing a conductive adhesive in an area, on the bottom wall of the groove, in which a chip needs to be fixed, and carrying out baking for reinforcement after the chip is placed, so that the chip is adhered to the groove; filling the area outside the chip in the groove with a filling layer so as to stuff and flatten the groove; forming a rewiring layer on the first surface of the shielding metal carrier plate and the surface of the groove, the rewiring layer being electrically connected to the chip to implement the electrical lead-out of the chip; and forming metal bumps on the rewiring layer. The preparation method and the packaging structure of the present invention effectively reduce the process complexity of a chip fan-out packaging structure, improve the electromagnetic shielding performance and the heat dissipation performance of the chip fan-out packaging structure while reducing the manufacturing cost, and reduce the risk of warping and breakage of products.

IPC Classes  ?

• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

Provided in the present invention are a bulk acoustic wave resonator and a manufacturing method therefor. The bulk acoustic wave resonator comprises a first electrode, a second electrode and a piezoelectric film sandwiched between the first electrode and the second electrode. The piezoelectric film consists of n layers of polar piezoelectric films, every two adjacent layers thereof having opposite polarities, and an acoustic mirror is provided between a substrate and the first electrode. Using layering to manufacture the polar piezoelectric films having opposite polarities achieves polarity reversal, reduces requirements on piezoelectric film materials, and improves the resonator resonant frequency without reducing the total piezoelectric film thickness or introducing transition electrodes, thus simplifying processes, reducing acoustic wave loss, and improving the quality factor. In addition, the more the layers of polar piezoelectric films, the greater the ability to excite higher-order resonance modes, resulting in higher resonance frequency. The manufacturing method of the present invention improves the filter working frequency while reducing technical and device requirements. A new manufacturing method for high-frequency bulk acoustic wave resonators is provided.

IPC Classes  ?

• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Abstract

The present invention relates to a flexible monocrystalline silicon wafer and a preparation method therefor, and a flexible solar cell. The preparation method comprises: texturing and cleaning a monocrystalline silicon wafer, and forming pyramidal anti-reflection structures on the surface and the back side of the monocrystalline silicon wafer; performing, by means of plasma etching, smoothing processing on peaks and valleys in pyramids, edges and corners, protrusions and grooves of the front and back sides of side and edge portions of the monocrystalline silicon wafer; and cleaning. According to the method, the peaks and valleys in the pyramids, edges and corners, protrusions and grooves of the front and back sides of the side and edge portions of the monocrystalline silicon wafer become smooth, while the pyramid structures in the remaining regions remain unchanged and the surface reflectance does not change, so that the monocrystalline silicon wafer can have the characteristic of flexibility, thereby improving the mechanical properties.

IPC Classes  ?

• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present invention relates to a monocrystalline textured silicon wafer with a polished edge, and a solar cell and a preparation method. No pyramid-shaped textured structures are provided in edge areas of the front face and back face of the monocrystalline textured silicon wafer and a side-face area of the silicon wafer, and there are pyramid-shaped textured structures in areas other than the edge areas and the side-face area. The preparation method for a monocrystalline textured silicon wafer comprises: performing etch polishing; forming a mask; texturing; and removing the mask. There are no pyramid-shaped textured structures on an edge of the silicon wafer or a cell piece, and the edge has a relatively smooth structure; and when the silicon wafer or the cell piece is subjected to bending, vibration and thermal shock, stress concentration can be effectively prevented, such that the mechanical strength of the silicon wafer or the cell piece is improved, and the probability of the silicon wafer cracking during a production process is reduced, thereby improving the reliability of the cell piece and a cell assembly product.

IPC Classes  ?

• H01L 31/0236 - Special surface textures
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present invention relates to the technical field of microfluidic chips, in particular to a 3D-printing-resin-based flip chip. In the flip chip of the present invention, a core area is prepared by means of a thermoplastic printing process; a view window is formed by bonding a front fluid microchannel, a back fluid microchannel, front flow-through liquid storage pools and back lateral liquid storage pools with upper and lower transparent 3D printing sheet layers, thereby completing structure manufacturing; in a sample injection process, samples in the front flow-through liquid storage pools and samples in the back lateral liquid storage pools are independent of each other; after sample injection is completed, the two kinds of samples are mixed by means of the flip chip and are combined for a reaction; by means of structural design, the sizes of samples in detection pools can be automatically adjusted, and different concentration gradients are measured; and multiple targets are simultaneously detected by means of parallel design. The present invention involves a simple preparation process, high consistency and repeatability of chips prepared in batches, low cost, strong functionality, and good popularization and practicability.

IPC Classes  ?

• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
• G01N 21/64 - Fluorescence; Phosphorescence

Abstract

The present invention provides a crystal growing method, an apparatus and a RF-SOI substrate for growing a crystal. The crystal growing method may comprise: controlling a first superconducting coil to generate a first current, and controlling a second superconducting coil to generate a second current, wherein a value of the first current is not equal to a value of the second current, the first superconducting coil and the second superconducting coil are superconducting coils positioned oppositely outside a crucible to generate a magnetic field in the crucible; and pulling upwards to grow a monocrystalline in an asymmetric magnetic field generated by the first current and the second current in the crucible.

IPC Classes  ?

• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• H01F 6/06 - Coils, e.g. winding, insulating, terminating or casing arrangements therefor

Abstract

Provided in the present invention are a gallium oxide cascade structure based on heterogeneous integration, and a preparation method. By means of a heterogeneous integration method, a gallium oxide semiconductor material for which P-type doping cannot be realized is integrated with an enhanced device to prepare a cascade structure, and the cascade structure is prepared on a substrate having a high heat dissipation capability. On this basis, an enhanced cascade power device can be prepared, and high heat-conduction performance can be achieved, thereby solving the problem of it not being possible to prepare a normally-off device from gallium oxide and the problem of heat dissipation.

IPC Classes  ?

• H01L 21/8256 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups , or

Abstract

Provided in the present invention are a silicon carbide trench-type MOSFET based on a high-k dielectric, and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, an epitaxial layer being formed on an upper surface thereof; forming a P well in an upper surface layer of the epitaxial layer; forming an N-type source region located on an upper surface layer of the P well, and a P-type body contact region at least partially located in the P well and adjacent to the N-type source region in a horizontal direction; forming a trench; forming a high-k dielectric layer to cover an inner wall and a bottom surface of the trench and to extend to part of an upper surface of the N-type source region; forming a gate electrode layer in the trench; forming a source ohmic contact layer on an upper surface of the P-type body contact region to further extend to the upper surface of the N-type source region and be adjacent to the high-k dielectric layer; and forming a source metal layer covering the source ohmic contact layer and the gate electrode layer. The manufacturing method in the present invention can effectively ameliorate the problems of a gate oxide layer at a corner of a trench of a trench-type MOSFET device experiencing electric field concentration during reverse voltage withstanding and it being difficult to control the quality of a gate oxide layer on a side wall of the trench, thereby improving the performance of the device.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

In a method for preparing silicon-on-insulator, the first etching stop layer, the second etching stop layer, and the device layer are formed bottom-up on the p-type monocrystalline silicon epitaxial substrate, where the first etching stop layer is made of intrinsic silicon, the second etching stop layer is made of germanium-silicon alloy, and the device layer is made of silicon. After oxidation, bonding, reinforcement, and grinding treatment, selective etching is performed. Through a first selective etching to p+/intrinsic silicon, the thickness deviation of the first etching stop layer on the second etching layer is controlled within 100 nm, and then through the second etching and the third etching, the thickness deviation and the surface roughness of the finally prepared silicon-on-insulator film can be optimized to less than 5 nm and less than 4 Å, respectively, so as to realize the flatness of the silicon-on-insulator film.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
• H01L 21/321 - After-treatment
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

A dual-shaft electrostatically actuated micro-mirror without coupling between shafts, and an array device. The dual-shaft electrostatically actuated micro-mirror without coupling between shafts comprises: a substrate (10); an outer frame (12) twisted around an outer shaft (102); outer-shaft torsion beams (14) and anchors (19), which are configured to fix the outer frame to the substrate (10); outer-shaft drive units, which are arranged on two sides of the outer shaft (102), and each of which comprises two comb teeth groups distributed in a high-low interdigital manner; a mirror body (11) twisted around an inner shaft (101); inner-shaft torsion beams (13), which connect the mirror body and the outer frame (12); a reflective film (105) arranged on an upper surface of the mirror body (11); inner-shaft drive units, which are arranged on two sides of the inner shaft (101), and each of which comprises two comb teeth groups distributed in a high-low interdigital and staggered manner; and wires (103) and insulating dielectrics (104). The mirror body (11), the inner-shaft torsion beams (13) and the inner-shaft drive units are all follow-up structures of the outer frame (12), so as to achieve physical isolation of inner-shaft drive and outer-shaft drive to eliminate coupling interference between the shafts.

IPC Classes  ?

• G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light

Abstract

A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 Å, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

Provided in the present invention are a semiconductor substrate structure and a device. The semiconductor substrate structure comprises a substrate, conductive pillars, transverse insulation layers and vertical insulation layers. Vertical electrical conduction can be achieved by means of the conductive pillars, and electrical insulation can be achieved by means of the transverse insulation layers and the vertical insulation layers. The semiconductor substrate structure of the present invention can achieve 3D interconnection, has the advantages of high process compatibility, flexible design, suitability for high-temperature processes, etc., and can be used as a substrate structure of an integrated circuit device to achieve isolation among circuit element structures, reduce parasitic capacitance among transistors or among leads, and enhance irradiation resistance of devices. The semiconductor substrate structure of the present invention can also be used for design of MEMS devices to achieve electrical lead-out of devices, simplify packaging structures of devices, and enhance the array capability of devices, and can further be used for single-chip integrated devices such as a CMOS-MEMS to improve the integration level of devices, reduce crosstalk between IC circuits and MEMS devices, and improve the utilization rate of substrates.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

The present invention relates to a method for manufacturing a flexible thin monocrystalline silicon solar cell. The method comprises the following steps: S1, providing a monocrystalline silicon wafer; S2, texturing the monocrystalline silicon wafer, so as to produce a textured surface anti-reflection structure having a pyramidal morphology on at least one surface of the monocrystalline silicon wafer; S3, performing rounding of an edge portion of the monocrystalline silicon wafer, the edge portion being an edge region, the distance thereof from the edge of the monocrystalline silicon wafer being no greater than 5 mm; S4, washing the monocrystalline silicon wafer; and S5, manufacturing a flexible thin solar cell using the monocrystalline silicon wafer which has undergone rounding and washing. According to the method for manufacturing a flexible thin monocrystalline silicon solar cell of the present invention, a stress concentration generating region, which causes silicon wafer cracking, is eliminated, causing the thin monocrystalline silicon wafer to have flexible structural characteristics, and significantly increasing the flexibility of the monocrystalline silicon wafer. The process is simple, and the flexible thin monocrystalline silicon solar cell has broad application prospects and practical value.

IPC Classes  ?

• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• H01L 31/0224 - Electrodes
• H01L 31/0236 - Special surface textures

Abstract

A surface acoustic wave filter, comprising: a support substrate (10), a piezoelectric layer, a resonator member (20) and a spurious-mode suppression member (30), wherein the piezoelectric layer is arranged on the support substrate (10); the resonator member (20) is arranged on the support substrate (10); one end of the spurious-mode suppression member (30) is connected to an output end of the resonator member (20), and the other end of the spurious-mode suppression member (30) is grounded; and the frequency where the resonance peak of the spurious-mode suppression member (30) is located is consistent with the center frequency of a high-frequency spurious mode of the resonator member (20), and when the lowest frequency excitation mode of the spurious-mode suppression member (30) is a zero-order horizontal shear wave mode, the wavelength of the spurious-mode suppression member (30) does not exceed the wavelength of the resonator member (20) by a first preset numerical multiple, and when the lowest frequency excitation mode of the spurious-mode suppression member (30) is a high-frequency spurious mode, the wavelength of the spurious-mode suppression member (30) does not exceed the wavelength of the resonator member (20) by a second preset numerical multiple. The surface acoustic wave filter can effectively suppress a high-frequency spurious mode caused by the characteristics of the material of a surface acoustic wave resonator, such that the performance of the surface acoustic wave filter is improved.

IPC Classes  ?

• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/05 - Holders or supports
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

The present invention relates to a micro-nano structure sensitive to a laser beam in a specific direction, including a substrate, wherein an insulating layer is fixedly disposed on the substrate, the insulating layer is provided with two silicon nanowires parallel to each other and having the same shape and size, lead-out nanowires are arranged at both ends of each of the silicon nanowires and are connected with a potentiometer, and a near-field coupling effect occurs between the silicon nanowires and the substrate when laser light irradiates the silicon nanowires, and one silicon nanowire closer to a laser light source is completely suppressed and the other silicon nanowire farther away from the laser light source maintains brightness. The present invention enables precise detection of a laser signal at a specific angle and non-contact signal transmission in a specific direction.

IPC Classes  ?

• G02B 6/122 - Basic optical elements, e.g. light-guiding paths

Abstract

The present invention relates to the technical field of microelectronics. Disclosed in the present invention are a high-frequency acoustic-wave resonator and a filter using same. The high-frequency acoustic-wave resonator comprises a support substrate, a bottom electrode, a piezoelectric film and an interdigital transducer, which are sequentially stacked from bottom to top, wherein the interdigital transducer comprises a first busbar and a plurality of first electrodes arranged at intervals; the first busbar is connected to the same side of the plurality of first electrodes; the product of the distance between the centers of adjacent first electrodes among the plurality of first electrodes and the frequency of a target mode is less than the acoustic velocity of the support substrate; and the target mode is a high-order mode of the high-frequency acoustic-wave resonator excited under the action of a longitudinal electric field. The acoustic-wave resonator provided in the present application is established on a heterogeneous integrated substrate, and is characterized in that the structure is simple, the piezoelectric film has a high strength, and the quality of the acoustic wave resonator can also be ensured.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details

Abstract

The present application relates to the technical field of the preparation of heterogeneous integrated devices. Provided are a structure of a longitudinal leaky surface acoustic wave resonator, and a filter. The structure of an acoustic wave resonator comprises a substrate, a piezoelectric thin film arranged on the substrate, and electrode arrays arranged on the piezoelectric thin film, wherein the electrode arrays comprise an interdigital electrode array and a reflective gate electrode array, and the distance between the centers of reflective gate electrodes in the reflective gate electrode array is less than the distance between the centers of interdigital electrodes in the interdigital electrode array. On the basis of a non-standard reflective gate structure provided in the embodiments of the present application, a reflection frequency interval of a reflective gate electrode array can be improved by means of reducing the distance between the centers of reflective gate electrodes in the reflective gate electrode array, such that a stray mode of a longitudinal leaky wave can be inhibited, thereby improving the performance of an acoustic wave resonator.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details

Abstract

The present invention provides a method of growing a single-crystal silicon, comprising: loading a batch of polysilicon material in a crucible of a furnace, heating the crucible to melt the polysilicon material into a mass of silicon melt, confirming a liquid surface of the mass of silicon melt, applying a superconducting magnetic field to the mass of silicon melt with a magnetic field generator and adjusting a position of the magnetic field generator to position a maximum point of the superconducting magnetic field within a predetermined range under the liquid surface, and dipping a seed crystal into the silicon melt, and pulling the seed crystal during rotation of the seed crystal to crystallize the single crystal under the seed crystal until forming an ingot of single-crystal silicon. Oxygen content in the ingot is controlled through positioning the maximum point of the superconducting magnetic field under the liquid surface. According to the present invention, it is needless to change heat field, cost is low and success rate to pull the single crystal is high.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

Abstract

A terahertz dual-comb spectrum stabilization system, comprising an optical loop, used for coupling a first optical frequency comb signal to a second optical frequency comb signal; and a frequency mixer, used for performing frequency mixing on the coupled first optical frequency comb signal and second optical frequency comb signal to generate a dual-comb signal. A local oscillator signal end of the frequency mixer is connected to a multi-stage frequency multiplication link, the multi-stage frequency multiplication link is used for performing frequency multiplication processing on a radio frequency signal, then an intrinsic signal of a terahertz wave band is generated by means of frequency multiplication by the frequency mixer, the intrinsic signal of the terahertz wave band is respectively mixed with the first optical frequency comb signal and the second optical frequency comb signal in the frequency mixer, and two down-conversion optical frequency comb signals are generated in a microwave wave band; and comb teeth of the two down-conversion optical frequency comb signals are respectively locked to lock the carrier drift frequency, so as to obtain a stable dual-comb spectrum. The system can lock the carrier frequency without introducing a femtosecond laser.

IPC Classes  ?

• G02F 1/35 - Non-linear optics

Abstract

A process management method and an electronic device. In the method, process data in a volatile memory can be migrated in real time to a non-volatile memory while a system is running; data in a memory does not need to be packaged and backed up when the system is dormant, data does not need to be parsed and reconstructed when the system is awakened or restarted, and the system can quickly go dormant and awaken; even if the system is restarted in a situation such as accidental power loss, key data in the memory can be prevented from being lost, and the speed of awakening or restarting the system can likewise be increased.

IPC Classes  ?

• G06F 3/14 - Digital output to display device

Abstract

The present invention provides a selector material, a selector unit and a preparation method thereof and a memory structure, wherein the selector material comprises at least one of Te, Se and S, that is, the selector material is selected from a simple substance such as Te, Se and S or compounds composed of any of these elements, further, the performance can be improved by doping with elements such as O, N, Ga, In, As and the like, or oxides, nitrides and carbides or other dielectric materials. The selector material in the present invention has the advantages of high turn-on current, simple material, fast switching speed, good repeatability and low toxicity when the selector material is used in the selector unit, which is beneficial to achieving high-density three-dimensional information storage.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

Provided in the present invention are a switch device and a memory. The switch device comprises a lower electrode, an upper electrode and a switch material layer sandwiched between the lower electrode and the upper electrode, wherein the switch material layer contains at least one element from among Te, Se and S; when the switch device is in a turned-on state, the switch material layer is in a liquid state, and a band gap thereof is 0; and when the switch device is in a turned-off state, the switch material layer is in a crystalline state, a Schottky barrier is formed between the switch material layer and the upper electrode, and a Schottky barrier is formed between the switch material layer and the lower electrode. A crystalline-liquid-crystalline phase-change switching mechanism of a switch material is applied to the switch device in the present invention, and the switch device has advantages such as a turn-on current being great, a leakage current being small, a threshold voltage being small, cells having a high consistency, being compatible with a CMOS process, the thermal stability being good, elements being simple, the toxicity being low, and being capable of realizing extreme atrophy; and a memory cell, such as a phase-change memory cell, a resistive memory cell, a ferroelectric memory cell and a magnetic memory cell, can be driven, thereby realizing high-density three-dimensional information storage.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• G11C 11/4063 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method for characterizing graphene on a platinum substrate, including: coating a methylene blue developing solution to a platinum substrate having a surface covered with graphene, so that the methylene blue developing solution reacts with hydrogen-containing gas under catalysis of platinum to yield colorless methylene white; after the pressure is restored, methylene white in the exposed area of platinum substrate will quickly turn blue when it is oxidized into methylene blue by reacting with oxygen in the air under catalysis of platinum. Thus, color difference can be formed to facilitate the observation of the graphene. The characterization method is highly reproducible and simple, and can be used to characterize graphene with a large area on a platinum substrate. The characterization method does not damage the graphene and platinum substrate, has no negative impact on the quality of graphene, and the platinum substrate can be recycled to reduce costs.

IPC Classes  ?

• G01N 33/208 - Coatings, e.g. platings
• G01N 21/78 - Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator producing a change of colour

Abstract

A method and apparatus for generating easily processed super-atoms of random shapes, and a storage medium. The method comprises: generating super-atoms on the basis of a super-atomic inverse square generation function; and screening the generated super-atoms on the basis of the minimum line width, so as to obtain super-atoms, which meet a processing condition. Super-atoms generated by means of the method have smooth edges without any chamfer; and by means of the method, the minimum line width can be customized to screen out particles or small holes having sizes which are too small and to remove same, and thus the generated super-atoms can be very easily processed, such that the method has a practical value in terms of micro-nano processing of a meta-surface.

IPC Classes  ?

• G06F 30/20 - Design optimisation, verification or simulation

Abstract

Provided in the present invention are a regeneration method for a nitride film etching liquid and an etching method for a nitride film. The regeneration method comprises the step of removing etching product ammonium ions in an etching residual liquid generated after the wet etching of a nitride film so as to regenerate an etching liquid. By means of the improved process of the present invention, ammonium ions can be removed online under the condition that the etching process is not stopped, such that the service life of the etching liquid can be prolonged, the operation of replacing the etching liquid is reduced, the production efficiency is improved, and the etching cost is reduced; in addition, the environmental pollution can be reduced by reducing the discharge of waste liquid.

IPC Classes  ?

• C02F 9/10 - Thermal treatment
• C02F 101/16 - Nitrogen compounds, e.g. ammonia
• H01L 21/311 - Etching the insulating layers

Abstract

The present disclosure relates to a method for treating a wafer surface. By controlling the gas composition at each stage of the treatment process, and corresponding processes of heating and annealing, and cooling and thinning by oxidation, the final wafer is enabled to have a surface roughness of less than 5 Å. This effectively reduces the cost of the final treatment process and has good application prospects.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/311 - Etching the insulating layers

Abstract

A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

The present disclosure relates to a method for improving the surface roughness of a SOI wafer. By controlling the gas composition at each stage of the rapid thermal treatment process and corresponding heating and annealing processes, the final wafer is enabled to have a surface roughness of less than 5Å and has good application prospects.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon. The present method can optimize the atmosphere for batch annealing to achieve better planarization than the conventional technologies. Specifically, the obtained top silicon layer of the SOI wafer has a surface roughness of less than 4 Å.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• C30B 29/06 - Silicon
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

Provided in the present invention are a wet etching device and a wet etching method. The wet etching device comprises an etching chamber and an adsorption module. One end of the adsorption module is in communication with a liquid discharge port of the etching chamber and/or the adsorption module is arranged in the etching chamber. The etching chamber is used for the wet etching of silicon oxide, silicon or silicon nitride on a substrate. The adsorption module is provided with an adsorption substance for adsorbing an etching product, i.e. a silicon compound. An etching solution during the etching process of a silicon oxide, silicon or silicon nitride material in the etching chamber flows through the adsorption module, and the etching product, i.e. the silicon compound, is adsorbed and removed by the adsorption module, so that the regeneration of the etching solution is achieved. According to the wet etching device of the present invention, the adsorption module, which can adsorb the silicon compound, is arranged on the circulation path of the etching solution, so that the service life of the etching solution can be effectively prolonged, the usage cost is reduced, the environmental pollution caused by the waste liquid discharge of the etching solution is reduced, and the frequency of replacing the etching solution can be reduced, which contributes to improving the production efficiency.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions

Abstract

A combined etching liquid, an etching system and an etching method of the present invention can be applied to the wet etching of a non-conductive thin film in semiconductor manufacturing. The combined etching liquid comprises a first etching liquid and a second etching liquid, wherein the first etching liquid is used for etching a non-conductive thin film, and the second etching liquid contains a component which can remove the reaction product of the etching of the non-conductive thin film with the first etching liquid; or a third etching liquid is present therein and contains a component used for removing another etching product of the first etching liquid, so as to prolong the service life of the first etching liquid. By taking the combined etching liquid for etching silicon nitride as an example, the first etching liquid contains phosphoric acid, and the second etching liquid contains a fluorine-containing compound; in combination with an etching apparatus, the temperature and the water content of an etching liquid in a mixing reaction chamber are adjusted, and a specific removable fluorine-silicon compound can be generated from the fluorine-containing compound by means of reaction with a phosphoric acid etching product, i.e. a silicon compound, such that the service life of the first etching liquid can be prolonged, the acid changing operation can be reduced, and the production efficiency can be improved.

IPC Classes  ?

• C09K 13/06 - Etching, surface-brightening or pickling compositions containing an inorganic acid with organic material
• C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
• H01L 21/311 - Etching the insulating layers
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

The present invention relates to an arrayed waveguide grating which has uniform channels, comprising an input waveguide end, a free transmission region and output waveguide ends, wherein the input waveguide end is connected to one end of the free transmission region, and the other end of the free transmission region is connected to a plurality of output waveguide ends separately. The arrayed waveguide grating is characterized in that the free transmission region is divided into several regular-shaped cells, and the status of the regular-shaped cells is adjusted according to a DBS imaging algorithm and a preset objective function, so that far-field distributions of the output waveguide end located at the center and the output waveguide end located at the edge are flat-topped. The present invention solves the problem of a 3 dB difference between a maximum insertion loss value and a minimum insertion loss value among output channels of a conventional arrayed waveguide grating.

IPC Classes  ?

• G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,
• G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

Abstract

A miniature laser radar receiving apparatus. The apparatus comprises a spherical base (1), wherein a micro-nano photoelectric detection array (2) is provided on a surface of the spherical base (1), and the micro-nano photoelectric detection array (2) is composed of several micro-nano photoelectric detection units (21), which are uniformly arranged. The laser radar receiving apparatus can test the direction and distance of light, has low operation complexity, and also has the advantages of a small size, lightweight, ease of integration and cross-scale measurement.

IPC Classes  ?

• G01S 7/486 - Receivers
• G01S 7/4912 - Receivers

Abstract

The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid

Abstract

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A cryogenic memory cell and a memory device are provided. The cryogenic memory cell includes a spin moment transfer device. The spin moment transfer device converts a write current into a spin polarization current and changes a magnetic polarization direction under the action of the spin polarization current to achieve write storage of 0 and 1. The cryogenic memory cell also includes a nano-superconducting quantum interference device; a ground terminal of the nano-superconducting quantum interference device is in common-ground connection with a ground terminal of the spin moment transfer device, and the nano-superconducting quantum interference device undergoes a magnetic flux change under the action of a change in the magnetic polarization direction of the spin moment transfer device, thereby switching between a superconducting state and a non-superconducting state under a read current bias, to achieve read-out of 0 and 1.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices

Abstract

The present application provides a compound eye camera device comprising a plurality of ommatidia arranged in a column or a row, and each of the ommatidia comprises an optical element and corresponding photosensitive units; each of the ommatidium columns corresponds to at least one ommatidium-column visual plane, the at least one ommatidium-column visual plane passing through the optical center of each ommatidium in the ommatidium column and a position near the center of at least one photosensitive unit of each ommatidium; each photosensitive unit intersects at least one ommatidium-column visual plane, and sight line of each photosensitive unit passes through the center of the photosensitive unit and the optical center of the ommatidium where the photosensitive unit is located; and a processor is configured to generate images based on information received by the photosensitive units, and to process the images to obtain information regarding the photographed object.

IPC Classes  ?

• H04N 23/55 - Optical parts specially adapted for electronic image sensors; Mounting thereof
• H04N 23/45 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
• H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils

Abstract

The present disclosure provides a method for preparing patterned graphene, and the method includes using a silicon carbide base as a solid-state carbon source, decomposing the silicon carbide under the action of high temperature and catalyst, to directly grow graphene on an insulating substrate. Through a first patterned trench and a second patterned trench in an accommodating passage, the pattern of the formed graphene can be directly controlled. Therefore, the present disclosure can accurately locate the position of the patterned graphene on the insulating substrate, it does not require transferring the graphene one more time, thereby avoiding contaminating the graphene and damaging its structure, and there is no need for photo-lithography, ion etching and other processes to treat the graphene in order to obtain patterned graphene, which further avoids damages to the graphene.

IPC Classes  ?

• C01B 32/186 - Preparation by chemical vapour deposition [CVD]

Abstract

A method for testing activation energy of a catalyst comprises: obtaining a changing curve of a resonant frequency variation over time by means of an integrated self-heating resonant cantilever beam (100), and converting the changing curve into a curve of a resonant frequency changing along with a temperature, and further converting the curve into a changing curve of a coverage degree along with the temperature; after first-order differential is performed, extracting a relevant parameter corresponding to a minimal value, then substituting the relevant parameter into a formula, so as to obtain a catalyst desorption rate constant and catalyst desorption activation energy, so that the test of the activation energy of the catalyst can be performed only by a one-time programed heating process; moreover, the test result is accurate, rapid and convenient, and a catalyst sample is small in consumption, and low in price.

IPC Classes  ?

• G01N 5/02 - Analysing materials by weighing, e.g. weighing small particles separated from a gas or liquid by absorbing or adsorbing components of a material and determining change of weight of the adsorbent, e.g. determining moisture content

Abstract

A micro-power wireless access method and apparatus for the Internet of things for power transmission and transformation equipment involves a time synchronization process, a traffic channel access process, a control channel configuration information access process, and a control channel burst information access process. In the time synchronization process, an aggregation node determines a delay parameter and other parameters based on a timeslot in which traffic information randomly transmitted by a sensing terminal is located, and the sensing terminal adjusts transmission time of a corresponding frame based on the parameters. The traffic channel access process adopts a mode in which one-way reporting is mainly used, to minimize working time of a sensor. The present disclosure realizes limited two-way communication on a control channel, supports configuration of a sensor cycle, a threshold, and other parameters, and supports a retransmission mechanism on the control channel for important alarm information.

IPC Classes  ?

• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 28/06 - Optimising, e.g. header compression, information sizing
• H04W 52/02 - Power saving arrangements
• H04W 74/02 - Hybrid access techniques
• H04W 74/04 - Scheduled access
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
• H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks

Abstract

The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects. It is no need to break the ingot to obtain the crystallographic defect distribution of the whole ingot, through which the technology for growing the ingot may be effectively adjusted to obtain the ingot with required characteristics of defect.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

The present invention relates to a star coupler capable of uniform power distribution. The star coupler comprises an input waveguide end, an FPR region and an output waveguide end, wherein the output waveguide end comprises a plurality of output waveguides; the input waveguide end is connected to one end of the FPR region, and the other end of the FPR region is respectively connected to the plurality of output waveguides; the FPR region is a fan-shaped region with a coupling point of the input waveguide end and the FPR region serving as the center and the length of the FPR region serving as the radius; the FPR region is provided with several regularly-shaped unit cells; and the state of the regularly-shaped unit cells is adjusted according to a preset imaging algorithm and a preset objective function, such that the power of the output waveguides is uniformly distributed. The present invention further relates to a design method for a star coupler capable of uniform power distribution. By means of the method, the problem of the output power distribution of a star coupler not being uniform can be effectively overcome, and the computation amount is small and the complexity is low.

IPC Classes  ?

• G02B 6/125 - Bends, branchings or intersections
• G02B 6/26 - Optical coupling means
• G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,

Abstract

A phase change material, a phase change memory cell, and a preparation method thereof. The phase change material comprises elements tantalum, antimony and tellurium, the phase change material having a chemical formula of TaxSbyTez, wherein x, y, and z represent atomic ratios of the elements respectively; and 1≤x≤25, 0.5≤y:z≤3, and x+y+z=100. The phase change thin film material TaxSbyTez has a high phase change speed, outstanding thermal stability, strong data retention capability, a long cycle life, and a high yield. Ta5.7Sb37.7Te56.6 has ten-year data retention capability at 165° C.; and applying same in a device cell of a phase change memory achieves an operating speed of 6 ns and endurance of more than 1 million write-erase cycles. The crystal grains of the phase change material TaxSbyTez of the present disclosure are small, and after annealing treatment at 400° C. for 30 minutes, the grain size is still smaller than 30 nm.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

An in-situ real-time temperature programmed analytical method, comprising: dropwise adding a sample, which is to be tested, to a sample application area of at least one test sensor (1); performing, within a first preset temperature range, temperature programming on the test sensor (1), so as to obtain a baseline, wherein the baseline is obtained by recording resonant frequency change data of the test sensor (1) in the process of temperature programming; performing, within a second preset temperature range, temperature programming on the test sensor (1), so as to obtain a measurement curve, wherein the measurement curve is obtained by recording the resonant frequency change data of the test sensor (1) in the process of temperature programming; and obtaining a temperature programmed analytical curve according to the baseline and the measurement curve. A test sensor (1) integrated with heating and data acquisition functions is used to perform temperature programmed analysis on a sample to be tested, thereby reducing the hysteresis of a test result. In addition, high precision and good responsiveness are achieved, and the temperature programmed analytical method is simplified, such that accurate quantitative analysis of a sample is achieved.

IPC Classes  ?

• G01N 5/04 - Analysing materials by weighing, e.g. weighing small particles separated from a gas or liquid by removing a component, e.g. by evaporation, and weighing the remainder

Abstract

The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability. In addition, the method can be applied to all crystal defect types, is easy to operate, and is an environmentally friendly method for determination of grown-in defects.

IPC Classes  ?

• C30B 29/06 - Silicon
• G01N 21/956 - Inspecting patterns on the surface of objects
• G01N 21/88 - Investigating the presence of flaws, defects or contamination

Abstract

The present invention provides a high-throughput vapor deposition apparatus and a vapor deposition method. A rotary workbench (2) is located in a reaction chamber (1); a gas introduction device (3) is located in the reaction chamber (1) and above the rotary workbench (2); a plurality of through holes (31) is provided on the gas introduction device (3); a gas isolation structure (4) divides an upper chamber (11) into an isolation gas chamber (111) and a reaction gas chamber (112) which are isolated from each other; an isolation gas is introduced into the isolation gas chamber (111) via an isolation gas introduction channel (5), and a reaction gas is introduced into the reaction gas chamber (112) via a reaction gas introduction channel (6), for carrying out thin film deposition on an area of a substrate corresponding to the reaction gas chamber (112). The high-throughput vapor deposition apparatus only requires one isolation gas supply system and one reaction gas isolation system, a total of two systems, and thus is simple in structure, easy to implement, and good in isolation.

IPC Classes  ?

• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
• C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

Abstract

A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.

IPC Classes  ?

• H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
• H10N 60/12 - Josephson-effect devices
• H10N 60/80 - Constructional details
• H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
• G01J 1/44 - Electric circuits
• G01J 1/04 - Optical or mechanical part
• G06F 1/10 - Distribution of clock signals
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

The present invention provides a laser, including: a medium, having a ground state, an intermediate state, and an excited state in ascending order of energy; an excitation system, configured to excite electrons in the medium from the ground state to the intermediate state; and an excitation laser, configured to drive electrons in the intermediate state at different spatial positions in the medium to the ground state through a stimulated emission process with a fixed phase relationship, to generate a laser with a shorter relative wavelength. Due to the use of an excitation laser to drive electrons from the intermediate state, the photons generated by the stimulated emission have coherence, thereby forming a laser. In the present invention, an excitation system performing primary pumping combined with an excitation laser with a relatively long wavelength performing secondary pumping generate lasers with a relatively short wavelength, and the structure of the short-wavelength laser is simple, compact, and easy to be implemented. In addition, the cost of the short-wavelength laser can be reduced, and a laser with a shorter wavelength can be obtained.

IPC Classes  ?

• H01S 3/23 - Arrangement of two or more lasers not provided for in groups , e.g. tandem arrangement of separate active media
• H01S 3/094 - Processes or apparatus for excitation, e.g. pumping using optical pumping by coherent light
• H01S 3/22 - Gases

Abstract

The present disclosure provides a phase change memory and a method for making the same. The phase change memory includes a substrate, a plurality of phase change memory cells, and an isolation material layer. The plurality of phase change memory cells are separately disposed on the substrate, the phase change memory cell sequentially includes, from bottom to top, a first electrode material layer, a first transition material layer, an ovonic threshold switching (OTS) material layer, a second transition material layer, a second electrode material layer, a third transition material layer, a phase change material layer, a fourth transition material layer, and a third electrode material layer; The isolation material layer is disposed on the substrate and surrounds side surfaces of the phase change memory cell, and the plurality of phase change memory cells are isolated from each other by isolation material layer.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

The present application provides a terahertz spectrum measurement system and a method for analyzing a terahertz spectrum of a substance, wherein the terahertz spectrum measurement system comprises: two terahertz quantum cascade lasers with their emission ports arranged oppositely; and a vacuum hood arranged between the emission ports of two terahertz quantum cascade lasers. The terahertz spectrum measurement system and the method for analyzing a terahertz spectrum of a substance realize a separate terahertz dual frequency comb while retaining the advantages of the on-chip dual frequency comb system, which solves the problem that the on-chip dual frequency comb cannot directly measure the terahertz spectra of substances.

IPC Classes  ?

• G01N 21/3581 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light using Terahertz radiation
• G01N 21/01 - Arrangements or apparatus for facilitating the optical investigation
• H01S 5/042 - Electrical excitation
• H01S 5/34 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
• G01N 21/39 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using tunable lasers

Abstract

The present invention relates to a silicon-based Mach-Zehnder interferometer based on a Y-branch symmetric structure. The silicon-based Mach-Zehnder interferometer comprises: an input Y-branch waveguide and an output Y-branch waveguide, wherein the input Y-branch waveguide and the output Y-branch waveguide are of the same structure, and a first output end of the input Y-branch waveguide is connected to a first input end of the output Y-branch waveguide by means of a first straight waveguide; a second output end of the input Y-branch waveguide is connected to one end of a first curved waveguide, a second input end of the output Y-branch waveguide is connected to one end of a second curved waveguide, and the other end of the first curved waveguide is connected to the other end of the second curved waveguide by means of a second straight waveguide; and the first curved waveguide and the second curved waveguide are of the same structure and are symmetric about a center line of the second straight waveguide. By means of the present invention, the stable transmission efficiency can be achieved when a waveguide length is changed between 10 μm to 40 μm.

IPC Classes  ?

• G02B 6/125 - Bends, branchings or intersections

Abstract

The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

Abstract

A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a micro-displacement mechanism with a non-Hermitian coupling angle detection and correction device. A substrate is fixed on the upper surface of a rigid bottom plate, an insulating layer is fixed on the substrate, two identical silicon wire groups are arranged on the insulating layer, the silicon wire groups comprise a plurality of silicon wires that are parallel to each other and have the same shape and size, and the distances between adjacent silicon wires are equal; the silicon wires are perpendicular to the front and rear sides of the rigid bottom plate; a scattering light source is arranged on the lower surface of a rigid top plate; when a laser emitted by the scattering light source is irradiated on the silicon wire groups, a near-field coupling effect occurs between the silicon wires and the substrate, and one silicon wire in the silicon wire groups is completely inhibited. The present invention can simultaneously detect and correct the displacement error of the rigid top plate of a parallelogram flexible hinge mechanism along the x-axis direction under the action of F force and the parasitic rotation angle error of the rigid top plate around the y-axis.

IPC Classes  ?

• G01B 11/02 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness

Abstract

A micro-space three-dimensional morphology measurement apparatus comprising a light source assembly and at least two detection assemblies, wherein the detection assemblies comprise substrates (8, 11), insulating layers (7, 12) are fixedly provided on the substrates (8, 11), a plurality of silicon wires (1, 2, 13) that are mutually parallel and have a same size and shape are arranged on the insulating layers (7, 12), and the distance between adjacent silicon wires (1, 2, 13) is the same, two ends of each silicon wire (1, 2, 13) both lead out wires (3, 4) and are connected to electrical potential measurement meters (5, 6), and the electrical potential measurement meters (5, 6) are connected to processors; the light source assembly performs line-by-line scanning on a surface of a measured sample (14) by means of laser light, and when laser light reflected by the measured sample (14) shines onto the detection assemblies, a near-field coupling effect occurs between the silicon wires (1, 2, 13) and the substrates (8, 11), and causes an amplitude of a resonator formed by the silicon wires (1, 2, 13) and the substrates (8, 11) to produce to be completely suppressed, and the processors calculate position information of a reflection point of the surface of the measured sample (14) according to continuous signals output by the electrical potential measurement meters (5, 6) connected to the silicon wires (1, 2, 13).

IPC Classes  ?

• G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures

Abstract

The present invention relates to a micro-nano structure sensitive to a laser beam in a specific direction. The micro-nano structure comprises a substrate, wherein an insulating layer is fixedly arranged on the substrate; and two silicon wires, which are parallel to each other and are in the same shape and size, are arranged on the insulating layer, and wires are led out from two ends of each silicon wire and are connected to potential meters. When laser light irradiates the silicon wires, a near-field coupling effect is generated between the silicon wires and the substrate; and one silicon wire close to a laser light source is completely inhibited, and the other silicon wire far away from the laser light source maintains the brightness thereof. By means of present invention, a laser signal at a certain specific angle can be accurately detected, and non-contact signal transmission can be carried out in a specific direction.

IPC Classes  ?

• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• G02B 6/122 - Basic optical elements, e.g. light-guiding paths
• B82Y 35/00 - Methods or apparatus for measurement or analysis of nanostructures

Abstract

The present invention relates to an optoelectronic barcode system based on a non-Hermitian coupling principle. A barcode recognition device comprises a substrate; an insulting layer is fixedly provided on the substrate; a plurality of silicon wires which is parallel to each other and has the same shape and size is provided on the insulating layer, and the distances between adjacent silicon wires are equal; wires are lead out from either end of each silicon wire so as to be connected to a potentiometer; the potentiometer is connected to a processor; the middle of the substrate is provided with a through hole for laser light emitted by a laser device to pass through; the laser device is fixed relative to the substrate; when the laser light emitted by the laser device irradiates on a barcode and is then reflected onto the silicon wires, a near-field coupling effect occurs between the silicon wires and the substrate, and a resonator formed by the silicon wires and the substrate is made to produce amplitude complete suppression; and the processor calculates the position of a laser light reflection point according to position information of two silicon wires, among the silicon wires, having minimum potential values. The present invention can provide a barcode identifier for a micro-nano device.

IPC Classes  ?

• G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code

Abstract

Disclosed in the present invention is a wireless communication method for node devices in Internet of Things (IoT) of a power transmission and transformation device. In IoT of a power transmission and transformation device, communication channels between a master device and slave devices include a broadcast channel, a downlink control channel, a multicast channel, a downlink shared channel, an uplink random contention channel and an uplink shared channel, different channels being distinguished by channel type fields of MAC frame headers; and communication processes between the master device and the slave devices are set, and include a node broadcast process, a random access process, a pre-allocation registration process, a scheduling communication process of an uplink shared control channel, a discontinuous reception (DRX) scheduling communication process, a communication process of a downlink shared control channel, a packet fragmentation process, etc.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
• H04W 76/28 - Discontinuous transmission [DTX]; Discontinuous reception [DRX]

Abstract

Disclosed in the present invention are a micropower wireless access method and apparatus for Internet of Things of a power transmission and transformation device. The method relates to the time synchronization, service channel access, control channel configuration information access and burst information access processes. In time synchronization, an aggregation node determines parameters such as delay according to a time slot in which service information randomly sent by a sensing terminal is located, and the sensing terminal adjusts the sending time of a corresponding frame according to the parameters. The service channel access process adopts a one-way reporting-based mode, such that the working time of the sensor is minimized. Limited two-way communication is realized in a control channel, parameter configurations of a sensor period, a threshold value and the like are supported, a retransmission mechanism is supported on the control channel for important alarm information, and the reliability of an alarm service is improved. According to the present invention, standardized access can be provided for the high-frequency, small-data-volume and low-power-consumption device state sensing sensor for the Internet of Things of the power transmission and transformation device, and the requirements for long service life and maintenance-free operation of the micro-power consumption sensor can be met.

IPC Classes  ?

• H04W 4/35 - Services specially adapted for particular environments, situations or purposes for the management of goods or merchandise
• H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
• H04W 52/02 - Power saving arrangements
• G06Q 50/06 - Electricity, gas or water supply

Abstract

34233N quantum dots. The product for measuring aerobic glycolysis is a reagent, and the final concentration of nitrogen-doped carbon fluorescent quantum dots in the reagent is 1 μg/mL to 1 mg/mL based on the final volume of the reagent. Fluorescent labelling of NAD+ in living cells can be performed by using the nitrogen-doped carbon fluorescent quantum dots, so that the fluorescent labelling and imaging of cells having aerobic glycolysis are realized. The method has the advantages of low costs, high efficiency, rapidness, and high accuracy, among others. At the same time, the technology contributes to the development of serial techniques such as fluorescent recognition, very early cancer warning, cancer metastasis detection, and cancer proliferation and cancer malignancy assessment, among others.

IPC Classes  ?

• G01N 21/64 - Fluorescence; Phosphorescence
• C09K 11/65 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing inorganic luminescent materials containing carbon
• B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals

Abstract

A tumor cell detection kit using nitrogen-doped carbon fluorescent quantum dots and a method of use therefor, the kit comprising a solution A and a solution B. The solution A is a nitrogen-doped carbon fluorescent quantum dot solution, and the liquid B is a buffer solution. The nitrogen-doped carbon fluorescent quantum dot solution consists of nitrogen-doped carbon fluorescent quantum dots and a solvent. The method of use therefor at least comprises the following steps: step S10, providing a reagent kit solution A, a solution B, a pleural fluid sample and a urine sample of a patient; step S20, performing high-speed centrifugation, resuspending the solution B, and then adding the solution A for dyeing; step S30, performing high-speed centrifugation, and resuspending the solution B; and S40, measuring the fluorescence intensity by a spectrophotometer. The present kit and method have high specificity and high sensitivity to detection of tumor cells in pleural fluid, urine liquid and tissue fluid, are easy to operate and low in cost. The present invention can improve doctors' diagnosis of clinical tumor in patients, and can further provide help for tumor prognosis, drug use screening, and individualized treatment plans.

IPC Classes  ?

• B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals
• A61P 35/00 - Antineoplastic agents
• B82Y 40/00 - Manufacture or treatment of nanostructures
• C01B 21/082 - Compounds containing nitrogen and non-metals
• C09K 11/65 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing inorganic luminescent materials containing carbon
• A61K 33/00 - Medicinal preparations containing inorganic active ingredients
• A61K 47/22 - Heterocyclic compounds, e.g. ascorbic acid, tocopherol or pyrrolidones

Abstract

The present invention provides a temperature-insensitive Mach-Zehnder interferometer, including: a first mode converter; a second mode converter, located on one side of the first mode converter and with a distance from the first mode converter; and a connecting arm, located between the first mode converter and the second mode converter, one end of the connecting arm is connected with the first mode converter, and the other end is connected with the second mode converter. The connecting arm includes a straight waveguide connecting arm. The temperature-insensitive Mach-Zehnder interferometer of the present invention can be configured to be insensitive to temperature by adjusting parameters such as the width and thickness of the connecting arm.

IPC Classes  ?

• G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
• G01B 9/02056 - Passive reduction of errors

Abstract

The present invention discloses a channel simulation method, propagation paths among transmitters, receivers, scattering vertices, reflecting vertices, and diffracting vertices being identified based propagation-graph of the propagation, comprising the following steps: calculating the propagation effects of scattering by the transmitters, receivers, the scattering vertices, to obtain a scattering channel transfer function; calculating the propagation effects of reflection by the transmitters, receivers, the reflecting vertices, to obtain a reflecting channel transfer function; calculating the propagation effects of diffraction by the transmitters, receivers, the diffracting vertices, to obtain a diffracting channel transfer function; calculating the total channel transfer function by adding the scattering channel transfer function, the reflecting channel transfer function, and the diffracting channel transfer function. According to the present invention, the channel simulation results obtained exhibit fidelity and yield broad applications in the field of wireless communication, radar, and environment sensing.

IPC Classes  ?

• H04B 17/391 - Modelling the propagation channel

Abstract

A method for preparing a film bulk acoustic wave device by using a film transfer technology includes: 1) providing an oxide monocrystal substrate; 2) implanting ions from the implantation surface into the oxide monocrystal substrate, and then forming a lower electrode on the implantation surface; or vice versa; and forming a defect layer at the preset depth; 3) providing a support substrate and bonding a structure obtained in step 2) with the support substrate; 4) removing part of the oxide monocrystal substrate along the defect layer so as to obtain an oxide monocrystal film, and transferring the obtained oxide monocrystal film and the lower electrode to the support substrate; 5) etching the support substrate from a bottom of the support substrate to form a cavity; 6) forming an upper electrode on the surface of the oxide monocrystal film.

IPC Classes  ?

• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Abstract

Disclosed a heat shield structure for a single crystal production furnace, which is provided above a melt crucible of a single crystal production furnace and comprises an outer housing and a heat insulation plate disposed within the outer housing. A bottom outer surface of the outer housing faces an interior of the melt crucible, and an angle formed between a plane in which the heat insulation plate is located and a plane in which a bottom of the outer housing is located is an acute angle and faces an outer surface of single crystal silicon. The heat shield design is changed, a heat absorbing plate is additionally provided for transferring heat absorbed to the single crystal silicon, a heat channel is formed in the heat shield, so that a pulling rate is controlled, which improves radial mass uniformity of the single crystal silicon.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 29/06 - Silicon

Abstract

A selector material, a selector unit, and a preparation method and a memory structure, the selector material comprising at least one from among Te, Se, and S, that is to say, a singular material of Te, Se, or S or a compound formed from any elements therefrom is selected for use as the selector material. Further, by means of doping with such elements O, N, Ga, In, or As, or a dielectric material such as an oxide, a nitride, or a carbide, performance can be improved. The use of the selector material of the present invention in a selector unit results in such features as a large open-state current, simple materials, rapid switching, excellent repeatability, and low toxicity, helping to implement high density 3D information storage.

IPC Classes  ?

• H01L 21/24 - Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

Abstract

The present invention provides a method for preparing a gallium oxide semiconductor structure and a gallium oxide semiconductor structure obtained thereby. The method comprises: providing a gallium oxide single-crystal wafer (1) having an implantation surface (1a) (S1); performing an ion implantation from the implantation surface (1a) into the gallium oxide single-crystal wafer (1), such that implanted ions reach a preset depth and an implantation defect layer (11) is formed at the preset depth (S2); bonding the implantation surface (1a) to a high thermal conductivity substrate (2) to obtain a first composite structure (S3); performing an annealing treatment on the first composite structure such that the gallium oxide single-crystal wafer (1) in the first composite structure is peeled off along the implantation defect layer (11), thereby obtaining a second composite structure and a third composite structure (S4); and performing a surface treatment on the second composite structure to remove a first damaged layer (111), so as to obtain a gallium oxide semiconductor structure comprising a first gallium oxide layer (12) and the high thermal conductivity substrate (2) (S5). In the gallium oxide semiconductor structure formed using the above method, the first gallium oxide layer (12) is integrated with the high thermal conductivity substrate (2) to effectively improve the thermal conductivity of the first gallium oxide layer (12).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or

Abstract

A superconducting magnetic flux storage unit and a reading and writing method therefor. The superconducting magnetic flux storage unit comprises a storage loop, an addressing circuit, and a reading circuit. The storage loop comprises a first Josephson junction. The first Josephson junction has a current phase relationship that deviates from a sine function, and a stable magnetic flux storage hysteresis is formed by means of scanning a bias current. The addressing circuit is used to adjust critical current of the first Josephson junction so as to change the magnitude of the magnetic flux storage hysteresis of the storage loop. The reading circuit is used to read the magnetic flux state of the storage loop in situ. The offset between the current phase relationship of the first Josephson junction and the sine function in the storage loop of the present application may be equivalent to the role of the inductance of the storage loop in forming the storage hysteresis. In the foregoing manner, the superconducting magnetic flux storage unit may get rid of the minimum area limitation caused by the loop inductance requirement, so that the area of the superconducting magnetic flux storage unit may be greatly reduced.

IPC Classes  ?

• G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers

Abstract

A transverse miniature infrared gas sensor, comprising: a miniature optical gas chamber (1), an infrared light source (2), an infrared detector (3), a power supply chip (4), an ASIC chip (5), and a first circuit board (6). A light path of the miniature optical gas chamber (1) is of a transverse folding reflection structure, and the light path is parallel to the first circuit board (6). The miniature optical gas chamber (1) comprises a light input end and a light output end; the infrared light source (2) is connected to the light input end, and the infrared detector (3) is connected to the light output end. The infrared detector (3) and the infrared light source (2) are perpendicular to the light path; the infrared detector (3) and the infrared light source (2) are provided on the same side of the miniature optical gas chamber (1); the miniature optical gas chamber (1), the infrared light source (2), and the infrared detector (3) are integrated on one surface of the first circuit board (6), and the power supply chip (4) and the ASIC chip (5) are integrated on the other surface of the first circuit board (6); the infrared detector (3) is integrally packaged by using an MEMS packaging technology. System-level hybrid integrated packaging is used, so that the size of the infrared gas sensor can be effectively reduced.

IPC Classes  ?

• G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis

Abstract

The present disclosure provides a method for preparing a multi-layer hexagonal boron nitride film, including: preparing a substrate; preparing a boron-containing solid catalyst, and disposing the boron-containing solid catalyst on the substrate; annealing the boron-containing solid catalyst to melt the boron-containing solid catalyst; feeding a nitrogen-containing gas and a protecting gas to an atmosphere in which the melted boron-containing solid catalyst resides, the nitrogen-containing gas reacts with the boron-containing solid catalyst to form the multi-layer hexagonal boron nitride film on a surface of the substrate. The method for preparing a multi-layer hexagonal boron nitride film can prepare a hexagonal boron nitride film having a lateral size in the order of inches and a thickness from several nanometers to several hundred nanometers on the surface of the substrate, providing a favorable basis for the application of hexagonal boron nitride in the field of two-dimensional material devices.

IPC Classes  ?

• B01J 23/755 - Nickel
• C01B 21/064 - Binary compounds of nitrogen with metals, with silicon, or with boron with boron
• B01J 23/745 - Iron
• C23C 16/34 - Nitrides

Abstract

The present invention relates to a superconducting integrated circuit design method based on different-layer JTL placement and routing. The method comprises the following steps: performing bias coil segmentation processing on a unit data interface of a unit library, and reserving the position of a via hole; performing placement and arrangement on units on a logic unit layer according to a circuit logic schematic diagram; performing clock line connection on each unit by using a JTL and a splitter of the logic unit layer; and performing data connection on each unit by using JTLs which are located on a transverse JTL routing layer and a longitudinal JTL routing layer which are not located on the same layer as the logic unit layer, wherein the JTL on the transverse JTL routing layer serves as a transverse data routing unit between the units, the JTL on the longitudinal JTL routing layer serves as a longitudinal data routing unit between the units, and the connection between the JTL on the upper layer and the position of the unit data interface on the lower layer is realized by means of calling the via hole. According to the present invention, the defect of not facilitating the routing of JTLs is overcome.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/18 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components exhibiting superconductivity

Abstract

The present invention provides a fog computing and blockchain platform-based distributed weather station system, comprising multiple weather stations, multiple fog nodes which are distributed in the same way as the weather stations, and a blockchain platform. Each weather station is in communication connection to only one fog node, each fog node is in communication connection to multiple weather stations located in the communication range of the fog node and serves as a routing and storage node of the weather stations, each fog node is in communication connection to the blockchain platform, and the blockchain platform provides a query interface for a user. The present invention further provides an operating method for the system. According to the distributed weather station system in the present invention, the fog nodes are used as routing and storage nodes of multiple weather stations, so that the data storage capacity of the weather stations is enhanced; moreover, a blockchain platform is used, widely distributed weather stations are integrated and a service platform is provided, so that any user can purchase weather station service by means of the platform.

IPC Classes  ?

• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

Abstract

The present invention provides a calibration and depth image processing method for a multinocular stereo camera, comprising: selecting a reference camera and a to-be-corrected camera from a multinocular camera device, and obtaining corresponding reference camera image and to-be-corrected camera image; optimizing internal parameters and external parameters of the to-be-corrected camera according to the reference camera image and the to-be-corrected camera image; and obtaining a final depth image. According to the method of the present invention, camera parameters are optimized using a depth calculation result of matching features, so that the transition of boundary portions of a plurality of depth images is smooth, the depth images of the non-overlapped portions can be further refined and adjusted according to the optimized parameters, and the consistency and stability of final depth results are ensured by means of mutual constraint between different binocular cameras.

IPC Classes  ?

• G06T 7/50 - Depth or shape recovery
• G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration

Abstract

An apparatus and a method for using light to adjust the sensitivity of a silicon nanowire sensor. The apparatus comprising a silicon nanowire sensor used to output a sensitive signal for sensing a target object and to convert the sensitive signal into an electrical signal; a light source used to supply the silicon nanowire sensor with a preset illumination intensity; and an optical power regulator used to regulate the preset illumination intensity and a signal processor for performing signal processing and feedback. In the present apparatus, by means of arranging a power-adjustable light source at the top of a silicon nanowire sensor and changing the illumination conditions surrounding same, a function of adjusting the sensitivity thereof is implemented. In the present method, the varying response sensitivity of a silicon nanowire sensor under different illumination intensities is utilized, and the sensitivity of the sensor is adjusted by means of setting an appropriate illumination condition. The present invention features a simple structure, convenient operation, and no device wear, and is able to implement quick and effective adjustment of the sensitivity of silicon nanowire sensors.

IPC Classes  ?

• G01N 21/17 - Systems in which incident light is modified in accordance with the properties of the material investigated
• G01N 27/00 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
• B82Y 15/00 - Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors

Abstract

A method for using light to calibrate a silicon nanowire sensor, comprising: surface modifying a silicon nanowire sensor (S100); acquiring light response currents of the surface-modified silicon nanowire sensor under different illumination intensities in a preset measurement environment (S102); on the basis of the light response currents, determining a light response function analytic expression of a light response function expression (S104); on the basis of the light response function analytic expression and an environmental variable offset value, determining a target object response function analytic expression of a target object response function expression (S106); and on the basis of the target object response function analytic expression, determining the concentration of a sample to be measured corresponding to the response current of the sample to be measured (S108). The absorption efficiency of a silicon nanowire is used to evaluate the performance of a silicon nanowire sensor, solving the problem of inconsistent sensor response efficiency caused by differences in sensing units. The method features the strengths of being simple, efficient, low-cost, having no device wear, and not interfering with subsequent device use.

IPC Classes  ?

• G01N 21/17 - Systems in which incident light is modified in accordance with the properties of the material investigated
• G01N 27/00 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
• B82Y 15/00 - Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors

Abstract

A method and an apparatus for using optical modulation to improve the signal-to-noise ratio in a silicon nanowire sensor. The method comprises: on the basis of a carrier wave signal, determining an optical excitation signal for a silicon nanowire sensor (S101); on the basis of the optical excitation signal, acquiring a modulated signal of the silicon nanowire sensor on an object being sensed (S103); and using a lock-in amplifier to process the carrier wave signal and the modulated signal to obtain a target response signal of the silicon nanowire sensor on the object being sensed (S105). A lock-in amplifier is used to transpose the signal spectrum of a target response signal of a silicon nanowire sensor to the frequency of a carrier wave signal, and then amplification is performed, avoiding interference from noise in the silicon nanowire sensor. The signal-to-noise ratio in the silicon nanowire sensor can thus be improved, enhancing the anti-interference capacity of the sensor.

IPC Classes  ?

• G01N 21/17 - Systems in which incident light is modified in accordance with the properties of the material investigated
• G01N 27/00 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means

Abstract

The present disclosure provides a method for making a single photon detector with a modified superconducting nanowire. The method includes: preparing a substrate; modifying a superconducting nanowire with stress on a surface of the substrate; and fabricating a superconducting nanowire single photon detector based on the superconducting nanowire with stress. Based on the above technical solution, in the superconducting nanowire single photon detector provided by the present disclosure, the device material layer film has a certain thickness, the critical temperature of the device material can be reduced, the uniformity of the device material and small superconducting transition width are ensured, thereby improving the detection efficiency of the device.

IPC Classes  ?

• H01L 39/08 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the shape of the element
• H01L 39/10 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the means for switching
• H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
• H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof

Abstract

A gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. By means of bonding and thinning, an unintentionally doped gallium oxide layer (110) is transferred onto a highly doped and highly thermally conductive heterogeneous substrate (200); and by means of surface treatment and ion implantation performed on the gallium oxide layer (110), a heavily doped gallium oxide layer (120) can be obtained, so as to prepare a gallium oxide semiconductor structure comprising the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence; in a vertical gallium oxide-based power device prepared on the basis of a gallium oxide semiconductor structure, the intermediate layer is the thick gallium oxide layer (110) which has a lower current carrier concentration than the heavily doped gallium oxide layer (120), increasing a breakdown voltage of the device in design, and the highly thermally conductive heterogeneous substrate (200) can improve heat dissipation performance of the device, providing a large current for the device having a Fin structure.

IPC Classes  ?

• H01L 21/34 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies not provided for in groups , , and with or without impurities, e.g. doping materials
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

Disclosed are a compound eye camera device and a compound eye system. The compound eye camera device comprises a plurality of small eyes arranged in a row or column, each of the small eyes comprises an optical element and a corresponding photosensitive unit, each column of the small eyes at least corresponds to a view plane of a column of the small eyes, the view plane of the column of the small eyes passes through the optical center of each small eye of the column of the small eyes and a position near the center of the at least one photosensitive unit of the small eye, each photosensitive unit at least intersects with a view plane of a column of small eyes, the line of sight of each photosensitive unit passes through the center of the photosensitive unit and the optical center of the small eye in which the photosensitive unit is located, and a processor is configured to generate an image on the basis of information received by the photosensitive unit, and to process the image to obtain information regarding a captured object. The compound eye system may comprise the above compound eye camera device. By means of the compound eye camera device, two-dimensional plane or three-dimensional detection can be performed from different directions, and acquisition of accurate two-dimensional and three-dimensional space information is facilitated.

IPC Classes  ?

• H04N 5/225 - Television cameras

Abstract

The present disclosure provides a method and system for improving a counting rate of a superconducting nanowire single photon detector. The method includes: coupling an electrical attenuator in series with an output end of the superconducting nanowire single photon detector; the electrical attenuator includes an input end and an output end, and the input end of the electrical attenuator is coupled with the output end of the superconducting nanowire single photon detector. The present disclosure couples the electrical attenuator in series with the output end of the superconducting nanowire single photon detector. Since the configuration of the electrical attenuator is a resistor network, it can act as a series resistor and can also reduce the response pulse amplitude of the superconducting nanowire single photon detector. The present disclosure can improve the counting rate of the superconducting nanowire single photon detector, while keeping the detection efficiency high.

IPC Classes  ?

• G01J 1/46 - Electric circuits using a capacitor
• G01J 1/04 - Optical or mechanical part
• G01J 1/08 - Arrangements of light sources specially adapted for photometry
• H01L 39/10 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the means for switching
• H01P 3/06 - Coaxial lines
• G01J 1/44 - Electric circuits