Abstract

Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

Abstract

An electronic package and a manufacturing method thereof are provided, in which a wiring structure electrically connected to a photonic structure is disposed on a surface of a part of the photonic structure, an electronic component is disposed on the wiring structure to be electrically connected to the wiring structure, and an optical element is disposed on a surface of another part of the photonic structure to be electrically connected to the photonic structure. Therefore, the photonic structure and the electronic component are placed relatively vertically on opposite sides of the wiring structure, thereby effectively reducing the layout area of the wiring structure to meet the demand for miniaturization.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided, which comprises: a carrier structure; an electronic element disposed on and electrically connected to the carrier structure; a supporting structure disposed on the carrier structure; a semiconductor element disposed on the carrier structure; and an optoelectronic element disposed on, electrically connected to the semiconductor element and partially supported by the supporting structure. By the implementation of the present disclosure, the optoelectronic element in the electronic package and/or the optical fiber connected to the electronic package can obtain a well and firm support, avoiding the breakage of the optoelectronic element and/or the optical fiber, so as to improve the manufacturing yield, the reliability and the service life of the electronic package.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first carrier structure and a second carrier structure with a thickness less than that of the first carrier structure are provided, at least a first electronic component is disposed on the first carrier structure, and at least a second electronic component is disposed on the second carrier structure, wherein the first electronic component and the second electronic component are covered by an encapsulating layer, such that the second electronic component can be disposed on the second carrier structure by using a packaging module to avoid excessive height of the packaging module from occurrence.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

The present disclosure provides a circuit structure having an insulating layer; a plurality of first circuits disposed on one side of the insulating layer; and a plurality of first electrical connection pads, each having a first extension portion extending toward and electrically connected to one end of a first circuit of the first circuits, wherein a width of the extension portion gradually decreases toward a junction of the first extension portion and the first circuit. By implementing of the present disclosure, stress on the junction between the electrical connection pad and the circuit can be dispersed along the extension portion through the arrangement of the extension portion and its tapered width design, thereby preventing fracture on the junction of the electrical connection pad and the circuit due to excessively concentrated stress, so that the manufacturing yield and reliability of semiconductor packages with this circuit structure can be improved.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A test equipment is provided, which includes a cabin for providing a low-temperature testing environment for elements under test, and an air curtain structure surrounding the cabin to send dry air toward the cabin. The air curtain structure includes a ring body and a plurality of openings disposedinside the ring body, so that the ring body can send dry air toward the cabin through the plurality of openings, thereby reducing the ambient humidity and preventing condensation water dripping from causing the test equipment damage.

IPC Classes  ?

• G01N 17/00 - Investigating resistance of materials to the weather, to corrosion or to light
• F24F 9/00 - Use of air currents for screening, e.g. air curtains

Abstract

An electronic package and the manufacturing method thereof are provided. The method includes forming a circuit structure on an encapsulating structure with a recess and a plurality of vias, disposing a plurality of conductive pillars in the plurality of vias to be electrically connected to the circuit structure, and disposing an electronic component in the recess to be electrically connected to the circuit structure. Afterwards, a routing structure is disposed on the encapsulating structure to be electrically connected to the plurality of conductive pillars and the electronic component. Therefore, by disposing the electronic component in the recess, the encapsulating structure covers the electronic component to facilitate dissipation of thermal stress.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package and a manufacturing method thereof are provided, in which a plurality of conductive pillars with detachable blocks and a first electronic component with detachable blocks are provided, and the first electronic component, the plurality of detachable blocks and the plurality of conductive pillars are covered with an encapsulating layer, so that the plurality of detachable blocks are exposed from the surface of the encapsulating layer, and then the plurality of detachable blocks are removed to form a plurality of recesses on the surface of the encapsulating layer, so that the plurality of conductive pillars and the first electronic component are exposed from the recesses. Therefore, through the design of the recesses, the contact area between the circuit portion subsequently formed on the encapsulating layer and the encapsulating layer can be increased, thereby preventing from peeling of the circuit portion during thermal cycles.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a method for fabricating the same are provided. The electronic package includes a cladding layer embedded with a first electronic component and a plurality of conductive pillars; a circuit structure provided on one surface of the cladding layer; a second electronic component disposed on the circuit structure; an insulating layer disposed on another surface of the cladding layer; and a circuit portion disposed on the insulating layer. It can adjust the deformation of the electronic package by changing the diametric sizes of the plurality of conductive pillars.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present disclosure discloses an electronic package and a manufacturing method thereof. An electronic component is disposed on a substrate, an encapsulation layer covers the electronic component, and a frame that is not in contact with the substrate is embedded in the encapsulation layer, thereby preventing the electronic package from warping by the frame resisting thermal stress.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/495 - Lead-frames

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element and a heat dissipation structure covering the electronic element are disposed on a carrier structure, and the electronic element is covered with a cladding layer. The heat dissipation structure has convex portions facing the carrier structure, so that the bonding area between the heat dissipation structure and the cladding layer is increased via the convex portions, thereby preventing the problem of peeling from occurring to the heat dissipation structure.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a passive element and an interposer structure are disposed on a carrier structure, the passive element is encapsulated by an encapsulation layer, and the electronic element is disposed on and electrically connected to the passive element and the interposer structure. Therefore, by the design of the electronic element electrically connecting to the passive element, the power transmission path is shortened and the resistance is reduced, thereby achieving the effect of reducing power loss.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic package and manufacturing method are provided. The electronic package includes a carrier structure and an electronic element. The carrier structure has a first side and a second side opposing the first side and includes at least one insulation layer and at least one circuit layer bonded to the at least one insulation layer. The electronic element is disposed on the first side of the carrier structure. A portion of each of the circuit layers of the carrier structure in a response region below the electronic element is hollowed out to reduce signal interference during high frequency signal transmission and to enhance the reliability of high frequency transmission.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic structure is provided and includes: an electronic body having a first surface and a second surface opposing the first surface; a plurality of conductive bumps disposed on the first surface of the electronic body; a protective layer formed on the first surface of the electronic body and covering the plurality of conductive bumps; and a plurality of grooves formed in the protective layer. A manufacturing method of the electronic structure, and an electronic package and a manufacturing method thereof are further provided.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/498 - Leads on insulating substrates
• H01L 23/528 - Layout of the interconnection structure

Abstract

Provided are a conductive bump and its fabricating method, including: forming a first metal layer, a second metal layer, a barrier metal layer, and a third metal layer on a bonding pad of a semiconductor substrate in sequence. The first metal layer is a copper layer, the second metal layer is a nickel layer, the barrier metal layer is a copper layer, and the third metal layer is a tin-silver alloy layer. The metal migration problem can be prevented by adding the barrier metal layer between the third metal layer and the second metal layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which at least one groove and a plurality of openings are formed on a first side of a carrier member, a plurality of conductive pillars are formed in the plurality of openings, a first electronic element is accommodated in the groove, a plurality of conductive elements are formed on a second side of the carrier member and electrically connected to the plurality of conductive pillars and the first electronic element, and a circuit structure is formed on the first side of the carrier member and electrically connected to the plurality of conductive pillars and the first electronic element. Therefore, a board body made of semiconductor material serves as the carrier member, so that the coefficient of thermal expansion (CTE) of the carrier member matches the CTE of the first electronic element, which is beneficial to dispersing thermal stress.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A heat dissipation structure is provided and includes: bonding portions disposed on electronic elements on an electronic carrier board of a test apparatus; and a board body having a first side and a second side opposing the first side, and the board body is disposed on the bonding portions via the first side and formed with heat transfer members on the second side.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
• G01R 1/04 - HousingsSupporting membersArrangements of terminals

Abstract

An electronic package is provided, in which a package module is disposed on a first surface of a carrier structure, and the package module is covered by a shielding layer, so that the shielding layer is formed on one part of a side surface of the carrier structure without being formed on the other part of the side surface, and thus a second surface of the carrier structure can be used as an antenna transmitting surface and/or an antenna receiving surface to prevent the shielding layer from interfering with the reception and the transmission of the carrier structure.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a substrate structure thereof are provided, in which an electronic element is disposed on the substrate structure having a circuit layer, and an insulating protective layer of the substrate structure has an opening that exposes the circuit layer. A plurality of extension portions protruding toward the inside of the opening and spaced apart are formed on the edge of the opening of the insulating protective layer, so that when an underfill material is filled into a space between the electronic element and the substrate structure, the space between the electronic element and the substrate structure can be evenly filled up to prevent the underfill material from forming voids.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.

IPC Classes  ?

• H01L 23/64 - Impedance arrangements
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H10D 1/20 - Inductors

Abstract

An electrical detection method provides a wiring structure including a base material body and a plurality of contact portions bonded to the base material body. Each of the contact portions includes an electrical detection pad exposed from a surface of the base material body, an electrical auxiliary pad exposed from the surface of the base material body, and a conductor that electrically connects the electrical detection pad and the electrical auxiliary pad. When probes of a detection device are connected to the contact portions, each of the probes exerts a force on the electrical detection pad and the electrical auxiliary pad of each of the contact portions at the same time, so that the contact force between the probes and the contact portions is enhanced to facilitate the electrical testing.

IPC Classes  ?

• G01R 1/073 - Multiple probes
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which a plurality of photonic integrated circuit chips and an auxiliary electronic element are separately configured on a package module to shorten the transmission distance of the optical signal. Therefore, the signal transmission rate of a circuit structure can be increased, thereby improving the overall operating performance of the electronic package.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic module including a carrier structure, at least one first electronic element disposed on a first side of the carrier structure, at least one second electronic element disposed on a second side of the carrier structure, and a plurality of conductive elements is stacked on a substrate via the plurality of conductive elements and a substrate frame, so as to increase an accommodation space between the electronic module and the substrate, thereby preventing the at least one second electronic element of the electronic module from colliding with the substrate.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A wafer dicing method is provided, which includes: using a laser beam to perform a first dicing on a wafer to form a dicing lane on the wafer; using a bevel knife of a dicing machine to perform a second dicing in an inactive area of the wafer, wherein, before the second dicing, the bevel knife is raised to compensate for a thickness difference of the wafer in the inactive area and the dicing lane; and using the bevel knife to perform a third dicing in the dicing lane, wherein, during the third dicing, a wafer cut width of the second dicing is used to activate a Z-axis compensation mechanism of the dicing machine, so that the bevel knife cuts to a predetermined wafer cut width. As such, the applicable dicing lane width range of the bevel knife is increased via the precise control of the wafer cut width.

IPC Classes  ?

• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic structure is tightly bonded to a carrier structure via a bonding layer, and the bonding layer includes a first bonding material and a second bonding material adjacent to the first bonding material, so that the second bonding material can fill in a deformation place of the first bonding material to ensure that no void is formed between the bonding layer and the carrier structure after the bonding layer is bonded to the carrier structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and the electronic element is encapsulated by a heat dissipation covering layer, and the heat dissipation covering layer is in contact with a metal layer formed on a side surface of the carrier structure, so that heat around the electronic element can be dissipated quickly to effectively avoid a problem of failure of the electronic element due to overheating during operation.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a photonic integrated circuit chip and an electronic integrated circuit chip are disposed on opposite sides of an interposer respectively, and the photonic integrated circuit chip and the electronic integrated circuit chip can accomplish signal connection with each other via a plurality of conductive vias in the interposer directly, thereby reducing the power consumption and transmission delay of the signals transmitted between the circuits.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which at least one first electronic element, at least one second electronic element and an optical engine module are all disposed or heterogeneously integrated on a first circuit structure and are electrically connected to the first circuit structure. Furthermore, the first circuit structure is disposed on a carrier structure, so that the first circuit structure and the first electronic element, the second electronic element and the optical engine module on the first circuit structure are carried by the carrier structure, and the first electronic element, the second electronic element and the optical engine module are all electrically connected to the carrier structure via the first circuit structure. Therefore, the electronic package can improve data transmission performance, reduce insertion loss/power loss, or reduce the warpage problem.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A package substrate and a fabricating method thereof are provided, in which a core board body is provided, a first organic conductive layer and a second metal layer are sequentially formed on a first metal layer of the core board body, and portions of the first organic conductive layer and the first metal layer are removed respectively according to a pattern of the second metal layer, such that the second metal layer, or the second metal layer, the first organic conductive layer and the first metal layer are served as a first circuit layer. Therefore, the design of the organic conductive layer can facilitate the control of the side etching amount of the metal circuit during etching, enabling the production of circuit layer with fine line width/fine line pitch.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Abstract

A substrate structure and a manufacturing method thereof are provided, in which a substrate body including a dielectric layer and a circuit layer formed on the dielectric layer is provided with a first insulating layer thereon, and a second insulating layer is further provided on the first insulating layer, and a mark is arranged on the second insulating layer. In this way, the arrangement of the mark will not affect wiring space of the circuit layer of the substrate body, and it will not be interfered by the circuit layer when reading the mark, thereby improving the reading success rate.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An electronic package is provided and includes: a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component, a heat conductor sandwiched between the electronic component and the heat dissipation structure, a first intermetallic compound layer formed between the heat dissipation structure and the heat conductor, and a second intermetallic compound layer formed between the heat conductor and the electronic component. Therefore, stable connections can be formed between the heat dissipation structure, the heat conductor and the electronic component via the first intermetallic compound layer and the second intermetallic compound layer to improve heat dissipation effect.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

An electronic package and a manufacturing method thereof are provided, in which a groove space for accommodating an electronic element is formed on a wiring structure, and an encapsulation layer is formed on the wiring structure to cover the electronic element. Via the design of the groove space, the overall thickness of the electronic package can be easily thinned to meet the demand for miniaturization.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A chip carrier structure is provided and defined with a chip carrier region and a wire bonding region, and the chip carrier structure includes: an insulating layer; a circuit layer formed on the insulating layer; a solder mask layer formed on the insulating layer and the circuit layer and having a plurality of openings in the wire bonding region; and a protective layer formed on a portion of the circuit layer exposed from the solder mask layer, where an area of the protective layer in each of the openings is less than 70000 μm2. By reducing the areas of the circuit layer exposed from the openings and the protective layer exposed from the openings, the problem of delamination caused by poor bonding force between the materials of the protective layer and the circuit layer is greatly reduced, thereby improving the reliability and lifespan of the chip carrier structure.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates

Abstract

A device and method for controlling air purge equipment are provided, which are applicable to controlling an air purge equipment of a testing system. The testing system tests an object to verify the quality thereof. The air purge equipment reduces the internal humidity of the testing system. The device and method for controlling air purge equipment sense a base temperature of the testing system, and sense whether there is a testing element for testing the object in the testing system, and then automatically turn on or turn off the air purge equipment according to the base temperature and the presence of the testing element, so as to avoid that the low temperature causes the moisture to condense into water and consequently affects the testing of the object, and so as to eliminate unnecessary activation of the air purge equipment to avoid accumulating particles or blowing off the object.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

An electronic package is provided and includes a first circuit structure having opposite first and second surfaces; an electronic component set including a first electronic component and a second electronic component and having opposite first and second sides, wherein the first electronic component is located on the first side and has opposite first active surface and first inactive surface, the second electronic component has opposite second active surface and second inactive surface, and a part of the second active surface protrudes and is exposed from an outside of the first electronic component to electrically connect to the first surface; and an encapsulating layer defining opposite first encapsulating surface and second encapsulating surface, wherein the second encapsulating surface is connected to the first surface. As such, the overall height of the electronic package can be reduced and the heat dissipation efficiency of the electronic package can be improved also.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first optoelectronic element having a first optical fiber connection portion is disposed on an electronic module, a second optoelectronic element having a second optical fiber connection portion is disposed on a first level layer of a lower carrying portion of a step-shaped carrier structure, and the electronic module is disposed on a second level layer of the step-shaped carrier structure and the second optoelectronic element having the second optical fiber connection portion, so that the electronic module is electrically connected to the second optoelectronic element having the second optical fiber connection portion. Thereby, two optoelectronic elements having optical fiber connection portions can be easily and vertically integrated, and the second optoelectronic element can be stably carried by the step-shaped carrier structure.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first barrier body and a second barrier body are disposed respectively, and a heat dissipation structure is formed with a hole thereon. Thereby, gas in the heat dissipation structure can be discharged via the hole, so as to prevent the gas from remaining in a thermal conductive layer and affecting the heat dissipation effect.

IPC Classes  ?

• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic component is disposed on a substrate and covered with an encapsulation layer, and a frame body is embedded in the encapsulation layer and protrudes from the substrate. Therefore, the frame body can disperse thermal stress, thereby preventing warping from occurring to the electronic package.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element stacking structure is disposed on a carrier structure to integrate multiple chips into a single package, so that the electronic package can meet with the requirements of miniaturization without increasing the layout area of the carrier structure.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 23/498 - Leads on insulating substrates
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H05K 1/02 - Printed circuits Details

Abstract

An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a heat dissipation structure thereof are provided, in which a supporting member of the heat dissipation structure is disposed around an outer periphery of a central area and has grooves at corner areas. In this way, the grooves can avoid stress concentration in the corner areas, and the rest of the supporting member can well connect and fix the heat dissipation structure and a carrying structure, so as to suppress warpage of the entire electronic package and prevent delamination.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic module including a bridging component and an electronic component is partially arranged on a carrying structure and partially protrudes outside the carrying structure, and a photonic component is electrically connected to the protruding part of the electronic module. With this configuration, the layout area of the carrying structure can be reduced to meet the requirement of miniaturization.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided, in which a supporting structure having a supporting body is disposed on a carrying structure and is in contact with or in proximity to an electronic component, and a barrier structure is disposed on the supporting body, such that the electronic component is exposed from an opening of the barrier structure. Furthermore, a thermal conduction layer is formed on the electronic component exposed from the opening of the barrier structure, and the barrier structure blocks or surrounds the thermal conduction layer on the electronic component, thereby preventing the thermal conduction layer from overflowing.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A packaging structure is provided and includes: an electronic module; an encapsulation layer having a first surface and a second surface opposing the first surface and covering the electronic module; a protecting layer formed on the second surface of the encapsulation layer; and a heat conduction layer formed on the protecting layer. An electronic package including the packaging structure and methods for manufacturing the packaging structure and the electronic package are further provided.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

IPC Classes  ?

• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic component and a heat dissipation structure having an opening are arranged on a carrier structure, a heat sink is arranged in the opening and bonded to the electronic component, and the electronic component, the heat dissipation structure and the heat sink are covered with an encapsulation layer, such that the heat sink can be arranged according to a heat source of a specific part of the electronic component so as to effectively dissipate heat.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

An electronic package is provided, and the manufacturing method of which is to form a plurality of conductive pillars and dispose an electronic element on a first circuit structure, then cover the plurality of conductive pillars and the electronic element with a cladding layer, and then form a second circuit structure on the cladding layer, so that the plurality of conductive pillars are electrically connected to the first circuit structure and the second circuit structure, and the electronic element is electrically connected to the first circuit structure, where a fan-out redistribution layer is configured in the first circuit structure and the second circuit structure, and at least one ground layer is configured in the second circuit structure. Further, the ground layer includes a plurality of sheet bodies arranged in an array, so that at least one slot is disposed between every two adjacent sheet bodies.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass

Abstract

A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, then a cladding layer is formed to cover the electronic element, and a shielding layer is formed on the cladding layer to cover the electronic element. The cladding layer is bonded to a shielding structure, and the shielding structure is located between the shielding layer and the electronic element, so as to prevent the electronic element from being subjected to external electromagnetic interference via multiple shielding mechanisms of the shielding structure and the shielding layer.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package is provided and includes a protection layer formed on the electronic structure having a plurality of conductors to cover the plurality of conductors, a dielectric layer having a plurality of grooves to enable the electronic structure to be bonded onto one side of the dielectric layer with the protection layer thereon such that each of the plurality of conductors is correspondingly accommodated in each of the plurality of grooves, and a plurality of conductive components disposed on another side of the dielectric layer. Accordingly, the design of the grooves is used to correspond to the high and low surfaces of the electronic structure such that the problem of poor manufacturing process can be avoided.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

An electronic package is provided, in which an electronic element and a heat dissipation member are disposed on different areas of a carrier structure having a heat dissipation layer, where the electronic element is covered by an encapsulation layer, and the heat dissipation member is thermally connected to the electronic element via the heat dissipation layer, so that the heat energy generated by the electronic element can be prevented from conducting into the encapsulation layer during the heat dissipation process, such that the problem of overheating around the electronic element can be avoided.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, a heat conduction layer is formed on the electronic element, and a heat dissipation member having a recess portion is disposed on the heat conduction layer to cover the electronic element. Therefore, the arrangement of the recess portion can buffer the flow of the heat conduction layer to facilitate the formation of an intermetallic structure with sufficient thickness between the heat dissipation member and the electronic element, and the heat dissipation effect of the electronic element can meet expectations.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A carrier structure is provided, in which a ground layer is formed on a dielectric body, a circuit layer is formed in the dielectric body, and a conductive via is formed in the dielectric body and electrically connected to the circuit layer and the ground layer, where the ground layer has at least one first groove that exposes a surface of the dielectric body, so that the noise of the circuit layer is easy to spread out of the dielectric body, so as to prevent the problem of crosstalk from occurring in the circuit layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

An electronic package and a carrier structure thereof are provided, in which the carrier structure is used for disposing a semiconductor chip and defined with a die placement area and a peripheral area adjacent to the die placement area on a surface thereof, and a winding shape of conductive traces arranged at a boundary between the die placement area and the peripheral area is a continuous bending shape with notches to facilitate dispersion of thermal stress, thereby preventing the problem of breakage from occurring to line segments of the conductive traces.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates

Abstract

An inductor module is provided, in which a first coil and a second coil surrounding an outer circumference of the first coil are formed on a carrier structure to generate magnetic flux. The first coil includes a first conductive layer bonded to the carrier structure, and a plurality of first wires arranged on the carrier structure and connected to the first conductive layer. The second coil includes a second conductive layer bonded to the carrier structure, a plurality of conductive pillars embedded in the carrier structure and connected to the second conductive layer, and a plurality of second wires arranged on the carrier structure and connected to the conductive pillars. The first conductive layer and the second conductive layer are arranged at intervals in different layers of the carrier structure.

IPC Classes  ?

• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• H01F 17/00 - Fixed inductances of the signal type
• H01F 27/02 - Casings
• H01F 27/28 - CoilsWindingsConductive connections

Abstract

An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

An electronic package and a manufacturing method thereof are provided, in which a dam is surrounding an electronic component on a carrier structure, the electronic component is encapsulated by a thermal conduction layer, and the electronic component, the dam and the thermal conduction layer are covered by a heat sink, such that the dam strongly supports the heat sink to effectively disperse the thermal stress, so as to effectively control the warpage of the heat sink to prevent the problem of delamination from occurring between the heat sink and the thermal conduction layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure with a circuit layer, a first encapsulating layer and a second encapsulating layer are formed on the carrier structure to cover the electronic element, a first antenna layer is formed on the first encapsulating layer, and a second antenna layer communicatively connected to the first antenna layer is formed on the second encapsulating layer. Therefore, the thickness of the first encapsulating layer is used to control the resonance distance of the antenna frequency so as to generate better resonance effect, and the distance between the first antenna layer and the second antenna layer is controlled by the thickness of the second encapsulating layer to increase the bandwidth of the antenna.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a manufacturing method thereof are provided, in which support members are disposed on a carrier structure having a plurality of electrical contact pads, and a conductive element is bonded on each of the electrical contact pads, and an electronic module is disposed on the carrier structure via the conductive elements, so that the support members contact and support the electronic module to prevent the electronic module from warping.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Abstract

An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

Abstract

An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 21/8254 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using II-VI technology
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a substrate structure thereof are provided, in which an electronic element and a flow stopper surrounding the electronic element are disposed on a substrate body of the substrate structure, and a heat dissipation structure is bonded on the electronic element via a heat dissipation material, so that the flow stopper limits an overflow range of the heat dissipation material to prevent the heat dissipation material from contaminating a circuit layer on the substrate body.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An antenna module is provided with a plurality of antenna structures and a shielding structure arranged on a plate body, and the shielding structure is located between two adjacent antenna structures, where the shielding structure includes a concave portion formed on the plate body and a dielectric material formed between the concave portion and the antenna structure to generate different impedance characteristics, thereby improving the antenna isolation.

IPC Classes  ?

• H01Q 1/48 - Earthing meansEarth screensCounterpoises
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01Q 1/50 - Structural association of antennas with earthing switches, lead-in devices or lightning protectors

Abstract

An electronic package and a substrate structure thereof are provided, in which a circuit layer and a filling layer are formed on a substrate body in the substrate structure, where the circuit layer has a plurality of conductive traces separated from each other, so that the filling layer is filled between the plurality of conductive traces, and a portion of a surface of the circuit layer and a surface of the filling layer are covered with an insulating protective layer. Therefore, the insulating protective layer is carried by the filling layer, so that the insulating protective layer can be thin, thereby preventing the phenomenon of copper migration from occurring to the substrate structure in subsequent processes.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package and a manufacturing method thereof are provided, in which a plurality of electronic components and a shielding part are disposed on a carrier structure, the shielding part is located between two of the electronic components, and the plurality of electronic components and the shielding part are covered by an encapsulating layer, where a surface of the shielding part has a protruding portion. Therefore, a periphery surface of the shielding part is a non-straight surface, so as to prevent the reflection of electromagnetic waves in the encapsulating layer from interfering with the signal transmission of the electronic components.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/495 - Lead-frames
• H01L 23/498 - Leads on insulating substrates
• H01L 23/66 - High-frequency adaptations

Abstract

An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.

IPC Classes  ?

• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

IPC Classes  ?

• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/66 - High-frequency adaptations
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

IPC Classes  ?

• H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic structure and a wall structure surrounding the electronic structure are disposed on a carrier structure, a heat conducting layer is formed on the electronic structure, and the wall structure and the heat conducting layer are covered by a heat dissipation element. Therefore, a thermal stress can be effectively dispersed by the arrangement of the wall structure, such that a warpage of the electronic structure and a heat dissipation body can be effectively controlled.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a cover is disposed on a carrier structure having an electronic element, and the electronic element is covered by the cover. A magnetic conductive member is arranged between the cover and the electronic element, and an air gap is formed between the magnetic conductive member and the cover to enhance the shielding effect of the electronic package.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

An electronic package and a manufacturing method thereof are provided, in which a magnetically permeable member and a plurality of supporting members having conductive through vias are disposed on a carrier structure having a circuit layer, the magnetically permeable member is located between two supporting members, and a conductive member is disposed on the supporting members to cover the magnetically permeable member, so that the circuit layer, the conductive through vias and the conductive member form a coil surrounding the magnetically permeable member to increase the inductance.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package, a packaging substrate and a fabricating method are provided, in which a conductive bump pad is formed on an electrical contact pad of the packaging substrate, so that when an electronic element is bonded to the packaging substrate via a solder material in a flip-chip process, the conductive bump pad can guide the flow of the solder material. Therefore, the problem of empty soldering caused by the solder material not effectively contacting with the electrical contact pad can be avoided.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is pasted on a routing layer that is configured with a plurality of conductive pillars, then the electronic element, the conductive pillars and the routing layer are covered with a cladding layer, and a circuit structure electrically connected to the electronic element and the conductive pillars is formed on the cladding layer. Therefore, the conductive pillars can be directly formed on the routing layer and the dielectric layer is omitted, so there is no need to consider the thickness of the dielectric layer, so as to facilitate the thinning of the electronic package.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in an encapsulation layer, and a circuit structure is disposed on the encapsulation layer and electrically connected to the first electronic element and the second electronic element. The circuit structure has a hollow area corresponding to the first electronic element, and a heat dissipation structure is disposed in the hollow area to thermally connect the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation structure, so as to avoid the problem of affecting the operation of the second electronic element due to the overheating of the encapsulation layer.

IPC Classes  ?

• H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in a packaging layer, and a circuit structure is formed on the packaging layer and electrically connected to the first electronic element and the second electronic element, where the circuit structure has a heat dissipation portion thermally connected to the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation portion, so as to avoid the problem of affecting the operation of the second electronic element due to overheating of the packaging layer.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic package and the manufacturing method thereof are provided, in which a photonic element and an electronic element are embedded in an encapsulation layer, and the photonic element has an external contact area exposed from the encapsulation layer, such that signals of the electronic element can be directly transmitted to an optical fiber via the external contact area of the photonic element to achieve the purpose of photoelectric integration.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A carrier substrate is provided and has a first circuit structure and a second circuit structure on opposing sides of the carrier substrate, where on one routing region, a difference between a routing ratio of a first circuit layer of the first circuit structure and a routing ratio of a second circuit layer of the second circuit structure is within 10%. Therefore, the difference between the routing ratios of the two opposing outermost circuit layers of the carrier substrate in specific target regions can be reduced, so as to avoid a warpage of the carrier substrate due to a great difference in metal distribution areas.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A working system for a semiconductor packaging process includes a machine equipment and a supply unit correspondingly connected to the machine equipment, and the supply unit includes an input device, an output device and a pick-and-place device for inputting a magazine to the input device and/or outputting the magazine from the output device, so that the magazine is automatically transported to the input device or away from the output device by the pick-and-place device, thereby accelerating the operation speed of the production line.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

Abstract

An electronic package and the manufacturing method thereof are provided, in which a first electronic element and a second electronic element are disposed on a carrier structure, and the first electronic element and the second electronic element are electrically connected to each other by a wire. Therefore, by replacing some layers of the circuit layer of the carrier structure with the wire, the carrier structure can satisfy the functional signal transmission of the first and second electronic elements without configuring too many circuit layers, so as to shorten the process steps and time of the carrier structure, thereby effectively reducing the manufacturing cost of the electronic package.

IPC Classes  ?

• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A working system for a semiconductor packaging process includes a machine equipment, a supply unit and a return device. The supply unit is correspondingly connected to the machine equipment and includes an input device and an output device. The return device is connected to the input device and the output device. As such, a magazine is transferred from the input device to the output device via the return device, thereby accelerating the operation speed of a production line.

IPC Classes  ?

• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

Abstract

An electronic structure is provided, in which a plurality of conductors are disposed on one surface of an electronic body, an epoxy molding compound is used as a protective layer to encapsulate the plurality of conductors, a circuit portion is bonded onto the other surface of the electronic body, and a plurality of external bumps and solder material are formed on the circuit portion. Therefore, with the design of the protective layer, heat energy can be effectively transferred from the protective layer to the solder material below during a process of heating the electronic structure so as to avoid a problem of non-wetting of the solder material.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An electronic package is provided, in which a first electronic module and a second electronic module are stacked via a plurality of first conductive structures and a plurality of second conductive structures, and the amount of solder of the first conductive structures is greater than the amount of solder of the second conductive structures, such that the electronic package can be configured with the first conductive structures and the second conductive structures according to the degree of warpage of the electronic package, so as to effectively disperse the stress to avoid the problem of warpage.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits