The invention relates to a carrier (1) for a composite substrate (S). The carrier comprises a base substrate and a trapping layer (3a) made of polycrystalline silicon arranged on the base substrate (2). The trapping layer has electric traps of a first type having an activation energy of 0.383 eV within a tolerance of 0.008 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2. The trapping layer has electrical traps of a second type having an activation energy of 0.428 eV within a tolerance of 0.016 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2.
H01L 21/66 - Testing or measuring during manufacture or treatment
2.
METHOD FOR MANUFACTURING A HOMOEPITAXIAL SILICON CARBIDE LAYER, MAKING IT POSSIBLE TO LIMIT THE FORMATION OF BPD-TYPE DEFECTS, AND ASSOCIATED COMPOSITE STRUCTURE
The invention relates to a method for manufacturing an active layer of monocrystalline silicon carbide by homoepitaxy on a composite structure, the method comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide extending in a main plane and arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a first thickness along an axis normal to the main plane; 2) forming a local barrier in or on the growth layer, the local barrier extending at a distance from and along the peripheral perimeter, and corresponding to a physical discontinuity of the growth layer chosen from: - a proeminent relief induced by the presence of a material on the growth layer, said material being different from that of the growth layer, - a recessed relief corresponding to an etched region of the growth layer, or - an amorphous domain or domain of crystallinity different from the rest of the growth layer, the local barrier having a thickness, along the axis normal to the main plane, less than the first thickness; 3) epitaxial growth of the active layer on the growth layer.
moynuumoynuuu) are determined, prior to carrying out steps b), c) and d), on the basis of a model that relates them to an etched mean thickness of the surface layer and to a mean etching non-uniformity defined by the difference between an etched mean thickness in a central region and in a peripheral region of the surface layer.
The invention relates to a substrate and the production method therefor for producing a bidirectional switch, the method comprising: - transferring, to the front face of a carrier substrate, a first seed layer (21) made of a wide-bandgap polar semiconductor material; - transferring, to the rear face of the carrier substrate, a second seed layer (22) made of the wide-bandgap polar semiconductor material, wherein these transfers are carried out so as to expose a surface of a first type (F1) of the first seed layer (21) and a surface of the first type (F1) of the second seed layer (22), and wherein a surface of a second type (F2) of the first seed layer (21) and a surface of the second type (F2) of the second seed layer (22) are at the interface with the front face and the rear face of the support substrate, respectively.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A method is used to fabricate a double semiconductor-on-insulator structure comprising, from a back side to a front side of the structure: a handle substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. The method comprises:—a first step of formation of an oxide layer on the front and back sides of the handle substrate, to form the first electrically insulating layer and an oxide layer on the back side of the handle substrate, —a first step of layer transfer, to transfer the first single-crystal semiconductor layer, —a second step of formation of an oxide layer, to form the second electrically insulating layer, and —a second step of layer transfer, to transfer the second single-crystal semiconductor layer.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
6.
COMPOSITE STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a composite structure including a thin layer of a first monocrystalline material arranged on a carrier substrate, the method including: providing an initial substrate of a second polycrystalline material; and depositing, by spin coating, at least on one front surface of the initial substrate, a layer of polymer resin including preformed 3D carbon-carbon bonds; performing a first annealing step at a temperature between 120° C. and 180° C. on the initial substrate provided with the polymer resin layer, to form a layer of cross-linked polymer resin; and performing a second annealing step at a temperature greater than 600° C., in a neutral atmosphere, to convert the layer of cross-linked polymer resin into a glassy carbon film. a composite structure includes a thin layer of a first monocrystalline material on a carrier substrate, which includes a glassy carbon film on an initial substrate of a second polycrystalline.
A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate.
A method for fabricating a double semiconductor-on-insulator structure comprising the steps of: providing a first donor substrate and a handle substrate, forming a weakened zone in the donor substrate so as to delimit a first semiconductor layer to be transferred, bonding the first donor substrate to the handle substrate, a first electrically insulating layer being at the interface, and detaching at the weakened zone, treating the surface of the first transferred semiconductor layer comprising: a rapid thermal annealing, a thermal oxidation followed by a deoxidation, a smoothing heat treatment at a temperature of above 1000° C. in a non-oxidizing atmosphere, chemical-mechanical polishing, providing a second donor substrate of a second semiconductor layer to be transferred, transferring the second semiconductor layer, a second electrically insulating layer being at the interface.
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
SOITEC (France)
Inventor
Mazen, Frédéric
Rieutord, François
Tardif, Samuel
Landru, Didier
Kononchuk, Oleg
Ben Mohamed, Nadia
Abstract
A method and device for monitoring the weakening of an interface between a layer and a substrate while a weakening anneal is being carried out. The method includes illuminating the first face of the substrate layer assembly with a monochromatic light beam in a first direction; measuring the intensity of the light beam scattered by the substrate layer assembly in at least a second direction, the second direction forming a non-zero angle with the first direction; and determining a state of weakening of the interface from the intensity.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
10.
METHOD FOR MANUFACTURING A NON-DEFORMABLE P-SIC WAFER
A method of manufacturing a polycrystalline silicon carbide wafer includes the following stages: heat treatment of a polycrystalline silicon carbide slab; thinning of the polycrystalline silicon carbide slab, the thinning comprising a correction, by withdrawal of material from the polycrystalline silicon carbide slab, of a deformation brought about by the heat treatment.
The present invention relates to a method for producing a composite structure, the method comprising: (a) forming a temporary substrate (3') comprising a carrier substrate (3), wherein a plurality of tile portions (P'1-P'3) or a layer of interest (20) made of a first material are arranged on the carrier substrate (3); (b) forming a removable interface (5) arranged between the carrier substrate (3) and the tile portions or the layer of interest, or in or on the tile portions or the layer of interest; (c) assembling the temporary substrate (3') with a receiver substrate (4) made of a second material that is different from the first material, via the tile portions or the layer of interest; and (d) removing the carrier substrate (3) by dismantling the removable interface (5) so as to transfer at least one portion of the tile portions (P'1-P'3) or of the layer of interest (20) to the receiver substrate (4) to form the composite structure.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Gaudin, Gweltaz
Allibert, Frédéric
Rouchier, Séverin
Bethoux, Jean-Marc
Widiez, Julie
Gelineau, Guillaume
Abstract
22111211 = 2.85×1018cm-322 = 5.40×1020cm-3, - an interface zone, between the carrier substrate and the working layer, comprising nodules and regions of direct contact between the working layer and the carrier substrate, the nodules comprising a metal or semiconductor material other than silicon carbide, the interface zone having an average resistivity of less than or equal to 0.01 mohm.cm2, a dopant concentration profile along a thickness of the semiconductor structure: - being in the form of a step, and - being devoid of a doping peak in the interface zone, or - exhibiting a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration to within plus or minus 10%. The invention also relates to a process for fabricating such a semiconductor structure.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
The present invention relates to an elastic wave device comprising a piezoelectric material (3) with first domains (3a1, 3a2) of a first polarization direction (13a) and second domains (3b1, 3b2) with a second polarization direction (13b), the first direction being opposite to the second direction, in which the first and second domains are periodically alternated along a direction, called periodic direction, perpendicular to the surface normal of the piezoelectric material, and a pair of interdigitated comb electrodes (15a, 15b), the respective comb teeth (17a1, 17a2, 17b1, 17b2) of which extend mainly in the periodic direction, and to a method for manufacturing such an elastic wave device.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
A method of manufacturing a structure comprising at least two tiles on a substrate comprises: —placing, on a support substrate, at least two tiles, the tiles being arranged on the support substrate in an incorrect distribution and/or geometry compared with a target distribution and/or geometry; —forming a mask comprising a protective film partially covering the tiles in a pattern defining the target distribution and/or geometry and at least one opening extending around the protective film; and —etching at least one tile through the opening in the mask so as to correct the arrangement of the tiles according to the target distribution and/or geometry.
A method for transferring a piezoelectric layer onto a support substrate comprises:—providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate,—forming a weakened zone in the piezoelectric substrate so as to delimit the piezoelectric layer to be transferred,—providing the support substrate,—forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate,—bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and-fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.
H10N 30/057 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by stacking bulk piezoelectric or electrostrictive bodies and electrodes
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
17.
DEVICE ARCHITECTURES WITH TENSILE AND COMPRESSIVE STRAINED SUBSTRATES
A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
The invention relates to a front-side imager comprising in succession: a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises, between the carrier substrate and the first electrically insulating layer: a second electrically insulating separating layer, and a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR STRUCTURE COMPRISING A POLYCRYSTALLINE SILICON CARBIDE SUBSTRATE AND AN ACTIVE LAYER OF SINGLE-CRYSTAL SILICON CARBIDE
A method of manufacturing a semiconductor structure, which includes a support substrate of polycrystalline silicon carbide and an active layer of single-crystal silicon carbide, involves:
the formation of a support substrate including a stack of a first layer of polycrystalline SiC mainly of polytype 3C and of a second layer of polycrystalline SiC mainly of polytype 4H and/or 6H,
the bonding of a donor substrate including an active layer of single-crystal SiC of polytype 4H or 6H to a face of polytype 4H and/or 6H of the support substrate, and
the transfer of the active layer onto the support substrate.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
20.
SURFACE ELASTIC WAVE FILTER WITH RESONANT CAVITIES
A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.
A semiconductor structure includes a Silicon-On-Insulator substrate and an epitaxial III-N semiconductor layer stack on top of the Silicon-On-Insulator substrate. The Silicon-On-Insulator substrate has a silicon base layer, an intermediate layer on top of the base layer, and a n-type doped silicon top layer on top of the intermediate layer. The intermediate layer includes a trap-rich layer and a buried insulator on top of a trap-rich layer. The epitaxial III-N semiconductor layer stack, which is on top of the Silicon-On-Insulator substrate, includes a first active III-N layer and a second active III-N layer on top of the first active III-N layer. A two-dimensional Electron Gas is located between the first active III-N layer and the second active III-N layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
SOITEC (France)
Inventor
Salvetat, Thierry
Berre, Guillaume
Darras, François- Xavier
Abstract
A method for manufacturing disassemblable substrates, comprising: (a) providing a first substrate comprising implanted species forming a flat implantation zone and a proximal surface; a second substrate comprising a surface; (b) forming a series of cavities on the proximal surface of the first substrate and/or on the surface of the second substrate; (c) assembling the first and second substrates (1, 2) by direct bonding; and (d) applying a heat treatment to weaken the flat implantation zone. Further, the series of cavities being arranged in such a way as to allow direct bonding between the first and second substrates during step (c); and prevent thermal initiation of the splitting of the weakened flat implantation zone at the end of step (d).
A method for fabricating a donor substrate comprises the steps of A: providing a handle substrate, B: providing a target substrate, C: attaching the target substrate to the handle substrate, and D: rectifying, in particular, by grinding, the target substrate attached to the handle substrate, so as to form the donor substrate, the method being characterized in that a waiting time period of a predetermined duration is observed between step C and step D.
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Ben Mohamed, Nadia
Acosta-Alba, Pablo-Edouardo
Broekaart, Marcel
Colas, Franck
Kononchuk, Oleg
Landru, Didier
Larrey, Vincent
Mazen, Frédéric
Abstract
The invention relates to a process for transferring a thin layer to a carrier substrate, comprising: - joining a donor substrate (1) and the carrier substrate (2) by direct bonding of their respective front sides (1a, 2a) via a bonding interface (3), to form a bonded assembly (100) having an unbonded local region (31) within this bonding interface (3), the donor substrate (1) further comprising a buried fragile plane (11), - splitting along the buried fragile plane (11), the splitting being initiated in the unbonded local region (31) after growth of microcracks in said plane (11) by thermal activation, and leading to the transfer of a thin layer (10) from the donor substrate (1) to the carrier substrate (2). The process is noteworthy in that the unbonded local region (31) is generated by at least one rough region (31a) produced by scanning a laser beam over at least one of the front sides (1a, 2a) of the donor substrate (1) and carrier substrate (2) before they are joined, the scan covering an area of at least 100 microns by 100 microns and of at most 500 microns by 500 microns.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
The invention relates to a method for manufacturing a diamond substrate, or a III-V material substrate, for microelectronic applications, the method comprising: - bonding a plurality of monocrystalline diamond tiles or III-V material tiles (20) onto a carrier substrate (1), each tile being spaced apart from the adjacent tiles so as to expose a lateral surface (S2) of each tile; - epitaxially growing diamond or the III-V material from the lateral surface and the upper surface of each tile until a continuous layer (2) of monocrystalline diamond or III-V material is formed and extends over the plurality of tiles (20); - forming, by implanting atomic species, a weakened zone (21) in the continuous layer (2) of monocrystalline diamond or III-V material to define a surface layer (22) to be transferred; - bonding the continuous layer (2) of monocrystalline diamond or III-V material onto a receiver substrate (3); - detaching the continuous layer (2) of monocrystalline diamond or III-V material along the weakened zone (21) so as to transfer the surface layer (22) of monocrystalline diamond or III-V material onto the receiver substrate (3) to form the diamond or III-V material substrate.
The present disclosure relates to an intermediate substrate (10) for the manufacture of a semiconductor substrate, the intermediate substrate successively comprising: a a first semiconductor layer (2); b a first thermal barrier layer (5); c a support (13) comprising an absorption layer (3) configured to absorb laser radiation in a given wavelength range, the temperature of the absorption layer (3) increasing as it absorbs the laser radiation, and a separation zone (8) adjacent to the absorption layer (3) configured to thermally degrade due to the increase in temperature of the absorption layer, so as to separate at least part of the support (13) from the rest of the intermediate substrate (10).
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
27.
GATE ALL AROUND SEMICONDUCTOR STRUCTURE AND ITS METHOD OF PREPARATION
The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) directly disposed on the support (1a). At least one pFET structure is directly residing on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is directly residing on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and a nFET gate structure encapsulating each channel nanosheet of the second stack.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
METHOD FOR TRANSFERRING BLOCKS FROM A DONOR SUBSTRATE ONTO A RECEIVER SUBSTRATE BY IMPLANTING IONS IN THE DONOR SUBSTRATE THROUGH A MASK, BONDING THE DONOR SUBSTRATE TO THE RECEIVER SUBSTRATE, AND DETACHING THE DONOR
A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
29.
PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTAL MATERIAL
A method for fabricating a structure comprises preparing a first pseudo-substrate, and in-depth weakening the first pseudo-substrate by ion implantation at a certain depth in the first pseudo-substrate. The first pseudo-substrate is prepared by providing a single crystal substrate comprising a piezoelectric material; forming an oxide layer on a surface of the single crystal substrate; and transferring a piezoelectric layer of the single crystal substrate adjacent the oxide layer to a handle substrate to form the first pseudo-substrate. The method further comprises bonding the first pseudo-substrate to a substrate to provide an assembly, and separating the assembly at the ion-implanted depth of the first pseudo-substrate to form the structure and a second pseudo-substrate. The structure comprises at least a portion of the piezoelectric layer of the single crystal substrate on the substrate.
B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties
B32B 9/04 - Layered products essentially comprising a particular substance not covered by groups comprising such substance as the main or only constituent of a layer, next to another layer of a specific substance
C30B 29/68 - Crystals with laminate structure, e.g. "superlattices"
C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
30.
SYSTEM FOR ENCAPSULATING A SURFACE ELASTIC WAVE DEVICE
A compact and robust encapsulation system for protecting a surface wave device comprises a SAW device and a sealing joint, which seals a second substrate to the base substrate of the SAW device so as to form a cavity, and an antenna connection means arranged outside the cavity on the encapsulation system.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
The invention relates to a polycrystalline silicon carbide carrier for a substrate intended to accommodate a power semiconductor device. The carrier has a first face, referred to as the "front face", and a second face, referred to as the "rear face", and comprises a first surface layer arranged directly under the front face and having a resistivity higher than or equal to 1 ohm.cm and a second surface layer arranged directly under the rear face and having a resistivity strictly lower than 1 ohm.cm.
The invention relates to a method for producing a donor substrate (1) for transferring a piezoelectric layer onto a support substrate, which comprises the following successive steps: • (a) providing a piezoelectric substrate (5) and a manipulation substrate (2); • (b) depositing a photo-polymerisable adhesive layer (6) on a main face of the manipulation substrate (2) or the piezoelectric substrate (5); • (c) bonding the piezoelectric substrate (5) with the manipulation substrate (2) via the adhesive layer (6) to form a heterostructure (7); • (d) irradiating the heterostructure (7) with a luminous flux to polymerise the adhesive layer (6); • (e) thermally treating the irradiated heterostructure (7); and • (f) thinning the piezoelectric substrate (5) by its face opposite the manipulation substrate (2), so as to form the donor substrate (1).
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
34.
SEMICONDUCTOR STRUCTURE FOR OPTOELECTRONIC APPLICATIONS
A semiconductor structure for optoelectronic applications; comprises a first layer made of a crystalline semiconductor, the layer being disposed on an intermediate layer including or adjacent to a direct-bonding interface, the intermediate layer being disposed on a second layer made of a crystalline semiconductor material. The intermediate layer is composed of a material that is different from those of the first and second layers, and the attenuation coefficient of which is lower than 100. The refractive index of the intermediate layer differs by less than 0.3 from the refractive index of at least one sub-layer of the first layer adjacent to the intermediate layer, and of at least one sub-layer of the second layer adjacent to the intermediate layer.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
35.
SUBSTRATE COMPRISING A THICK BURIED DIELECTRIC LAYER AND METHOD FOR PREPARING SUCH A SUBSTRATE
The invention relates to a final substrate (S) comprising, consecutively and in contact with one another, an upper layer (5) made of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electrical charge trapping layer (2) and a base substrate (3). The final substrate (S) has a curvature of less than 60 micrometres, preferably less than 40 micrometres. An exposed surface of the upper layer (5) has a roughness of less than 0.3 nm as a root mean square measurement over a field of 30 micrometres by 30 micrometres. The invention also relates to a method for preparing such a substrate.
A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline SiC carrier substrate includes: forming a polycrystalline SiC layer on a donor substrate, at least a surface portion of which is made of single-crystal SiC; before or after forming the polycrystalline SiC layer, implanting ionic species into the surface portion of the donor substrate, so as to form a plane of weakness delimiting a thin single-crystal SiC layer to be transferred; after the implanting of the ionic species and the forming of the polycrystalline SiC layer, bonding the donor substrate and the polycrystalline SiC carrier substrate, the polycrystalline SiC layer being at the bonding interface; and detaching the donor substrate along the plane of weakness, so as to transfer the polycrystalline SiC layer and the thin single-crystal SiC layer onto the polycrystalline SiC carrier substrate.
C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
The invention relates to a process comprising: providing a heterostructure comprising a growth substrate (1), an interlayer (2) of two-dimensional material and an epitaxial semiconductor layer (3); providing a rigid substrate (4) comprising a weakened plane (5); producing a first assembly by bonding the rigid substrate to the heterostructure, the first side (F) and the epitaxial layer (3) being at the bonding interface; splitting the first assembly at the interlayer (2) of two-dimensional material, so as to obtain a second assembly resulting from transfer of the epitaxial layer (3) from the heterostructure to the rigid substrate (4); producing a third assembly by bonding the second assembly to a target substrate (7), the epitaxial layer (3) being at the bonding interface; splitting the third assembly along the weakened plane (5) of the rigid substrate (4).
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
H03H 3/04 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
H10N 30/082 - Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 9/00 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators
COMPOSITE STRUCTURE COMPRISING A USEFUL MONOCRYSTALLINE SIC LAYER ON A POLYCRYSTALLINE SIC CARRIER SUBSTRATE AND METHOD FOR MANUFACTURING SAID STRUCTURE
A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 μm; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 μm; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
41.
STRUCTURE COMPRISING MONOCRYSTALLINE LAYERS OF ALN MATERIAL ON A SUBSTRATE AND SUBSTRATE FOR THE EPITAXIAL GROWTH OF MONOCRYSTALLINE LAYERS OF ALN MATERIAL
A structure comprises a carrier substrate, a plurality of tiles on the carrier substrate, and a plurality of monocrystalline layers of AlN material on the plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material. Each monocrystalline layer of AlN material of the plurality of monocrystalline layers of AlN material is disposed on a respective tile of the plurality of tiles. Also disclosed is substrate for epitaxial growth of monocrystalline layers of AlN material. The substrate comprises a carrier substrate and a plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material.
A method for preparing a support substrate having a charge-trapping layer includes introducing a monocrystalline silicon base substrate into a chamber of deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with a carrier gas, performing the following successive steps:
forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period; and
forming a polycrystalline silicon charge-trapping layer directly on the dielectric layer by introducing a precursor gas containing silicon into the chamber over a second time period, subsequent to the first time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature strictly between 1010° C. and 1200° C.
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
43.
METHOD FOR MANUFACTURING A PLURALITY OF POLYCRYSTALLINE SILICON CARBIDE SUBSTRATES
The invention relates to a method for manufacturing a plurality of polycrystalline silicon carbide substrates (200), the method comprising the following steps: • forming a multilayer structure by alternately depositing a plurality of polycrystalline silicon carbide layers (20, 21, 22, 23, 24) and a plurality of separation layers (30, 31, 32, 33) on at least one face of a temporary support substrate (10); • detaching each polycrystalline silicon carbide layer (20, 21, 22, 23, 24) from the multilayer structure by removing the temporary substrate (10) and each separation layer (30, 31, 32, 33) to form a respective polycrystalline silicon carbide substrate (200).
A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
45.
METHOD FOR FABRICATING A POLYCRYSTALLINE SILICON CARBIDE CARRIER SUBSTRATE
A method of fabricating a polycrystalline silicon carbide carrier substrate involves growing an initial polycrystalline silicon carbide substrate on a seed of graphite or of silicon-carbide. A stiffening carbon film is then formed on a front face of the initial substrate. The initial substrate has, in the plane of its front face, a first average silicon carbide grain size. The seed is then removed, so as to free the back face of the initial substrate, which has, in the plane of its back face, a second average silicon carbide grain size, which is smaller than the first average size. The back face of the initial substrate is then thinned to a thickness for which the initial substrate has, in the plane of its thinned back face, a third average grain size equal to the first average grain size to within ±30%.
The invention relates to a method for preparing a thin single-domain layer (3') made of ferroelectric material, the method comprising, between a step of splitting a donor substrate (1) at a weakened plane (2) in order to form a first layer (3) and a sequence for finishing the first layer (3), the application of a treatment to the free face (8) of the first layer (3) in order to produce a hydrogen concentration of greater than 2.0E21 at/cm^3 in a surface thickness of the first layer (3).
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
47.
METHOD FOR TRANSFERRING A USEFUL LAYER TO A FRONT FACE OF CARRIER SUBSTRATE
A method for transferring a useful layer to a carrier substrate comprises: a) providing a donor substrate including a donor layer; b) forming an embrittlement area by implanting species in the donor layer and defining therewith a useful layer; c) assembling the carrier substrate with the donor substrate; d) a heat treatment step including a first phase and a second phase, wherein the first phase, having a first duration, is heated to a first temperature and is suitable for maturing defects and preventing a fracture from occurring in the embrittlement area, and wherein the second phase, having a second duration, comprises a bearing at a second temperature, below the first temperature, and is suitable for causing a fracture to occur along the embrittlement area.
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
A coupled cavity filter structure that uses a surface acoustic wave, in particular, a guided surface acoustic wave, comprises an acoustic wave propagating substrate, at least one input transducer structure and one output transducer structure, provided over the substrate, each comprising inter-digitated comb electrodes, at least one reflecting structure comprising at least one or more metallic strips positioned at a distance and in between the input and output transducer structures, in the direction of propagation of an acoustic wave. The acoustic wave propagating substrate is a composite substrate comprising a base substrate and a piezoelectric layer. In additional embodiments, a coupled cavity filter structure comprises a groove. In additional embodiments, a SAW ladder filter device comprises at least two coupled cavity filter structures as described herein, wherein the at least two coupled cavity filter structures are positioned on a single line.
The invention relates to a method for producing a substrate (300) comprising a polycrystalline silicon carbide layer (30, 30A, 30B) and a monocrystalline silicon carbide layer (20, 20A, 30B) in direct contact with the polycrystalline silicon carbide layer, said method successively comprising the following steps of: - transferring a first monocrystalline silicon carbide layer (20, 20A) onto a front face of a temporary graphite carrier substrate (10), - depositing polycrystalline silicon carbide on the first monocrystalline silicon carbide layer (20, 20A) to form the polycrystalline silicon carbide layer (30, 30A), - removing the temporary graphite carrier substrate (10).
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Ledoux, Olivier
Laurant, Christine
Darras, François-Xavier
Laurent, Romain
Mehrez, Zouhir
Abstract
The invention relates to a method for transferring a layer onto a carrier substrate, the method comprising: a) a step of forming cavities in a carrier substrate, the cavities opening out via a main face; b) a step of transferring a sealing layer that is intended to seal all of the cavities formed during step a); step a) being carried out such that all of the cavities are distributed regularly over a main region of the main face and such that the main face comprises a peripheral ring free of cavities and inside which the main region is circumscribed, the peripheral ring extending from the edge of the carrier substrate over a length L that is shorter than a predetermined length Lp below which the sealing layer is free of regions that have not been transferred in the peripheral ring.
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Drouin, Alexis
Gaudin, Gweltaz
Rouchier, Séverin
Schwarzenbach, Walter
Widiez, Julie
Rolland, Emmanuel
Abstract
A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
52.
METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A PLURALITY OF BURIED CAVITIES
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Darras, François-Xavier
Mazen, Frédéric
Abstract
The present invention relates to a method for manufacturing a structure comprising a plurality of cavities confined between a thin layer and a carrier substrate, the method comprising the following steps: a) providing a donor substrate and a carrier substrate; b) implanting first light species into the donor substrate to form a uniform buried weakened plane which defines, together with the front face of the donor substrate, the thin layer to be transferred; c) locally implanting second species into the donor substrate so as to introduce these species into the uniform buried weakened plane only at second regions so as to form a functional buried weakened plane having: first regions comprising the first light species and not the second species, and the second regions comprising the first light species and the second species; d) forming a plurality of cavities that open onto a front face of the donor substrate or of the carrier substrate; e) joining, by direct bonding, the donor substrate to the carrier substrate, via their respective front faces, to form a bonded structure in which the cavities are vertically in line with either the first regions or the second regions of the functional buried weakened plane; f) applying a heat treatment to the bonded structure in order to cause spontaneous separation along the functional buried weakened plane and form the structure on the one hand and the rest of the donor substrate on the other hand.
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
54.
HOLDING DEVICE ARRANGEMENT FOR USE IN AN IMPLANTATION PROCESS OF A PIEZOELECTRIC SUBSTRATE
A holding device arrangement for use in an implantation process of a piezoelectric substrate comprises a substrate holding device with an elastic and thermo-conductive layer for receiving a piezoelectric substrate, and means for electrically connecting the surface of the elastic and thermo-conductive layer for receiving the piezoelectric substrate to ground potential. A method for implanting a piezoelectric substrate is performed using such holding device arrangement as described above, and an ion implanter may include such a holding device arrangement.
H01J 37/20 - Means for supporting or positioning the object or the materialMeans for adjusting diaphragms or lenses associated with the support
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
A support for a semiconductor structure comprises a base substrate and a charge trapping layer on the base substrate. The charge trapping layer comprises an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer. The charge trapping material has a grain size between 100 nanometers (nm) and 1000 nm, and/or a lattice parameter greater than a lattice parameter of the at least one interlayer. Also disclosed is a semiconductor structure comprising such support.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
56.
COMPOSITE STRUCTURE COMPRISING A MONOCRYSTALLINE THIN FILM ON A POLYCRYSTALLINE SILICON CARBIDE SUPPORT SUBSTRATE, AND ASSOCIATED PRODUCTION METHOD
422220200400400 is greater than 50%, preferably greater than 80%. The invention also relates to a method for producing such a composite structure. Figure to be published with the abstract: No figure
C23C 16/01 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes on temporary substrates, e.g. on substrates subsequently removed by etching
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
57.
CARRIER COMPRISING A CHARGE-TRAPPING LAYER, COMPOSITE SUBSTRATE COMPRISING SUCH A CARRIER, AND ASSOCIATED PRODUCTION METHOD
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Nouri, Lamia
Veytizou, Christelle
Laurant, Christine
Augendre, Emmanuel
Abstract
A carrier (Sprt) for a composite substrate, the carrier (Sprt) comprising a layer (Trap) for trapping electrical charges, in contact with a base carrier (BSprt), the trapping layer (Trap) comprising a low permittivity layer made of a material having a relative dielectric permittivity lower than silicon dioxide, and the material which has a relative dielectric permittivity lower than silicon dioxide being SiOC or SiOCH.
The present disclosure relates to a method for forming a weakened zone (5) in a semiconductor substrate (6), successively comprising the following steps: a. forming a screen layer (4) having a non-planar controlled profile on a first face (61) of the substrate, b. implanting species through the screen layer and the first face (61) of the substrate to form the weakened zone, the profile of the screen layer being selected to compensate for a non-uniformity in the implantation depth of the species so that the weakened zone (5) is substantially located in a plane parallel to the first face (61).
The present disclosure relates to a method for reducing the boron concentration in a semiconductor layer (12) of a semiconductor-on-insulator substrate (1), the method involving: - at least one heat treatment cycle, each cycle comprising thermal oxidation of the semiconductor layer (12) so as to form an oxide layer (120) on the semiconductor layer (12), wherein, by segregation of the boron, boron atoms from the semiconductor layer (12) diffuse into the oxide layer (120) so as to create a boron concentration deficit in the semiconductor layer (12) at the interface with the oxide layer (120), and - removing the oxide layer (120), wherein the thermal oxidation comprises a temperature increase, under an inert atmosphere, to a temperature above a thermal oxidation target temperature, followed by a temperature decrease to said thermal oxidation target temperature so as to form a temperature gradient in the substrate at which an oxide layer (120) formation rate is higher in the center of the semiconductor layer than at the edge.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
SUBSTRATE-MOUNTED INTEGRATED STRUCTURE, COMPRISING A FERROELECTRIC LAYER WITH SELECTIVE REVERSE POLARIZATION IN THE THICKNESS THEREOF, AND METHOD FOR MANUFACTURING SAME
lay laylay) and the first volume (V1) is disposed between this face of the ferroelectric layer and the second volume (V2); and wherein the second volume (V2) has a hydrogen concentration, known as the polarity reversal concentration, greater than the first volume (V1), and the polarity reversal concentration is between 10 19and 10 22 hydrogen atoms per cubic centimeter.
H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 1019/cm3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 1019/cm3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.
C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
The invention relates to a method for producing a semiconductor substrate having an epitaxially deposited layer, comprising the following successive steps: - etching (ETCH) a susceptor of an epitaxy reactor; - coating (COAT) the susceptor; - placing a semiconductor substrate on the susceptor; - depositing (EPI) an epitaxial layer on the semiconductor substrate. The method also comprises, after coating and before deposition, exposing (ISO) the susceptor to an oxygen-containing gas mixture. The method further comprises, after placement and before deposition, a baking step (BAKE) involving baking the semiconductor substrate, which, except on the underside of the semiconductor substrate, removes an oxide layer formed by exposing the susceptor to an oxygen-containing gas mixture.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
Structure (Struct) comprising a ferroelectric layer (Ferrolay) having a first polarization (P1) in a first area and a second polarization (P2), opposite to the first polarization, in a second area (V) different from the first area, the first polarization and the second polarization being oriented perpendicularly or obliquely to the ferroelectric layer, the second polarization area having a hydrogen concentration greater than the first polarization area, the structure further comprising a support (Sprt) and a dielectric layer (Diel) disposed between this support and the ferroelectric layer.
H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
Commissariat À L'énergie Atomique Et Aux Énergies Alternatives (France)
Soitec (France)
Inventor
Allibert, Frédéric
Landru, Didier
Kononchuk, Oleg
Guiot, Eric
Gaudin, Gweltaz
Widiez, Julie
Fournel, Franck
Abstract
The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 23/00 - Details of semiconductor or other solid state devices
65.
STRUCTURE COMPRISING A SURFACE LAYER TRANSFERRED TO A SUPPORT PROVIDED WITH A CHARGE TRAPPING LAYER WITH LIMITED CONTAMINATION AND METHOD FOR MANUFACTURING SAME
Device comprising a ferroelectric surface layer (20) containing lithium; a dielectric layer (16) comprising an oxide and arranged in contact with the ferroelectric surface layer; and a substrate (10) in contact with the dielectric layer, the substrate comprising a charge trapping layer (14) arranged on a support (12), the charge trapping layer (14) being arranged between the support (12) and the dielectric layer (16), the dielectric layer (16) having a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge trapping layer (14) being such that the charge trapping layer (14) has a lithium content of less than 5x1011at/cm2.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
A surface acoustic wave device comprising a base substrate, a piezoelectric layer and an electrode layer in between the piezoelectric layer and the base substrate, a comb electrode formed on the piezoelectric layer comprising a plurality of electrode means with a pitch p, defined asp=A, with A being the wavelength of the standing acoustic wave generated by applying opposite potentials to the electrode layer and comb electrode, wherein the piezoelectric layer comprises at least one region located in between the electrode means, in which at least one physical parameter is different compared to the region underneath the electrode means or fingers. A method of fabrication for such surface acoustic wave device is also disclosed. The physical parameter may be thickness, elasticity, doping concentration of Ti or number of protons obtained by proton exchange.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
H03H 9/25 - Constructional features of resonators using surface acoustic waves
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
SOITEC (France)
Inventor
Laurant, Christine
Augendre, Emmanuel
Allibert, Frédéric
Veytizou, Christelle
Abstract
The invention relates to a process for manufacturing a multilayer structure, comprising the following steps: - providing a carrier substrate (40) comprising a carrier layer (41) and a porous silicon layer (42); - providing a donor substrate (50) comprising a buried fragile plane (50B) and a surface layer (51); - assembling (S3) the carrier substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being placed in contact with the carrier substrate; - separating the surface layer (51) from the donor substrate (50) via fracture along the buried fragile plane (50B); at least one of the carrier and donor substrates (40, 50), called the degraded substrate, comprises a degraded portion (60) so as to prevent it from bonding to the other of the carrier and donor substrates (50, 40) in the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the edge of said degraded substrate.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
The present disclosure relates to a method for manufacturing an image sensor for detecting visible light and short-wave infrared rays, characterised in that the method comprises the following steps of: a. providing a support substrate (1, 1') comprising a first semiconductor material; b. forming, in the support substrate (1, 1'), cavities (5) in order to define pixels (11, 11') sensitive to visible light in the first semiconductor material between the cavities (5); c. forming an electrically insulating protective layer (4) at least on the lateral surfaces of each pixel (11, 11') sensitive to visible light; growing, in the cavities (5), a second material that is different from the first material, so as to form pixels (12, 12') sensitive to short-wave infrared rays.
A method for manufacturing a substrate for a radiofrequency filter by joining a piezoelectric layer to a carrier substrate via an electrically insulating layer, wherein the method comprises depositing the electrically insulating layer by spin coating an oxide belonging to the family of SOGs (spin-on glasses) on the surface of the piezoelectric layer to be joined to the carrier substrate, followed by an anneal for densifying the electrically insulating layer before joining the piezoelectric layer to the carrier substrate via the electrically insulating layer.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H10N 30/00 - Piezoelectric or electrostrictive devices
H10N 30/05 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
The invention relates to a method for preparing a single-domain thin film (4) of ferroelectric material comprising lithium, the method comprising the provision of a first layer (8) that has a free surface (9). According to the invention, the preparation method comprises a surface treatment that exposes the free face (9) of the first layer (8) to a treatment atmosphere comprising at least 0.02% carbon dioxide in order to form a lithium-rich passivation layer and a treatment for removing the lithium-rich passivation layer.
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
The invention relates to a method for manufacturing two substrates called donor pseudo-substrates (1, 2) each comprising at least two tiles on a carrier substrate, the method comprising the following successive steps: - placing, on a first carrier substrate (3), at least two tiles (P1, P2), each tile having an initial thickness greater than or equal to 300 μm, so as to form a first donor pseudo-substrate (1) comprising the at least two tiles, - bonding said first donor pseudo-substrate (1) onto a second carrier substrate (4) via the tiles (P1, P2), - splitting the tiles into two portions (P'1, P'2, P''1, P''2) of a first thickness (e1) and a second thickness (e2) so as to keep a first portion (P'1, P'2) of said tiles having the first thickness (e1) on the first donor pseudo-substrate and to transfer a second portion (P''1, P''2) of the tiles having the second thickness (e2) onto the second carrier substrate (4) so as to form a second donor pseudo-substrate (2), the second thickness (e2) being between 20% and 80% of the initial thickness of the tiles of the first donor pseudo-substrate.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
73.
METHOD FOR PRODUCING A STRUCTURE COMPRISING AT LEAST TWO TILES ON A SUBSTRATE
The present invention relates to a method for producing a composite structure, the method comprising: (a) forming a temporary substrate (20) comprising an intermediate substrate (2) and a plurality of tiles (P1, P2, P3) of a first material; (b) joining the temporary substrate to a receiver substrate (3) made of a second material, different from the first material, via the tiles; and (c) removing the intermediate substrate (2) in order to transfer at least a portion (P'1, P'2, P'3) of the tiles to the receiver substrate. The receiver substrate comprises a main surface from which cavities (01, 02, 03) extend, the receiver substrate being joined to the temporary substrate on the main surface side such that each tile is received in a respective cavity. Once the intermediate substrate has been removed, the free surface of the tile portions is substantially aligned with the main surface of the receiver substrate.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
74.
METHOD FOR STABILIZING A SURFACE OF A SEMICONDUCTOR MATERIAL
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
Gaudin, Gweltaz
Kononchuk, Oleg
Belhachemi, Djamel
Rolland, Emmanuel
Moulin, Alexandre
Navone, Christelle
Roi, Jérémy
Massy, Damien
Abstract
The invention relates to a method for stabilizing a surface of a semiconductor material, in particular a monocrystalline semiconductor material, against the formation of terraces and/or beads, said method comprising the formation, on said surface, of a vitreous carbon layer (30) in the gaseous phase at a pressure greater than or equal to 80 kPa (800 mbar).
laylay) of boron arsenide BAs having two dimensions each of at least 2 cm in, respectively, two directions normal to each other and within the extension plane.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
76.
METHOD FOR MANUFACTURING A SUBSTRATE FOR AN ELECTRONIC POWER OR RADIOFREQUENCY DEVICE
22) ratio and temperature conditions suitable for forming carbon inclusions (1) in the layer of silicon carbide, and · assembling the support substrate (10) and a surface layer (20) made of a monocrystalline material.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
SOITEC (France)
Inventor
Roumanie, Marilyne
Navone, Christelle
Quenard, Sébastien
Landru, Didier
Veytizou, Christelle
Abstract
A method for producing a multilayer structure includes the following steps: a) providing a first substrate, b) depositing a thick layer of a precursor formulation including a preceramic polymer filled with inorganic particles on the first substrate, c) providing a second substrate, d) adhesively bonding the thick layer and the second substrate, e) thinning the first substrate or the second substrate so as to obtain an active layer, f) applying a pyrolysis heat treatment so as to ceramize the preceramic polymer of the thick layer and to obtain a ceramic matrix composite material, the filler content and the nature of the inorganic particles being chosen so that the thick layer has a coefficient of thermal expansion which differs, at most, by 15% from that of the first substrate and from that of the second substrate.
B32B 37/12 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties
B32B 37/06 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
B32B 37/10 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using direct action of vacuum or fluid pressure
B32B 38/00 - Ancillary operations in connection with laminating processes
The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), the trapping layer being formed of a silicon-rich oxide consisting of silicon at an atomic concentration of between 30% and 77%, of oxygen at an atomic concentration of between 8% and 40% and of nitrogen at an atomic concentration of between 8% and 45%. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing this composite substrate (S).
The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), which trapping layer is made of a silicon-rich oxide that has an atomic concentration of silicon of between 40% and 99.9%. The interlayer also comprises a dielectric layer (3b) in contact with the trapping layer (3a). A transition zone arranged between the trapping layer (3a) and the dielectric layer (3b) has a thickness greater than 50 nm in which the atomic concentration of silicon continuously varies. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing the carrier (1).
A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.
The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), which trapping layer is formed of a silicon-rich oxide consisting of silicon at an atomic concentration of silicon of between 70% and 90% and oxygen at an atomic concentration of between 10% and 30%. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing this composite substrate (S).
A method of transferring a layer from a heterostructure to a receiver substrate comprises the following successive steps: supplying a donor substrate of a first material and a carrier substrate of a second material, bonding the donor substrate to the carrier substrate, thinning the donor substrate, so as to form the heterostructure comprising the thinned donor substrate on the carrier substrate, removing a peripheral portion of the donor substrate, forming a weakened region in the thinned donor substrate so as to delimit a layer of the first material to be transferred, bonding the heterostructure to a receiver substrate, the layer of the first material to be transferred being located at the bonding interface, and detaching the donor substrate along the weakened region so as to transfer the layer of the first material to the receiver substrate.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
83.
NCFET TRANSISTOR COMPRISING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.
A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.
An acoustic wave sensor device comprises a first interdigitated transducer, a first reflection structure, a second reflection structure, a first resonance cavity comprising a first upper surface and formed between the first interdigitated transducer and the first reflection structure, and a second resonance cavity comprising a second upper surface and formed between the first interdigitated transducer and the second reflection structure. At least one of the first and second upper surfaces is covered at least partly by a metalization layer or a passivation layer. The present invention relates also to an acoustic wave sensor assembly.
An acoustic wave sensor device comprises a quartz material layer surface; arranged along a first axis, a first interdigitated transducer disposed over the planar surface of the quartz material layer, a first reflection structure disposed over the planar surface of the quartz material layer, and a second reflection structure disposed over the planar surface of the quartz material layer; and arranged along a second axis, a second interdigitated transducer disposed over the planar surface of the quartz material layer, a third reflection structure disposed over the planar surface of the quartz material layer, and a fourth reflection structure disposed over the planar surface of the quartz material layer; and wherein the first axis and the second axis are inclined to each other by a finite angle.
A hybrid structure and a method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a′) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
SOITEC (France)
Inventor
Augendre, Emmanuel
Laurant, Christine
Reboh, Shay
Vandermolen, Eric
Abstract
One aspect of the invention relates to a method for producing a semiconductor stack (10), comprising, from a first silicon layer (11), referred to as a support layer, the following steps: - forming a silicon carbide layer (12), extending over the support layer (11); and - annealing the layers until cavities (13) are formed, each cavity (13) extending into the support layer (11), from the silicon carbide layer (12).
A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.
A process for fabricating a substrate for a radiofrequency device includes providing a piezoelectric substrate and a carrier substrate, depositing a dielectric layer on a surface of the piezoelectric substrate, assembling together the piezoelectric substrate and the carrier substrate with a polymerizable adhesive directly between the dielectric layer and the carrier substrate to form an assembled substrate, and polymerizing the polymerizable adhesive layer to form a polymerized layer bonding the piezoelectric substrate to the carrier substrate, the polymerized layer and the dielectric layer together forming an electrically insulating layer between the piezoelectric substrate and the carrier substrate.
H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
C09J 7/30 - Adhesives in the form of films or foils characterised by the adhesive composition
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
H10N 30/08 - Shaping or machining of piezoelectric or electrostrictive bodies
H10N 30/082 - Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
91.
METHOD FOR MANUFACTURING A SILICON-CARBIDE-BASED SEMICONDUCTOR STRUCTURE AND INTERMEDIATE COMPOSITE STRUCTURE
A method for manufacturing a semiconductor structure comprises: a) providing a temporary substrate comprising a material having a coefficient of thermal expansion close to that of silicon carbide; b) forming an intermediate graphite layer on a front face of the temporary substrate; c) depositing, on the intermediate layer, a polycrystalline silicon carbide support layer having a thickness of between 10 microns and 200 microns, d) transferring a useful monocrystalline silicon carbide layer onto the support layer in order to form a composite structure, the transfer using molecular adhesion bonding, e) forming an active layer on the useful layer, and f) disassembling, at an interface of or inside the intermediate layer, to structure to form the semiconductor structure including the active layer, the useful layer and the support layer. A composite structure is obtained by the method.
The invention relates to a method for forming a respective layer of silicon carbide (20) on a plurality of silicon substrates, the method consecutively comprising: - placing a plurality of vertically stacked silicon base substrates (10) in a furnace, a vertical gap being provided between two adjacent base substrates (10); - letting a stream of a carbon-containing gas into the furnace; - raising the temperature to a temperature (TF) at which a layer of silicon carbide (20) is formed in order to simultaneously form, via reaction of the carbon-containing gas with the silicon, a layer of silicon carbide (20) on the surface of each base substrate (10) and a layer of carbon (30) on each layer of silicon carbide (20); - removing each layer of carbon (30).
xyy)-based diffusion barrier layer (122) preventing the diffusion of metal elements. The invention also relates to a process for manufacturing a piezoelectric-on-insulator (POI) substrate.
23tEMEM greater than a predetermined thickness, said predetermined thickness being determined according to the thickness of the trapping layer (102) such that the metal element dose in the trapping layer (102) is lower than a predetermined threshold dose. The invention also relates to a process for manufacturing a piezoelectric-on-insulator (POI) substrate.
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
95.
PIEZOELECTRIC-ON-INSULATOR (POI) SUBSTRATE, AND PROCESS FOR MANUFACTURING A PIEZOELECTRIC-ON-INSULATOR (POI) SUBSTRATE
25EMEM greater than a predetermined thickness, said predetermined thickness being determined according to the thickness of the trapping layer (102) such that the metal element dose in the trapping layer (102) is lower than a predetermined threshold dose. The invention also relates to a process for manufacturing a piezoelectric-on-insulator (POI) substrate.
The invention relates to a process for manufacturing a piezoelectric layer (10) on a substrate (11), characterized in that the process involves: - forming, by a first epitaxy, a pseudomorphic seed layer (102) of a first piezoelectric material on a donor substrate (100), - transferring the seed layer (102) and a portion (103) of the donor substrate (100) onto a receiver substrate (110) via at least one electrically insulating layer and/or at least one electrically conductive layer (105) adapted to allow relaxation of the seed layer, - removing the transferred portion (103) of the donor substrate (100) so as to expose a surface of the seed layer (102), - forming a monocrystalline layer (104) of a second piezoelectric material on the seed layer (102).
H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
H10N 30/00 - Piezoelectric or electrostrictive devices
H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
97.
SETUP METHOD FOR ADJUSTING THE TEMPERATURE CONDITIONS OF AN EPITAXY PROCESS
A setup method for an epitaxy process intended to form a useful layer on a receiving substrate, comprising:
a) selecting a test substrate:
having a thickness less than a usual thickness for a given substrate diameter, and/or
having a low interstitial oxygen concentration, and/or
comprising a SOI stack;
b) fixing initial temperature conditions defining temperatures to be applied to areas of the substrate;
c) forming a useful layer on the test substrate by applying the epitaxy process with the initial temperature conditions; then, measuring slip line defects;
d) fixing new temperature conditions;
e) forming a useful layer on a new test substrate of the same type, by applying the epitaxy process with the new temperature conditions; then, measuring slip line defects; and
f) comparing the quantity of slip line defects measured on the test structures and choosing the temperature conditions generating the fewest slip line defects.
A method is used for preparing the residue of a donor substrate, the residue comprising, on a peripheral zone of a main face, a peripheral ring. The method comprises: a first step of removing at least part of the peripheral ring; a second step of processing the main face of the residue aiming to remove a surface layer; a third step, after the second step, of grinding the peripheral zone of the main face of the residue, the third grinding step aiming to reduce the elevation of the peripheral zone.
The present invention relates to a method for producing a composite structure comprising tile portions, comprising: (a) forming a temporary substrate (3') comprising a carrier substrate (3) and a plurality of tile portions (P'1-P'3) of a first material which are arranged on the carrier substrate (3), the formation of the temporary substrate comprising: (i) taking a plurality of tiles (P1-P3) from at least one donor substrate (2) and placing each tile (P1-P3) on an intermediate substrate (1), each donor substrate (2) having a diameter that is smaller than the diameter of the intermediate substrate (1); (ii) forming a weakened region (11) in each tile (P1-P3) by implanting atomic species so as to delimit a tile portion (P'1-P'3) to be transferred; (iii) bonding the intermediate substrate (1) to the carrier substrate (3) via the tiles (P1-P3); and (iv) detaching the tiles along the weakened region, so as to transfer the tile portions (P'1-P'3) to the carrier substrate (3); (b) joining the temporary substrate (3') to a receiver substrate made of a second material, different from the first material, via the tile portions (P'1-P'3); and (c) removing the carrier substrate (3) by removing material or removing a removable interface (5) arranged between the carrier substrate (3) and the tile portions (P'1-P'3) or in the tile portions (P'1-P'3) so as to transfer at least some of the tile portions (P'1-P'3) to the receiver substrate (4) to form the composite structure.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
A method of manufacturing a composite structure comprises: a) providing a donor substrate of a single-crystal semiconductor material, b) implanting ions into the donor substrate, excluding an annular peripheral region, to form a buried brittle plane, the implantation conditions defining a first thermal budget for obtaining bubbling on a face of the donor substrate and a second thermal budget for obtaining a fracture in the brittle plane, c) forming a stiffening film on the donor substrate, carried out by applying a thermal budget lower than the first thermal budget, the stiffening film being perforated in the form of a mesh, the perforated stiffening film leaving a plurality of zones of the front face bare, d) depositing a carrier substrate on the donor substrate carried out by applying a thermal budget greater than the first thermal budget, and e) separating the donor substrate along the brittle plane.
