Abstract

A method of implanting atomic species into a piezoelectric substrate comprises providing a substrate including a piezoelectric portion and an electrically conductive portion mounting the substrate with the electrically conductive portion over a chuck, and implanting atomic species into the piezoelectric portion.

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/08 - Shaping or machining of piezoelectric or electrostrictive bodies

Abstract

A method of manufacturing a structure including a piezoelectric layer on a substrate involves:—forming, by a first epitaxy, a pseudomorphic seed layer of a first piezoelectric material on a donor substrate,—transferring the seed layer and a portion of the donor substrate onto a receiver substrate via at least one electrically insulating layer and/or at least one electrically conductive layer adapted to allow relaxation of the seed layer,—removing the transferred portion of the donor substrate so as to expose a surface of the seed layer,—and forming a monocrystalline layer of a second piezoelectric material on the seed layer.

IPC Classes  ?

• H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

The invention relates to a method for preparing a single-domain thin film (4) of piezoelectric material, the method comprising the finishing of a first layer (8) transferred to a support (2). The finishing comprises a heat treatment of the free face (9) of the first layer, followed by thinning of said layer to form the single-domain thin layer (4). According to the invention, the thinning of the first layer (8) comprises reactive ion etching using a plasma prepared by a mixture of a rare gas and a chlorinated gas.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/082 - Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The invention relates to a method for producing a self-supporting membrane made of monocrystalline silicon, comprising the following steps: a) providing a donor substrate made of monocrystalline silicon, a front face of which extends along a main plane and has at least one lateral dimension that is greater than or equal to 50 mm, b) forming, by ion implantation of hydrogen and helium in the donor substrate, with doses between 1E16 H/cm2and 5E16 H/cm2and between 2E16 He/cm2et 1E17 He/cm2, respectively, a buried fragile plane that is parallel to the main plane and defines a surface layer having a thickness of less than 2 μm together with the front face of the donor substrate, c) applying a separation heat treatment to the donor substrate to propagate a fracture wave in the buried fragile plane and separate the surface layer from the donor substrate, the front face of the donor substrate not being secured to any stiffener. Step c) is carried out such that displacement of the surface layer perpendicularly to the main plane by greater than 200 μm is prevented during the propagation of the fracture wave, the displacement being prevented at least at a peripheral edge of the surface layer. At the end of step c), a self-supporting membrane corresponding to the separated surface layer is formed and has a thickness of less than 2 μm and at least one lateral dimension that is greater than or equal to 50 mm. The invention also relates to the self-supporting membrane.

IPC Classes  ?

• H10P 54/50 -
• H10P 90/00 -
• C30B 33/06 - Joining of crystals
• C30B 29/06 - Silicon

Abstract

The invention relates to a method for characterizing a donor substrate for determining whether this donor substrate is liable to trigger the occurrence of defects in a layer that has been exfoliated by ion implantation. The characterization method comprises X-ray diffraction analysis of a region of the front face of the donor substrate, after the donor substrate has been implanted, to produce numerical angle-of-incidence/intensity data defining a diffraction pattern. The method also comprises a step of processing the diffraction pattern to provide an indicator quantifying the risk of triggering the occurrence of defects in an exfoliated layer of the donor substrate.

IPC Classes  ?

• H10P 74/20 -

Abstract

The invention relates to a method for producing a semiconductor structure, comprising the following steps: - providing a support substrate (1) comprising: · a semiconductor support layer (2) made of a first material and having a first face (3) and a second face (4) opposite the first face (3); · a polycrystalline silicon carbide layer (5) arranged on the first face (3) of the semiconductor support layer (2); - treating (7) the free surface (6) of the polycrystalline silicon carbide layer (5) ;- transferring, by bonding, a layer (8) of gallium nitride onto the treated free surface (6) of the silicon carbide layer (5).

IPC Classes  ?

• H10P 90/00 -
• H10P 10/00 -

Abstract

One aspect of the invention relates to a method for producing a composite structure (1), the method comprising the following steps: - providing a substrate (10) made of a first material, the substrate (10) comprising a first face (10a) and a second face (10b) opposite the first face (10a); - forming a plurality of first trenches (11a) in the substrate (10), the first trenches (11a) extending from the first face (10a); - at least partially filling the first trenches (11a) with a second material (12), one of the first and second materials being silicon and the other of the first and second materials being graphite; - reacting the silicon with carbon so as to form a first discontinuous layer of silicon carbide (13a); and - depositing (S5) a first support layer (14a) made of silicon carbide on the first discontinuous layer (13a) of silicon carbide and on the first face (10a) of the substrate (10) when the second material (12) is silicon, or on the first discontinuous layer of silicon carbide and the second material when the second material is graphite.

IPC Classes  ?

• H10P 90/00 -

Abstract

A method of preparing a thin film of ferroelectric material comprises a step of providing the thin film, the thin film having an exposed free face, and a step of thinning by ion etching, which step is defined by etching parameters. The etching parameters are chosen so that the free face of the thin film has a roughness that does not exceed a threshold value at the end of the thinning step.

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/082 - Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
• H10N 30/853 - Ceramic compositions

Abstract

The invention relates to a method for preparing a silicon-on-insulator substrate (S) comprising an electrical charge trapping layer (4) and having radio frequency and defectivity characteristics below predetermined thresholds. A thickness of the electrical charge trapping layer (4) is chosen to be strictly greater than 1 micrometre and less than 1.6 micrometres. The preparation method comprises a finishing sequence comprising an annealing step exposing the exposed face of the substrate to a neutral or reducing atmosphere for at least 30 minutes at a temperature strictly between 1050°C and 1100°C. According to the invention, the thickness of the electrical charge trapping layer (4) and the temperature of the annealing step are chosen so that the radio frequency and defectivity characteristics are below the respective predetermined thresholds.

IPC Classes  ?

• H10P 90/00 -
• H10W 10/10 -

Abstract

The invention relates to a treatment method for treating a surface (22) of a substrate (1), the substrate (1) comprising a peripheral zone (2) and an inner zone (4), the inner zone being provided with a plurality of tiles (20, 20a), the treatment method comprising steps of: - depositing a spacer (30) in the peripheral zone of the substrate, around the inner zone; and - polishing the surface of the substrate so as to obtain uniformity of a surface of the inner zone of the substrate. A method for transferring a portion of tiles from a donor substrate (10) to a receiver substrate is also described.

IPC Classes  ?

• H10P 52/40 -
• H10P 90/00 -
• H10P 72/70 -
• H10W 10/10 -

Abstract

A piezoelectric-on-insulator (POI) substrate includes a carrier substrate, a trapping layer on a free surface of the carrier substrate, a piezoelectric layer, in particular, a lithium tantalate or lithium niobate piezoelectric layer, and an intermediate structure sandwiched between the piezoelectric layer and the trapping layer of the carrier substrate. The intermediate structure includes at least one tantalum nitride-based or silicon carbon nitride based diffusion barrier layer preventing the diffusion of metal elements. A method is used to manufacture such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H10N 30/88 - MountsSupportsEnclosuresCasings
• H10N 30/09 - Forming piezoelectric or electrostrictive materials
• H10N 30/50 - Piezoelectric or electrostrictive devices having a stacked or multilayer structure

Abstract

According to one aspect, the invention relates to a method for producing a multilayer structure (1), comprising the following steps: providing a temporary substrate (2) formed from a first material and having a first face (2a), a second face (2b), and a lateral surface (2c); depositing on the temporary substrate (2) a carrier semiconductor layer (11) formed from a second material different from the first material, the carrier semiconductor layer (11) comprising a first portion (111) arranged on the first face (2a) of the temporary substrate (2) and a second portion (112) situated at the periphery of the first portion (111) and at the periphery of the temporary substrate (2); transferring a useful semiconductor layer (12) onto the first portion (111) of the carrier semiconductor layer (11); forming (S4) a groove (3) which extends into the carrier semiconductor layer (11) as far as the temporary substrate (2), so as to separate the first portion (111) and the second portion (112) of the carrier semiconductor layer (11) or to separate a first part of the second portion (112) adjacent to the first portion (111) and a second part of the second portion (112) extending over the lateral surface (2c) of the temporary substrate (2); and removing the temporary substrate (2) so as to detach the second portion (112) or the second part of the second portion (112).

IPC Classes  ?

• H10P 90/00 -
• H10P 10/00 -
• H10P 95/00 -

Abstract

344) with a thickness of between 0.5 and 3 µm, and - a seed layer (30) made of monocrystalline GaN, the intermediate layer (20) forming a bonding interface between the support substrate (10) and the seed layer (30).

IPC Classes  ?

• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 84/08 - Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
• H10P 90/00 -
• H10W 10/10 -

Abstract

SLaySLay) consisting of at least 99.92% silicon isotope 28SLaySLaySLayCarCarSLaySLayCarSLaySLaySLayCarCar), thus forming the donor structure (DonStruct).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of processing a composite structure including a thin layer of single-crystal silicon carbide disposed on a polycrystalline silicon carbide carrier substrate, includes, after formation of electronic component elements on a front face of the composite structure, grinding a rear face of the composite structure and removing a work-hardened layer present on the surface of the rear face as a result of the grinding process.

IPC Classes  ?

• H10P 52/40 -
• H10P 14/20 -
• H10P 58/00 -

Abstract

The invention relates to a method for manufacturing a semiconductor structure, which method comprises: a) providing an initial graphite substrate; b) depositing a polycrystalline silicon carbide carrier layer on an initial substrate; c) cutting the initial substrate along a plane parallel to its front face and/or to its rear face, resulting in two stacks, each composed of a temporary graphite wafer derived from the initial substrate, and a carrier layer; d) shaping at least one of the stacks, comprising mechanically thinning the temporary wafer, the stack having a front face on the carrier layer side and a rear face on the temporary wafer side; e) then forming an encapsulation layer on the stack, so as to cover the rear face, the edges and at least partially the front face thereof; f) removing the encapsulation layer from the front face of the stack in order to gain access to a free surface of the carrier layer of the stack; g) transferring a useful layer made of a single-crystal semiconductor material onto the free surface of the carrier layer, either directly or via an intermediate layer, to form a composite structure; h) producing a layer of components on the useful layer; i) removing the temporary wafer to form the semiconductor structure, said semiconductor structure including the layer of components, the useful layer and the carrier layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to an intermediate substrate (100) for producing a high-electron-mobility transistor (HEMT), the intermediate substrate (100) comprising: o a carrier substrate (10) made of polycrystalline silicon carbide having an electrical resistivity of between 1 Ω.cm and 10 kΩ.cm; and o a seed layer (20) made of monocrystalline GaN, the intermediate substrate (100) further comprising a direct bonding interface (15) with or without the addition of material between the silicon carbide of the carrier substrate (10) and the seed layer (20).

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions

Abstract

A method for polishing the front face of a polycrystalline silicon carbide slab comprising a surface region at least partially work damaged under the effect of grinding, comprises: the relative movement of a rotating grinding wheel and the polycrystalline silicon carbide slab until, with the rotating grinding wheel in contact with the front face of the slab, a layer of the polycrystalline silicon carbide slab has been removed, said layer comprising the at least partially work-hardened surface region and having a thickness of less than or equal to 3 μm; the halting of the relative movement and maintaining the rotating grinding wheel in contact with the front face of the polycrystalline silicon carbide slab for a period of time of greater than 15 seconds.

IPC Classes  ?

• C30B 33/06 - Joining of crystals
• C30B 29/36 - Carbides

Abstract

A method of forming a support substrate having a charge-trapping layer involves introducing a single-crystal silicon base substrate into a deposition chamber and, without removing the base substrate from the chamber and while flushing the chamber with a precursor gas, forming an intrinsic silicon epitaxial layer on the base substrate, then forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period, and then forming a polycrystalline silicon charge-trapping layer on the dielectric layer by introducing a precursor gas into the chamber over a second time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature of between 1010° C. and 1200° C.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline material arranged on a carrier substrate made of polycrystalline material, the manufacturing method comprising the following steps: a) providing a raw disk made of polycrystalline material having two faces; b) measuring at least one curvature parameter of the raw disk so as to define a first face with a convex profile and a second face with a concave profile, and selecting the first face to correspond to a front face of the carrier substrate at the end of step c); c) preparing the carrier substrate from the raw disk, involving mechanical and/or chemical treatment of the faces of the raw disk, the carrier substrate having a front face and a rear face corresponding to the first face and the second face of the raw disk, respectively; d) transferring the thin layer onto the front face of the carrier substrate in order to obtain the composite structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline material arranged on a carrier substrate, the manufacturing method comprising the following steps: a) providing a wafer having two faces and originating from a raw disk that has been mechanically ground by removing a thickness of 100 micrometers or less from both faces of the raw disk; b) preparing the carrier substrate from the wafer, involving mechanical and/or chemical treatment of both faces of the wafer; the carrier substrate having two faces; c) measuring at least one curvature parameter of the wafer or of the carrier substrate, and selecting: - from between the two faces of the wafer, the face having a negative arc, such that it corresponds to a front face of the carrier substrate at the end of step b); or - from between the two faces of the carrier substrate, the face having a negative arc, such that it corresponds to a front face of the carrier substrate; d) transferring the thin layer onto the front face of the carrier substrate in order to obtain the composite structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

CarDonDonCarDonDonDon) consisting of at least 99.92% of silicon isotope 28Si.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

A method for manufacturing a support substrate comprising a charge-trapping layer for a semiconductor-on-insulator or piezoelectric-on-insulator structure for a radio-frequency application, includes: placing a base substrate comprising a layer of native silicon oxide in a deposition chamber; raising the temperature of the deposition chamber to a deposition temperature of the charge-trapping layer; introducing an oxidizing gas into the deposition chamber in order to preserve the layer of native silicon oxide during the temperature rise; venting the oxygen from the deposition chamber at the formation temperature of the charge-trapping layer; and-depositing, in the deposition chamber, the charge-trapping layer of polycrystalline silicon on the layer of native silicon oxide.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control

Abstract

The invention relates to a method for preparing a single-domain thin film made of ferroelectric material, the method comprising transferring the layer from a donor substrate to a receiver substrate, followed by a heat treatment (Stab) and then thinning (Thin), the heat treatment comprising: increasing the temperature to a high temperature of between 400°C and the Curie temperature of the ferroelectric material forming the layer; maintaining the temperature for a time of 30 min or more; then lowering the temperature, wherein the temperature increase is carried out by a temperature ramp at a heating rate greater than 7°C/min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A method for producing a device comprising a piezoelectric membrane adjacent at least one cavity includes providing a carrier substrate having surfaces defining the at least one cavity extending into the carrier substrate at a first face of the carrier substrate. A layer of piezoelectric material is deposited on a face of a donor substrate. The layer of piezoelectric material is bonded to the carrier substrate to join the donor substrate and the carrier substrate, and after the bonding, the donor substrate is split along a plane within the donor substrate so as to transfer a membrane comprising the layer of piezoelectric material to the carrier substrate adjacent the at least one cavity. A donor substrate for use in such a method includes a fragile plane therein delimiting a surface layer, and a layer of piezoelectric material having a thickness greater than 500 nm on the surface layer.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Abstract

The invention relates to a treatment method applied to a plurality of substrates (Sub) kept parallel to one another, the treatment comprising at least two successive sequences of treatments, each of the sequences comprising at least one dipping in at least one chemical bath contained in a container provided with a manifold for injecting a treatment solution, the injection manifold comprising dispensing nozzles, the nozzles being distributed along the injection manifold, each of the substrates (Sub) being arranged substantially perpendicular to the injection manifold, in which method: a first of the at least two dipping operations is carried out with the substrates (Sub) oriented in a first orientation (Or1) that is determined at an angle about an axis normal to the substrates; and a second of the at least two dipping operations is carried out with at least a portion of the substrates oriented in a second orientation (Or2) that is different to the first orientation (Or1).

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

Abstract

The invention relates to a method for preparing a substrate comprising a thin layer (3) of piezoelectric material transferred to a carrier (5), the method being based on Smart Cut technology and comprising a step (S2) of implanting a donor substrate (1) and a joining step (S4). According to the invention, the preparation method comprises, before the implantation step (S2), a plasma treatment step (Sp) that comprises exposing the donor substrate (1) to a neutral gas plasma.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

A process for fabricating a semiconductor or piezoelectric structure comprises the following successive steps: (a) providing a donor substrate comprising a piezoelectric or semiconductor layer, (b) providing a receiver substrate, (c) treating a free surface of the donor substrate and/or a free surface of the receiver substrate, (d) bonding the donor substrate to the receiver substrate, the at least one treated free surface being at the interface between the donor substrate and the receiver substrate, and (e) transferring a portion of the piezoelectric or semiconductor layer from the donor substrate to the receiver substrate. The treatment of the free surface of the donor substrate and/or of the free surface of the receiver substrate comprises the following successive steps: (c1) chemical-mechanical polishing, and (c2) removing material from a peripheral region of the polished surface.

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a composite structure, the method comprising the following steps: a) providing a composite substrate including a carrier substrate and a seed layer of single-crystal III-V material arranged on the carrier substrate via a bonding interface, the carrier substrate having a thermal expansion coefficient different from that of the seed layer, and the seed layer having an intrinsic lattice parameter; b) epitaxially growing a stack of single-crystal III-V layers, referred to as epitaxial layers, on the seed layer, each epitaxial layer having an intrinsic lattice parameter. When the thermal expansion coefficient of the carrier substrate is less than that of the seed layer, at least one epitaxial layer of the stack has a composition selected such that the intrinsic lattice parameter thereof is reduced by 200 ppm to 3000 ppm relative to the intrinsic lattice parameter of the seed layer. When the thermal expansion coefficient of the carrier substrate is greater than that of the seed layer, at least one epitaxial layer of the stack has a composition selected such that the intrinsic lattice parameter thereof is increased by 200 ppm to 3000 ppm relative to the intrinsic lattice parameter of the seed layer. The invention also relates to a composite structure.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for manufacturing a donor wafer, comprising the following steps: a) providing a donor substrate made of a monocrystalline material, said donor substrate having been recycled at least once, after a transfer of a thin layer of said donor substrate onto a receiver substrate so as to form a composite structure, said composite structure comprising a surface layer formed entirely or partially by the thin layer and arranged on the receiver substrate, and providing the composite structure, b) checking the quality of the composite structure, by inspecting a free surface of the surface layer, to detect defects present on and/or in the surface layer, said defects then being classified as belonging to a first category, considered to be non-critical, or as belonging to a second category, considered to be critical, c) selecting the donor substrate if a density of defects classified as belonging to the second category during step b) is less than a predetermined density, d) assembling the donor substrate selected in step c) on a support substrate, by bonding, to form the donor wafer. The invention also relates to a donor wafer comprising a donor substrate made of monocrystalline silicon carbide, having a thickness of between 100 μm and 300 μm, arranged on a support substrate, and characterized in that a free face of the donor substrate has less than 0.5 defect/cm2 of the micro-hole or inclusion type.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

The invention relates to a photonic substrate (1) comprising a support (5) having a first face and a second face opposite the first face, an electrical charge trapping layer (4) arranged on the first face of the support (5), a dielectric layer (3; 3a, 3b) arranged on, and in contact with, the electrical charge trapping layer, and an electro-optical layer (2) made of an optical-quality monocrystalline material, the electro-optical layer (2) being arranged on, and in contact with, the dielectric layer (3; 3a, 3b). The invention also relates to an optical device using a substrate of this kind, and to a process for manufacturing said substrate.

IPC Classes  ?

• G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for manufacturing an acceptor substrate in order to form a composite substrate, the method comprising a step of providing a base substrate, and a step of depositing, in a deposition chamber, an electric charge trapping layer in contact with the base substrate. The trapping layer comprises from 40% to 80% of silicon atoms, from 0.1% to 45% of oxygen atoms, and from 0.2% to 50% of nitrogen atoms. The step of depositing the trapping layer implements a mixture of precursor gases. The mixture comprises a gas comprising silicon, a gas comprising oxygen and a gas comprising nitrogen. The gas comprising nitrogen is ammonia or a set of molecules that form ammonia in the deposition chamber during the deposition step.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

A method is used to fabricate a structure comprising a thin layer bonded to a carrier by way of a dielectric layer, the carrier comprising a charge-trapping layer placed on the surface of a base substrate. The method includes applying a surface treatment to an exposed surface of the main face of the carrier and/or to an exposed surface of the main face of the donor substrate to form thereon a layer that acts as a barrier to the diffusion of certain atomic species. This surface treatment involves exposing the exposed surface to an oxygen-containing plasma, and then exposing the exposed surface to a nitrogen-containing plasma.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

32lLTOLTOSiO2SiO2SiO2 being the thickness of the dielectric layer. The invention also relates to a production method.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

The invention relates to an elastic wave device in the field of elastic wave-based components for fields such as telecommunications. The device of the invention comprises a first electromechanical device, in particular a transducer (3) and a second electromechanical device, in particular a transducer (5), an array of at least one electrode (4000) located between the first transducer (3) and the second transducer (5) in the direction of propagation of the elastic waves, of which array at least one electrode is connected to a predetermined electrical potential (1005, 2005, 3005) via a modifiable impedance (1003, 2003, 3003), and a control means (1007, 2007, 3007) for modifying the modifiable impedance (1003, 2003, 3003).

IPC Classes  ?

• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

32lLNOLNOSiO2SiO2LNOSiO2LNOSiO2SiO2 is equal to between 0.75 and 0.85, preferably between 0.79 and 0.81.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

32lLTOLTOSiO2SiO2SiO2 being the thickness of the dielectric layer.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks

Abstract

A semiconductor structure (1) comprising: − a Silicon-On-Insulator substrate (100) comprising: o a base layer (103) comprising silicon; o an intermediate layer (102) on top of the base layer; and o a first silicon layer (101) on top of the intermediate layer (102), the first silicon layer (101) having a (1,0,0) lattice orientation; − a second silicon layer (200) on top of the first silicon layer (101), the second silicon layer (200) having a (1,1,1) lattice orientation; and − an interface layer (300) between the first silicon layer (101) and the second silicon layer (200).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A method for preparing a monodomain thin layer of ferroelectric material comprises: implanting light species in a ferroelectric donor substrate in order to form an embrittlement plane and to define a first layer therein; assembling the donor substrate with a support substrate by means of a dielectric assembly layer; and fracturing the donor substrate at the embrittlement plane. The dielectric assembly layer comprises an oxide having a hydrogen concentration lower than that of the first layer or preventing the diffusion of hydrogen to the first layer, or the dielectric assembly layer comprises a barrier preventing the diffusion of hydrogen to the first layer. A heat treatment of a free face of the first layer is used to diffuse the hydrogen contained therein and cause the multidomain transformation of a surface portion of this first layer, followed by a thinning of the first layer in order to remove the surface portion.

IPC Classes  ?

• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

A surface wave device comprises a substrate; a piezoelectric layer above an upper face of the substrate; a pair of electrodes in contact with the piezoelectric layer, the two electrodes including fingers extending in the same direction so as to form a periodic structure in which the fingers of the two electrodes alternate with each other, and having an interdigital distance separating the centers of two adjacent fingers of the same electrode; a metal layer interposed between the substrate and the piezoelectric layer; and a dielectric layer interposed between the metal layer and the piezoelectric layer, wherein the metal layer has a thickness of 5 nm to 100 nm and the dielectric layer has a thickness of 25 nm to 600 nm.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
• H03H 9/25 - Constructional features of resonators using surface acoustic waves

Abstract

The invention relates to a method for measuring at least one thickness parameter of a superficial layer of an SOI substrate, comprising the following steps: a) measurement of thickness at a predefined number of first points, spatially distributed over the surface, resulting in a first series of values comprising a first maximum and a first minimum, the measurement of thickness being carried out using a first technique; b) production of a complete map of the surface of the superficial layer using a second technique, different from the first technique, the map expressing a physical characteristic of the superficial layer correlated with its thickness; c) analysis of the map so as to identify whether there is a signature liable to be indicative of a thickness variation greater than or equal to the difference between the first maximum and the first minimum, in a localized region of the superficial layer; d) if a signature is identified, measurement of thickness at a plurality of second points positioned in the localized region, resulting in a second series of values comprising a second maximum and/or a second minimum; the measurement of thickness being carried out using the first technique; and e) calculation of at least one thickness parameter, based on the first series of values, and potentially on the second series of values.

IPC Classes  ?

• G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

The invention relates to a method for preparing a composite structure, comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide, a free face of which extends along a main plane, which growth layer is arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a crystallographic orientation such that there is: a disorientation angle between a given crystallographic plane and the free face, a disorientation direction, which corresponds to a projection of an axis normal to the free face onto the crystallographic plane, and a reference direction, which corresponds to a projection of the disorientation direction onto the main plane; 2) forming a trench in the growth layer, the trench having an inner edge which extends at a distance and continuously along the peripheral perimeter, following a contour such that, by defining four cardinal points (North-South-West-East) on the peripheral perimeter, with the West-East direction corresponding to the reference direction: the contour passing through the cardinal points North-West-South follows the general shape of the peripheral perimeter, and the contour passing through the cardinal points North-East-South has a saw-toothed pattern. The invention also relates to a composite structure capable of being made using the aforementioned preparation method.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a composite structure having a front face and a rear face extending parallel to a main plane, which structure comprises: - a useful layer of single-crystal silicon carbide, a free face of which constitutes the front face, which layer has a first concentration of N-type dopants; - a carrier substrate made of polycrystalline silicon carbide, a free face of which constitutes the rear face, which substrate has a second concentration of N-type dopants, the second concentration being higher than the first concentration; - an intermediate region extending along the main plane and including an interface zone between an assembled face of the useful layer and an assembled face of the carrier substrate; the composite structure being characterised in that the intermediate region comprises inclusions of single-crystal silicon carbide in direct contact with the useful layer and extending, in a direction normal to the main plane, between grains of the carrier substrate, the inclusions having a third concentration of N-type dopants which is between the first concentration and the second concentration. The invention also relates to a method for producing such a composite structure.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The present invention relates to a method for treating a substrate (10) having a rear face (204) made of polycrystalline silicon carbide and a front face (203) intended for the manufacture of an electronic component, which method comprises: forming a vitreous carbon layer (40) on the rear face (204); transferring a layer (20) made of a monocrystalline semiconductor material onto the front face (203); and, heat treating the substrate after the formation of the carbon layer (40), the carbon layer (40) limiting the increase in the roughness of the rear face (204) during the heat treatment.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

sublaylay) joined to the support assembly (Sprt.Set) so as to obtain a structure (Struct), the ferroelectric layer having a negative polarisation (P1); performing an additional full-field hydrogen implantation step, parameterised so as to correct or prevent the occurrence of polarisation inversion in the volume of the ferroelectric layer and/or at its interface with the support assembly (Sprt.Ens); and applying at least one first heat treatment to the structure (Strct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention comprises: a starting structure (Struct_0) designed to undergo separation by laser irradiation, comprising a substrate (Sub2), a transferred layer (TrLay), and a graphene oxide layer (GO, GO2) interposed between the substrate (Sub2) and the transferred layer (TrLay).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The present invention relates to a method for treating a substrate having a free surface made of a semiconductor material, in particular a single–crystal semiconductor material, comprising a method for stabilising the surface against the formation of terraces and/or beads, the method comprising: • forming a vitreous carbon layer (30) by a gas-phase carbon reaction on the surface at a temperature (T1) greater than 700°C, preferably greater than 800°C, and strictly lower than 1000°C, preferably lower than 950°C, and more preferably lower than 900°C; and • applying a heat treatment to the substrate after stabilising the surface, wherein the vitreous carbon layer (30) limits the reorganisation of the surface made of a semiconductor material in the form of terraces, the depositing of the carbon layer (30) and the heat treatment being carried out in the same furnace.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method of manufacturing a monocrystalline layer comprises the following successive steps: providing a donor substrate comprising a piezoelectric material of composition ABO3, where A consists of at least one element from among Li, Na, K, H, Ca; and B consists of at least one element from among Nb, Ta, Sb, V; providing a receiver substrate, transferring a layer called the “seed layer” from the donor substrate on to the receiver substrate, such that the seed layer is at the bonding interface, followed by thinning of the donor substrate layer; and growing a monocrystalline layer of composition A′B′O3 on piezoelectric material ABO3 of the seed layer, where A′ consists of a least one of the following elements Li, Na, K, H; B′ consists of a least one of the following elements Nb, Ta, Sb, V; and A′ is different from A or B′ is different from B.

IPC Classes  ?

• H10N 30/093 - Forming inorganic materials
• C01G 31/02 - Oxides
• C01G 33/00 - Compounds of niobium
• C01G 35/00 - Compounds of tantalum
• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/22 - Complex oxides
• C30B 29/30 - NiobatesVanadatesTantalates
• H01L 21/762 - Dielectric regions
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/076 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
• H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
• H10N 30/853 - Ceramic compositions

Abstract

lay-138lay4242laylay) of the starting composite structure (StartStruct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The present invention relates to a method of method of manufacturing a heterostructure for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of a piezoelectric material on or over the support substrate, removing a first peripheral portion of the block of a piezoelectric material and a first peripheral portion of the support substrate to obtain an exposed portion of the support substrate with a roughness with a root-mean-square height, Sq, in the range of 0.4 µm to 0.8 µm, thinning the block of a piezoelectric material after removal of the first peripheral portion of the block of a piezoelectric material to obtain a piezoelectric substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
• H10N 30/80 - Constructional details

Abstract

The invention relates to a method (100) for polishing a planar substrate (Waf) using a planarising and polishing machine comprising a support plate (Pl) provided with a polishing pad (Pol.Pad), a conditioning head (Cond.Head) for conditioning the polishing pad, and a head (Pol.Head) for holding the planar substrate (Waf) against the polishing pad, the method comprising a first step (110) of a first conditioning of the polishing pad (Pol.Pad) using the conditioning head (Cond.Head), wherein the planar substrate (Waf) is not subjected to any polishing operation; a second step (120) of a first polishing of the planar substrate (Waf), wherein the polishing pad is not subjected to any conditioning operation; and a third step (130) in which (i) a second polishing of the planar substrate (Waf) is performed and, simultaneously, (ii) a second conditioning of the polishing pad (Pol.Pad) is performed.

IPC Classes  ?

• B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
• B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces

Abstract

The invention relates to a semiconductor substrate (Sub) configured to allow laser separation of a layer of active material (ActMat), comprising: a support substrate (Sprt); an inorganic layer (Inorg) on the support substrate, wherein the inorganic layer is formed of a material selected from among Al2O3, TiO2, WO3, La2O3, LaAlO3 and TiN; an electrically insulating layer (Ins) on the inorganic layer; and the layer of active material (ActMat) on the electrically insulating layer, wherein the layer of active material is monocrystalline.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The invention relates to a method for assembling two substrates by molecular adhesion, at least one of the two substrates being provided with a dielectric surface layer. The method comprises activating the dielectric surface layer by exposure to a plasma formed between two electrodes (4a, 4b) of an activation chamber (3), for an activation period of 15 seconds to 2 minutes and during which a radiofrequency power is applied to one of the electrodes. The method comprises injecting into the activation chamber (3) a controlled flow of oxygen or nitrogen and a controlled flow of a gas comprising sulphur. The method is characterised in that the radiofrequency power has a density strictly greater than 1.1 W/cm^2.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a tiled donor substrate, the method comprising the following steps: a) providing an initial structure comprising a carrier substrate having a front face and a rear face, and a plurality of tiles made of a first monocrystalline material, wherein the tiles are arranged on the front face and are spaced apart from one another; b) forming a complementary layer by means of an additive manufacturing technique, wherein the complementary layer: - is arranged between the tiles, in contact with the front face of the carrier substrate; - is composed of a material, referred to as the second material, having a coefficient of thermal expansion matched to that of the first material; c) applying a mechanical and/or chemical-mechanical surface treatment to the complementary layer and to the tiles, in order to obtain the tiled donor substrate, wherein a front face of the substrate has a flat and continuous surface at which the plurality of tiles and the complementary layer are flush.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disc, with a grinding wheel, the abrasive grit of which has an average size greater than or equal to 10 μm, to obtain a surface-ground disc having at least one surface-ground face; c) applying a heat treatment to the surface-ground disc, at a temperature above a growth temperature of the raw disc employed in step a), and below a melting temperature of the polycrystalline material, so as to obtain an annealed disc, d) thinning the annealed disc, from the at least one surface-ground face, said thinning including fine grinding with a grinding wheel, the abrasive grit of which has an average size of less than 10 μm, so as to obtain the support substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disk in order to obtain a surface-ground disc having at least one surface-ground face, the rough grinding leading to the formation of a damaged superficial region on said surface-ground face; the damaged superficial region comprising a work-hardened superficial layer and a stressed underlying layer; c) applying a heat treatment to the surface-ground disc, the temperature and the duration of the heat treatment being defined so as to relax the stresses present in the stressed layer; step c) leading to the obtaining of an annealed disc comprising, at the at least one surface-ground face, a superficial first annealed layer, instead of the work-hardened layer, and an underlying second annealed layer, instead of the stressed layer; d) thinning the annealed disc, from the at least one surface-ground face, in order to remove the first annealed layer; step d) leading to the obtaining of the support substrate in which all or part of the second annealed layer is preserved.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for transferring a thin film (7) onto a final carrier (11), the thin film (7) and the final carrier (11) having different coefficients of thermal expansion. The method comprises transferring the thin film (7) onto an intermediate carrier (5) at a first bonding interface (IA1) and forming a dielectric surface layer (10) on the exposed face of the thin film (7). The method further comprises activating the dielectric surface layer (10) by exposing it to a plasma having a radiofrequency power density of strictly greater than 1.1 W/cm^2, then assembling the thin film (7) via the dielectric surface layer (10) to the final carrier (11) and thus defining a second bonding interface (IA2). Finally, the method comprises mechanically stressing the final carrier (11) and/or the intermediate carrier (5) to remove the intermediate carrier (5) from the thin layer (7) at the first bonding interface (IA1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a substrate, according to which an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101) is polymerised at a polymerisation site, and, after the polymerisation step, the heterostructure (107) is moved to another site. The method is characterised in that, during the polymerisation step, the heterostructure (107) is colder than an ambient temperature of the other site. The invention also relates to a substrate (119) comprising an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101), characterised in that, when the substrate (119) has a temperature between 20°C and 25°C, in particular between 20°C and 22°C, the adhesive layer (115) is under compression, in particular with respect to the handling substrate (100) in such a way as to induce a curve (BOW) of the substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention relates to a method for producing a stacked structure comprising a layer of semiconductor material bonded to a substrate, which comprises: producing a heterostructure by: • forming an intermediate layer made of a two-dimensional material on a growth substrate (1); patterning the intermediate layer with a plurality of openings to form a patterned intermediate layer (3); growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a handling substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from transferring the continuous epitaxial layer (4) from the heterostructure to the handling substrate (6).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, at least one assembly of the plurality of vias forming a pattern repeated along at least one direction of a main extension plane of the first layer and the second layer. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A method for assembly by molecular adhesion of two substrates each having a main face, at least one of the two substrates bearing a dielectric surface layer on its main face, comprises (a) contacting the main faces of the two substrates, then (b) initiating and propagating a bonding wave between the main faces of the two substrates to assemble them with one another. Prior to the contacting of the main faces, sulfur is introduced into the dielectric surface layer at a dose of more than 3.0 E13 at/cm^2 into this layer. A joined structure is obtained via the method.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A piezoelectric-on-insulator (POI) substrate comprises a support substrate, in particular, a silicon-based substrate, a piezoelectric layer, in particular, a layer of lithium tantalate or lithium niobate, a dielectric layer, in particular, a layer of silicon oxide, sandwiched between the piezoelectric layer and the support substrate, and a trapping structure sandwiched between the dielectric layer and the support substrate. The trapping structure comprises at least two trapping layers that are based on different materials. A particular method may be employed for producing such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H10N 30/00 - Piezoelectric or electrostrictive devices
• H10N 30/03 - Assembling devices that include piezoelectric or electrostrictive parts
• H10N 30/853 - Ceramic compositions

Abstract

A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, each via having at least one transverse dimension less than or equal to 30 μm. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

The invention relates to a method for preparing a carrier (1) for a composite substrate (S), which method comprises forming a superficial porous layer (P) on a first face (1c) of the carrier (1), and dispensing a viscous solution comprising a solvent and a precursor of a filler material on the first face (1c) of the carrier (1) so as to absorb at least some of the viscous solution in open pores of the superficial porous layer (P). In a fourth step, the carrier (1) is heat-treated to transform the viscous solution present in the open pores in order to fill the open pores with the filler material.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. After transferring the monocrystalline semiconductor layer, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A method for fabricating a microelectronic device includes: producing a structure with a support provided with a semiconductor layer of a first level of components and another semiconductor layer of a second level, the other semiconductor layer including a lower sublayer contacting the insulating layer and an upper sublayer disposed on the lower sublayer, one of the lower and upper sublayers made from crystalline material while another of the lower and upper sublayers made from amorphous material; forming a transistor gate block on the semiconductor layer; forming, on either side of the gate block, by implanting dopants in the semiconductor layer, doped regions on either side of a semiconductor region facing the gate block for accommodating a channel of the transistor; and implementing heat treatment to recrystallize the second semiconductor sublayer while using the first semiconductor sublayer as a start region of a crystalline front while activating the dopants.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 62/40 - Crystalline structures
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A substrate for a power or radiofrequency electronic device includes a self-supporting support substrate made of polycrystalline silicon carbide and a surface layer of monocrystalline silicon carbide that extends over a front face of the support substrate. The support substrate has at least one porous portion extending from a rear face of the support substrate. The porous portion has a degree of porosity of greater than 5%.

IPC Classes  ?

• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/66 - High-frequency adaptations
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method for manufacturing a structure comprising at least two chips on a receiver substrate comprises: forming a pseudo-donor substrate by placing at least one tile of at least one donor substrate on a support substrate; bonding the pseudo-donor substrate to a receiver substrate via the tiles so that each tile at least partially covers at least two different zones of interest of the receiver substrate; transferring a portion of the tiles to the receiver substrate; at least one step of chemical-mechanical polishing of the tiles of the pseudo-donor substrate and/or of the tile portions transferred to the receiver substrate; after the at least one step of chemical-mechanical polishing, a removal of material from the tile portions so as to divide each tile portion into at least two chips each arranged on a respective zone of interest.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The invention relates to a method for direct bonding between two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide; (b) depositing a specific compound on the first bonding surface made of hydrophilic silicon oxide, the specific compound being an organic compound consisting of a basic functional group and substituents of the basic functional group, each substituent being a hydrophobic group; (c) bringing the first bonding surface made of hydrophilic silicon oxide, on which the specific compound has been deposited, into contact with the second bonding surface made of hydrophilic silicon oxide, so as to adhere the first substrate to the second substrate.

IPC Classes  ?

• C09J 5/00 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers
• C09J 5/02 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
• C09J 5/06 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first hydrophilic silicon oxide bonding surface and a second hydrophilic silicon oxide bonding surface; (b) depositing a specific compound on the first hydrophilic silicon oxide bonding surface, the specific compound being derived from the ammonia molecule or the ammonium ion by at least the substitution of a hydrogen atom with a hydroxyl -OH group and/or an amino -NH2 group, the specific compound not comprising carbon atoms; and (c) bringing the first hydrophilic silicon oxide bonding surface on which the specific compound has been deposited into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: a) providing a first substrate and a second substrate comprising, respectively, a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide, b) adding fluoride ions to the first hydrophilic silicon oxide bonding surface; c) bringing the first hydrophilic silicon oxide bonding surface into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate, by way of the fluoride ions at the bonding interface.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), wherein the first direction (13a) is opposite to the second direction, and wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17al to 17a3 and 17bl to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n of the substrate surface.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

A piezoelectric-on-insulator (POI) substrate comprises: a carrier substrate, in particular, a substrate based on silicon; a piezoelectric layer, in particular, a layer of lithium tantalate or of lithium niobate; a dielectric layer, in particular, a layer of silicon oxide, sandwiched between the piezoelectric layer and the substrate; a trapping structure sandwiched between the dielectric layer and the carrier substrate. The trapping structure comprises at least two trapping layers, which layers are separated each time by a dielectric intermediate layer. A method is used for producing such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

Abstract

A method for transferring a thin film onto a support substrate comprises implanting into a donor substrate light species including co-implantation of hydrogen ions at a first dose and a first implantation energy, and helium ions at a second dose and a second implantation energy. Hydrogen ions are also locally implanted at a third dose and a third energy to form an overdosed local region in a buried fragile plane formed by the implanted ions. The donor substrate and the support substrate are assembled by direct bonding to form a bonded structure, and a fracture heat treatment is applied to the bonded structure so as to induce spontaneous separation along the buried fragile plane. The separation leads to the transfer of a thin film from the donor substrate onto the support substrate. The overdosed local region of the buried fragile plane constitutes a starting point for the separation.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a method of manufacturing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of piezoelectric material on or over the support substrate, wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate, chemical-mechanical polishing, CMP, the block of piezoelectric material to obtain a piezoelectric substrate and implanting a species into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. The CMP is performed by means of a CMP pad comprising a sub pad with a hardness of more than 45 shore A.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of refreshing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing the donor substrate to be refreshed comprising a support substrate and a first piezoelectric substrate formed over the support substrate comprising or consisting of one of lithium tantalate and lithium niobate, wherein the first piezoelectric substrate is a second piezoelectric substrate from which a piezoelectric layer has been transferred to a target substrate and chemical-mechanical polishing, CMP, the first piezoelectric substrate to obtain a refreshed donor substrate comprising a refreshed piezoelectric substrate, wherein the CMP comprises removing a layer of the first piezoelectric substrate with a thickness of at most 2 µm, in particular, at most 1.2 µm.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of manufacturing a Piezoelectric on Insulator, POI, structure, comprising providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or consists of one of lithium tantalate and lithium niobate, transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, and polishing the piezoelectric layer transferred to the target substrate with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percent of the amorphous silicon in the range of 4 to 18.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The invention relates to a method for manufacturing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of tiles (1) arranged at a distance from one another on a support substrate (3), comprising the steps of: - arranging, on the support substrate (3), said tiles (1) and an intermediate substrate (2) comprising a plurality of through-openings (20), such that each tile (1) extends into a respective through-opening (20) of the intermediate substrate, and - performing chemical-mechanical polishing of the tiles (1) arranged in the openings of the intermediate substrate.

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

The invention relates to a method for transferring chips onto a receiver substrate from tiles arranged on a support substrate, comprising: - forming a substrate (10), referred to as the pseudo-donor substrate, comprising the support substrate (2) and the tiles (1), wherein two adjacent tiles are spaced apart by a first distance (d1), - carrying out chemical mechanical polishing on the tiles, - forming a weakened zone in at least one portion of the tiles so as to delimit a respective chip, - bonding the pseudo-donor substrate to the receiver substrate via the tiles, - detaching the tiles along the weakened zone so as to transfer a respective chip onto the receiver substrate, two adjacent chips being spaced apart by a second distance greater than the first distance (d1), - before the bonding step, locally roughening the surface of the tiles and/or the receiver substrate to make regions of the surface unsuitable for bonding, so as to prevent the chips from being transferred in said regions.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for transferring a thin film onto a support substrate, which comprises: providing a bonded assembly that comprises a donor substrate and the support substrate, assembled by direct bonding at their respective front faces, following a bonding interface, the bonded assembly having a local unbonded area within this bonding interface, the donor substrate further comprising a buried brittle plane; separating along the buried brittle plane, initiated at the local unbonded area after microcrack growth in said plane by thermal activation, the separation resulting in the transfer of a thin film from the donor substrate to the support substrate. The method is characterised in that the local unbonded area is generated solely by a roughened area, produced deliberately on at least one of the front faces of the donor and support substrates prior to assembly, free of topology and having a predetermined roughness with an amplitude of between 0.5 nm RMS and 60.0 nm RMS.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a structure (Strc) capable of forming a quantum device, comprising: a silicon carrier substrate (Car); a first layer (Si-L1) of silicon isotope 28Si; a layer (Ox) of silicon oxide; a second layer (Si-L2) of silicon isotope 28Si, wherein the structure is formed by the carrier substrate (Car), the first layer (Si-L1) of silicon isotope 28Si, the layer (Ox) of silicon oxide, and the second layer (Si-L1) of silicon isotope 28Si, stacked in this order, wherein the first layer (SiL1) and the second layer (Si-L2) of silicon isotope 28Si are each made up of at least 99.92% of silicon isotope 28Si.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of first blocks (1) arranged at a distance from one another on a carrier substrate (3), wherein the method comprises: - arranging, on the carrier substrate (3), the first blocks (1) and a plurality of second blocks (2) arranged between the first blocks (1) such that each edge of each first block (1) faces at least one second block (2), wherein the first blocks (1) comprise a first material and the second blocks (2) comprise a second material different from the first material; and - chemical-mechanical polishing of the first and second blocks (1, 2).

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

A method for correcting the thickness of a piezoelectric layer arranged on a piezoelectric-on-insulator substrate comprises: measuring the thickness of at least one intermediate layer located between the piezoelectric layer and a carrier substrate; measuring the thickness of the piezoelectric layer; based on the measurements of the thickness of the at least one intermediate layer and of the piezoelectric layer and on a numerical model of at least one property of the piezoelectric layer as a function of a plurality of pairs of thicknesses of the piezoelectric layer and of the at least one intermediate layer, computing a thickness correction for the piezoelectric layer with a view to obtaining a target value for each property; and applying the thickness correction to the piezoelectric layer using a milling process in a topographically discriminating manner.

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

A method for producing a semiconductor-on-insulator structure comprises the steps of: —joining a support substrate with a donor substrate, the support substrate having an electrical resistivity greater than or equal to 500 Ω·cm and containing interstitial nitrogen and interstitial oxygen, the initial concentration of interstitial oxygen in the support substrate being between 15 and 25 old ppma, the donor substrate including a semiconductor layer, an electrically insulating layer being at the interface between the support substrate and the donor substrate; and—transferring the semiconductor layer onto the support substrate, the method further comprising a nucleation step comprising a heat treatment in order to precipitate part of the oxygen and nitrogen so as to form nuclei of oxygen and nitrogen precipitates, and a stabilization step comprising a heat treatment in order to grow the nuclei to a size of between 10 and 50 nm.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Abstract

A piezoelectric-on-insulator substrate comprises a support substrate having a first acoustic impedance, a piezoelectric layer, especially a layer of lithium tantalate, lithium niobate, aluminum nitride, lead zirconate titanate, langasite or langatate, a dielectric layer having a second acoustic impedance and sandwiched between the piezoelectric layer and the support substrate, an intermediate layer positioned between the support substrate and the dielectric layer. The intermediate layer is a layer having a variable composition, in particular along its thickness, such that the acoustic impedance of the intermediate layer varies, in particular gradually, between the values of the first and the second acoustic impedances. The present disclosure also relates to a method for producing such a piezoelectric-on-insulator substrate and also to a surface acoustic wave device comprising such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

Abstract

The invention relates to a method for producing a SOI structure, comprising the following steps: a) providing an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to standard ASTM'79 and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a carrier substrate for the SOI structure after having undergone the subsequent step b); b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on a front face, of a silicon oxide layer other than optionally a native oxide layer, the sequence consisting of: - a first heat treatment defined by a plateau at a temperature higher than 1200°C and lower than 1280°C and with a duration of between 1 second and 60 seconds, by a temperature decrease ramp of between 10°C/s and 70°C/s, and by an argon or argon-hydrogen atmosphere; followed by - a second heat treatment defined by a plateau at a temperature of between 900°C and 1100°C, without an intermediate step before this temperature, under a neutral or oxidising atmosphere, in order to form a carrier substrate comprising: - a stripped surface layer, with a thickness greater than 40 μm and having a micro-defect concentration (BMD) of less than 108/cm3, and - an enriched deep layer, under the stripped surface layer, having a micro-defect concentration (BMD) of between 2.108/cm3and 5.1010/cm3. The invention also relates to a carrier substrate and a SOI structure including the carrier substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions

Abstract

Disclosed is a carrier (100) intended to be split by laser radiation, comprising a carrier substrate (Sprt); on the carrier layer, a splitting layer (Sep) formed from an inorganic material of thickness between 10 nm and 100 nm; and a layer (Brg) forming a Bragg mirror, the splitting layer (Sep) being interposed between the carrier substrate (Sprt) and the layer (Brg) forming the Bragg mirror, the carrier being configured in such a way that the carrier substrate is substantially transparent to laser radiation of a certain wavelength, the layer forming the Bragg mirror is substantially reflective with respect to the laser radiation, and the splitting layer (Sep) can absorb some of the laser radiation, such that the carrier can be split into two parts level with the splitting layer (Sep) under the action of the laser radiation.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

CarCarDonDon) respective overcoat layers (Cap1, Cap2) on the two superlattices (Stck1, Stck2); and assembling (660) the two superlattices (Stck1, Stck2) by placing their respective overcoat layers (Cap1, Cap2) in contact, so that together they form a bonding layer, the first overcoat layer (Cap1) and the second overcoat layer (Cap2) each having a thickness of less than 2 nm.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for controlling the quality of a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the method comprising: a) inspection of a free surface (10a) of the thin layer (10) using a technique coupling visible-light confocal microscopy and photoluminescence imaging, making it possible to detect defects, called secondary defects, b) preliminary identification of the secondary defects, by similarity, on the basis of their visible-light image, by virtue of an image recognition algorithm trained on various types of defects such as holes, bubbles, scratches, and defects of crystalline origin; at the end of step b), each secondary defect is associated with one identified type of defect, with a certain level of similarity, c) final classification of at least certain secondary defects by application of the following first conditions: - if the level of similarity associated with a secondary defect is greater than a high level, said secondary defect is definitively classified in the identified type of defect, - if the level of similarity associated with the secondary defect is between a low level and the high level, the photoluminescence image of said defect is analysed; if the secondary defect is associated with a labelled type of PL defect, said secondary defect is definitively classified in the identified type of defect, - in all other cases, the secondary defect is definitively classified as not a defect.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• C30B 29/36 - Carbides
• G01N 21/64 - FluorescencePhosphorescence
• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer

Abstract

The invention relates to a process for fabricating a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the process comprising the following steps: 1) providing at least one donor substrate made of single-crystal silicon carbide, having a front side and a rear side, the front side potentially having defects, called primary defects; 2) controlling the quality of the - at least one - donor substrate by means of a photoluminescence-based imaging technique, so as to extract a map of the front side, called the first map, cataloguing the primary defects identified as being of micro-hole type, of the complex type consisting of star stacking faults or of point-defect type; 3) transferring a thin layer, obtained from a surface layer of the - at least one - donor substrate, onto a carrier substrate made of polycrystalline silicon carbide, in order to obtain a composite structure and a residual donor substrate; 4) inspecting a free surface of the thin layer of the composite structure by means of a technique for inspecting for defects by means of scattering of an ultraviolet laser beam, so as to extract a map of the free surface, called the second map, cataloguing defects called secondary defects; 5) grading the composite structure, this including a comparison of the first map and of the second map.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01N 21/64 - FluorescencePhosphorescence
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• G01N 21/84 - Systems specially adapted for particular applications

Abstract

CarDonDon) a second superlattice (Stck2) on a second substrate by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers; and assembling (560) the second superlattice (Stck2) on the first superlattice (Stck1) at a dielectric separation layer which separates the first superlattice (Stck1) and the second superlattice (Stck2) and keeps them attached to one another, the first superlattice (Stck1), the separation layer and the second superlattice (Stck2) being stacked in this order.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

CarDonDonDon) a weakening plane (Imp) in the second substrate; assembling (560) the seed layer (Init) on the first superlattice (Stck1) at a dielectric separation layer that separates the first superlattice (Stck1) and the seed layer (Init) and keeps them attached to each other; removing (570A) a portion of the second substrate by fracturing the second substrate at the weakening plane (Imp) after the assembly step (560); exposing (570B) the seed layer (Init) after the step (570A) of fracturing the second substrate; and forming (580) the second superlattice (Stck2) on the exposed seed layer (Init).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

A method of manufacturing a donor substrate for the transfer of a piezoelectric layer onto a support substrate comprises providing a handling substrate and providing a piezoelectric substrate. A polymer layer is deposited on the handling substrate or the piezoelectric substrate. An intermediate layer is formed on a free surface of the piezoelectric substrate, and the piezoelectric substrate is assembled on the handling substrate such that the intermediate layer formed on the piezoelectric substrate is between the polymer layer and the piezoelectric substrate to form the donor substrate. A donor substrate may be manufactured by such a method, and such a donor substrate may be used for transferring a piezoelectric layer to another substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

A method of manufacturing a donor substrate for the transfer of a piezoelectric layer onto a support substrate comprises providing a handling substrate and a piezoelectric substrate. A surface activation treatment is carried out on the surface of the piezoelectric substrate to form an activated surface on the piezoelectric substrate. A polymer layer is deposited on the activated surface of the piezoelectric substrate or on the handling substrate. The piezoelectric substrate is then assembled on the handling substrate in such a way that the polymer layer is between the activated surface of the piezoelectric substrate and the handling substrate. The donor substrate may be used to transfer a layer of piezoelectric material from the donor substrate onto a support substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives