Abstract

The invention relates to a method for preparing a composite structure, comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide, a free face of which extends along a main plane, which growth layer is arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a crystallographic orientation such that there is: a disorientation angle between a given crystallographic plane and the free face, a disorientation direction, which corresponds to a projection of an axis normal to the free face onto the crystallographic plane, and a reference direction, which corresponds to a projection of the disorientation direction onto the main plane; 2) forming a trench in the growth layer, the trench having an inner edge which extends at a distance and continuously along the peripheral perimeter, following a contour such that, by defining four cardinal points (North-South-West-East) on the peripheral perimeter, with the West-East direction corresponding to the reference direction: the contour passing through the cardinal points North-West-South follows the general shape of the peripheral perimeter, and the contour passing through the cardinal points North-East-South has a saw-toothed pattern. The invention also relates to a composite structure capable of being made using the aforementioned preparation method.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a composite structure having a front face and a rear face extending parallel to a main plane, which structure comprises: - a useful layer of single-crystal silicon carbide, a free face of which constitutes the front face, which layer has a first concentration of N-type dopants; - a carrier substrate made of polycrystalline silicon carbide, a free face of which constitutes the rear face, which substrate has a second concentration of N-type dopants, the second concentration being higher than the first concentration; - an intermediate region extending along the main plane and including an interface zone between an assembled face of the useful layer and an assembled face of the carrier substrate; the composite structure being characterised in that the intermediate region comprises inclusions of single-crystal silicon carbide in direct contact with the useful layer and extending, in a direction normal to the main plane, between grains of the carrier substrate, the inclusions having a third concentration of N-type dopants which is between the first concentration and the second concentration. The invention also relates to a method for producing such a composite structure.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The present invention relates to a method for treating a substrate (10) having a rear face (204) made of polycrystalline silicon carbide and a front face (203) intended for the manufacture of an electronic component, which method comprises: forming a vitreous carbon layer (40) on the rear face (204); transferring a layer (20) made of a monocrystalline semiconductor material onto the front face (203); and, heat treating the substrate after the formation of the carbon layer (40), the carbon layer (40) limiting the increase in the roughness of the rear face (204) during the heat treatment.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

sublaylay) joined to the support assembly (Sprt.Set) so as to obtain a structure (Struct), the ferroelectric layer having a negative polarisation (P1); performing an additional full-field hydrogen implantation step, parameterised so as to correct or prevent the occurrence of polarisation inversion in the volume of the ferroelectric layer and/or at its interface with the support assembly (Sprt.Ens); and applying at least one first heat treatment to the structure (Strct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention comprises: a starting structure (Struct_0) designed to undergo separation by laser irradiation, comprising a substrate (Sub2), a transferred layer (TrLay), and a graphene oxide layer (GO, GO2) interposed between the substrate (Sub2) and the transferred layer (TrLay).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The present invention relates to a method for treating a substrate having a free surface made of a semiconductor material, in particular a single–crystal semiconductor material, comprising a method for stabilising the surface against the formation of terraces and/or beads, the method comprising: • forming a vitreous carbon layer (30) by a gas-phase carbon reaction on the surface at a temperature (T1) greater than 700°C, preferably greater than 800°C, and strictly lower than 1000°C, preferably lower than 950°C, and more preferably lower than 900°C; and • applying a heat treatment to the substrate after stabilising the surface, wherein the vitreous carbon layer (30) limits the reorganisation of the surface made of a semiconductor material in the form of terraces, the depositing of the carbon layer (30) and the heat treatment being carried out in the same furnace.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method of manufacturing a monocrystalline layer comprises the following successive steps: providing a donor substrate comprising a piezoelectric material of composition ABO3, where A consists of at least one element from among Li, Na, K, H, Ca; and B consists of at least one element from among Nb, Ta, Sb, V; providing a receiver substrate, transferring a layer called the “seed layer” from the donor substrate on to the receiver substrate, such that the seed layer is at the bonding interface, followed by thinning of the donor substrate layer; and growing a monocrystalline layer of composition A′B′O3 on piezoelectric material ABO3 of the seed layer, where A′ consists of a least one of the following elements Li, Na, K, H; B′ consists of a least one of the following elements Nb, Ta, Sb, V; and A′ is different from A or B′ is different from B.

IPC Classes  ?

• H10N 30/093 - Forming inorganic materials
• C01G 31/02 - Oxides
• C01G 33/00 - Compounds of niobium
• C01G 35/00 - Compounds of tantalum
• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/22 - Complex oxides
• C30B 29/30 - NiobatesVanadatesTantalates
• H01L 21/762 - Dielectric regions
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/076 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
• H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
• H10N 30/853 - Ceramic compositions

Abstract

lay-138lay4242laylay) of the starting composite structure (StartStruct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The present invention relates to a method of method of manufacturing a heterostructure for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of a piezoelectric material on or over the support substrate, removing a first peripheral portion of the block of a piezoelectric material and a first peripheral portion of the support substrate to obtain an exposed portion of the support substrate with a roughness with a root-mean-square height, Sq, in the range of 0.4 µm to 0.8 µm, thinning the block of a piezoelectric material after removal of the first peripheral portion of the block of a piezoelectric material to obtain a piezoelectric substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
• H10N 30/80 - Constructional details

Abstract

The invention relates to a method (100) for polishing a planar substrate (Waf) using a planarising and polishing machine comprising a support plate (Pl) provided with a polishing pad (Pol.Pad), a conditioning head (Cond.Head) for conditioning the polishing pad, and a head (Pol.Head) for holding the planar substrate (Waf) against the polishing pad, the method comprising a first step (110) of a first conditioning of the polishing pad (Pol.Pad) using the conditioning head (Cond.Head), wherein the planar substrate (Waf) is not subjected to any polishing operation; a second step (120) of a first polishing of the planar substrate (Waf), wherein the polishing pad is not subjected to any conditioning operation; and a third step (130) in which (i) a second polishing of the planar substrate (Waf) is performed and, simultaneously, (ii) a second conditioning of the polishing pad (Pol.Pad) is performed.

IPC Classes  ?

• B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
• B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces

Abstract

The invention relates to a semiconductor substrate (Sub) configured to allow laser separation of a layer of active material (ActMat), comprising: a support substrate (Sprt); an inorganic layer (Inorg) on the support substrate, wherein the inorganic layer is formed of a material selected from among Al2O3, TiO2, WO3, La2O3, LaAlO3 and TiN; an electrically insulating layer (Ins) on the inorganic layer; and the layer of active material (ActMat) on the electrically insulating layer, wherein the layer of active material is monocrystalline.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The invention relates to a method for assembling two substrates by molecular adhesion, at least one of the two substrates being provided with a dielectric surface layer. The method comprises activating the dielectric surface layer by exposure to a plasma formed between two electrodes (4a, 4b) of an activation chamber (3), for an activation period of 15 seconds to 2 minutes and during which a radiofrequency power is applied to one of the electrodes. The method comprises injecting into the activation chamber (3) a controlled flow of oxygen or nitrogen and a controlled flow of a gas comprising sulphur. The method is characterised in that the radiofrequency power has a density strictly greater than 1.1 W/cm^2.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a tiled donor substrate, the method comprising the following steps: a) providing an initial structure comprising a carrier substrate having a front face and a rear face, and a plurality of tiles made of a first monocrystalline material, wherein the tiles are arranged on the front face and are spaced apart from one another; b) forming a complementary layer by means of an additive manufacturing technique, wherein the complementary layer: - is arranged between the tiles, in contact with the front face of the carrier substrate; - is composed of a material, referred to as the second material, having a coefficient of thermal expansion matched to that of the first material; c) applying a mechanical and/or chemical-mechanical surface treatment to the complementary layer and to the tiles, in order to obtain the tiled donor substrate, wherein a front face of the substrate has a flat and continuous surface at which the plurality of tiles and the complementary layer are flush.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disc, with a grinding wheel, the abrasive grit of which has an average size greater than or equal to 10 μm, to obtain a surface-ground disc having at least one surface-ground face; c) applying a heat treatment to the surface-ground disc, at a temperature above a growth temperature of the raw disc employed in step a), and below a melting temperature of the polycrystalline material, so as to obtain an annealed disc, d) thinning the annealed disc, from the at least one surface-ground face, said thinning including fine grinding with a grinding wheel, the abrasive grit of which has an average size of less than 10 μm, so as to obtain the support substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disk in order to obtain a surface-ground disc having at least one surface-ground face, the rough grinding leading to the formation of a damaged superficial region on said surface-ground face; the damaged superficial region comprising a work-hardened superficial layer and a stressed underlying layer; c) applying a heat treatment to the surface-ground disc, the temperature and the duration of the heat treatment being defined so as to relax the stresses present in the stressed layer; step c) leading to the obtaining of an annealed disc comprising, at the at least one surface-ground face, a superficial first annealed layer, instead of the work-hardened layer, and an underlying second annealed layer, instead of the stressed layer; d) thinning the annealed disc, from the at least one surface-ground face, in order to remove the first annealed layer; step d) leading to the obtaining of the support substrate in which all or part of the second annealed layer is preserved.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for transferring a thin film (7) onto a final carrier (11), the thin film (7) and the final carrier (11) having different coefficients of thermal expansion. The method comprises transferring the thin film (7) onto an intermediate carrier (5) at a first bonding interface (IA1) and forming a dielectric surface layer (10) on the exposed face of the thin film (7). The method further comprises activating the dielectric surface layer (10) by exposing it to a plasma having a radiofrequency power density of strictly greater than 1.1 W/cm^2, then assembling the thin film (7) via the dielectric surface layer (10) to the final carrier (11) and thus defining a second bonding interface (IA2). Finally, the method comprises mechanically stressing the final carrier (11) and/or the intermediate carrier (5) to remove the intermediate carrier (5) from the thin layer (7) at the first bonding interface (IA1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a substrate, according to which an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101) is polymerised at a polymerisation site, and, after the polymerisation step, the heterostructure (107) is moved to another site. The method is characterised in that, during the polymerisation step, the heterostructure (107) is colder than an ambient temperature of the other site. The invention also relates to a substrate (119) comprising an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101), characterised in that, when the substrate (119) has a temperature between 20°C and 25°C, in particular between 20°C and 22°C, the adhesive layer (115) is under compression, in particular with respect to the handling substrate (100) in such a way as to induce a curve (BOW) of the substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention relates to a method for producing a stacked structure comprising a layer of semiconductor material bonded to a substrate, which comprises: producing a heterostructure by: • forming an intermediate layer made of a two-dimensional material on a growth substrate (1); patterning the intermediate layer with a plurality of openings to form a patterned intermediate layer (3); growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a handling substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from transferring the continuous epitaxial layer (4) from the heterostructure to the handling substrate (6).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, at least one assembly of the plurality of vias forming a pattern repeated along at least one direction of a main extension plane of the first layer and the second layer. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A method for assembly by molecular adhesion of two substrates each having a main face, at least one of the two substrates bearing a dielectric surface layer on its main face, comprises (a) contacting the main faces of the two substrates, then (b) initiating and propagating a bonding wave between the main faces of the two substrates to assemble them with one another. Prior to the contacting of the main faces, sulfur is introduced into the dielectric surface layer at a dose of more than 3.0 E13 at/cm^2 into this layer. A joined structure is obtained via the method.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A piezoelectric-on-insulator (POI) substrate comprises a support substrate, in particular, a silicon-based substrate, a piezoelectric layer, in particular, a layer of lithium tantalate or lithium niobate, a dielectric layer, in particular, a layer of silicon oxide, sandwiched between the piezoelectric layer and the support substrate, and a trapping structure sandwiched between the dielectric layer and the support substrate. The trapping structure comprises at least two trapping layers that are based on different materials. A particular method may be employed for producing such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H10N 30/00 - Piezoelectric or electrostrictive devices
• H10N 30/03 - Assembling devices that include piezoelectric or electrostrictive parts
• H10N 30/853 - Ceramic compositions

Abstract

A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, each via having at least one transverse dimension less than or equal to 30 μm. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

The invention relates to a method for preparing a carrier (1) for a composite substrate (S), which method comprises forming a superficial porous layer (P) on a first face (1c) of the carrier (1), and dispensing a viscous solution comprising a solvent and a precursor of a filler material on the first face (1c) of the carrier (1) so as to absorb at least some of the viscous solution in open pores of the superficial porous layer (P). In a fourth step, the carrier (1) is heat-treated to transform the viscous solution present in the open pores in order to fill the open pores with the filler material.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. After transferring the monocrystalline semiconductor layer, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A method for fabricating a microelectronic device includes: producing a structure with a support provided with a semiconductor layer of a first level of components and another semiconductor layer of a second level, the other semiconductor layer including a lower sublayer contacting the insulating layer and an upper sublayer disposed on the lower sublayer, one of the lower and upper sublayers made from crystalline material while another of the lower and upper sublayers made from amorphous material; forming a transistor gate block on the semiconductor layer; forming, on either side of the gate block, by implanting dopants in the semiconductor layer, doped regions on either side of a semiconductor region facing the gate block for accommodating a channel of the transistor; and implementing heat treatment to recrystallize the second semiconductor sublayer while using the first semiconductor sublayer as a start region of a crystalline front while activating the dopants.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 62/40 - Crystalline structures
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A substrate for a power or radiofrequency electronic device includes a self-supporting support substrate made of polycrystalline silicon carbide and a surface layer of monocrystalline silicon carbide that extends over a front face of the support substrate. The support substrate has at least one porous portion extending from a rear face of the support substrate. The porous portion has a degree of porosity of greater than 5%.

IPC Classes  ?

• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/66 - High-frequency adaptations
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method for manufacturing a structure comprising at least two chips on a receiver substrate comprises: forming a pseudo-donor substrate by placing at least one tile of at least one donor substrate on a support substrate; bonding the pseudo-donor substrate to a receiver substrate via the tiles so that each tile at least partially covers at least two different zones of interest of the receiver substrate; transferring a portion of the tiles to the receiver substrate; at least one step of chemical-mechanical polishing of the tiles of the pseudo-donor substrate and/or of the tile portions transferred to the receiver substrate; after the at least one step of chemical-mechanical polishing, a removal of material from the tile portions so as to divide each tile portion into at least two chips each arranged on a respective zone of interest.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The invention relates to a method for direct bonding between two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide; (b) depositing a specific compound on the first bonding surface made of hydrophilic silicon oxide, the specific compound being an organic compound consisting of a basic functional group and substituents of the basic functional group, each substituent being a hydrophobic group; (c) bringing the first bonding surface made of hydrophilic silicon oxide, on which the specific compound has been deposited, into contact with the second bonding surface made of hydrophilic silicon oxide, so as to adhere the first substrate to the second substrate.

IPC Classes  ?

• C09J 5/00 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers
• C09J 5/02 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
• C09J 5/06 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first hydrophilic silicon oxide bonding surface and a second hydrophilic silicon oxide bonding surface; (b) depositing a specific compound on the first hydrophilic silicon oxide bonding surface, the specific compound being derived from the ammonia molecule or the ammonium ion by at least the substitution of a hydrogen atom with a hydroxyl -OH group and/or an amino -NH2 group, the specific compound not comprising carbon atoms; and (c) bringing the first hydrophilic silicon oxide bonding surface on which the specific compound has been deposited into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: a) providing a first substrate and a second substrate comprising, respectively, a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide, b) adding fluoride ions to the first hydrophilic silicon oxide bonding surface; c) bringing the first hydrophilic silicon oxide bonding surface into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate, by way of the fluoride ions at the bonding interface.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), wherein the first direction (13a) is opposite to the second direction, and wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17al to 17a3 and 17bl to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n of the substrate surface.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

A piezoelectric-on-insulator (POI) substrate comprises: a carrier substrate, in particular, a substrate based on silicon; a piezoelectric layer, in particular, a layer of lithium tantalate or of lithium niobate; a dielectric layer, in particular, a layer of silicon oxide, sandwiched between the piezoelectric layer and the substrate; a trapping structure sandwiched between the dielectric layer and the carrier substrate. The trapping structure comprises at least two trapping layers, which layers are separated each time by a dielectric intermediate layer. A method is used for producing such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

Abstract

A method for transferring a thin film onto a support substrate comprises implanting into a donor substrate light species including co-implantation of hydrogen ions at a first dose and a first implantation energy, and helium ions at a second dose and a second implantation energy. Hydrogen ions are also locally implanted at a third dose and a third energy to form an overdosed local region in a buried fragile plane formed by the implanted ions. The donor substrate and the support substrate are assembled by direct bonding to form a bonded structure, and a fracture heat treatment is applied to the bonded structure so as to induce spontaneous separation along the buried fragile plane. The separation leads to the transfer of a thin film from the donor substrate onto the support substrate. The overdosed local region of the buried fragile plane constitutes a starting point for the separation.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a method of manufacturing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of piezoelectric material on or over the support substrate, wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate, chemical-mechanical polishing, CMP, the block of piezoelectric material to obtain a piezoelectric substrate and implanting a species into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. The CMP is performed by means of a CMP pad comprising a sub pad with a hardness of more than 45 shore A.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of refreshing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing the donor substrate to be refreshed comprising a support substrate and a first piezoelectric substrate formed over the support substrate comprising or consisting of one of lithium tantalate and lithium niobate, wherein the first piezoelectric substrate is a second piezoelectric substrate from which a piezoelectric layer has been transferred to a target substrate and chemical-mechanical polishing, CMP, the first piezoelectric substrate to obtain a refreshed donor substrate comprising a refreshed piezoelectric substrate, wherein the CMP comprises removing a layer of the first piezoelectric substrate with a thickness of at most 2 µm, in particular, at most 1.2 µm.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of manufacturing a Piezoelectric on Insulator, POI, structure, comprising providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or consists of one of lithium tantalate and lithium niobate, transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, and polishing the piezoelectric layer transferred to the target substrate with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percent of the amorphous silicon in the range of 4 to 18.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The invention relates to a method for manufacturing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of tiles (1) arranged at a distance from one another on a support substrate (3), comprising the steps of: - arranging, on the support substrate (3), said tiles (1) and an intermediate substrate (2) comprising a plurality of through-openings (20), such that each tile (1) extends into a respective through-opening (20) of the intermediate substrate, and - performing chemical-mechanical polishing of the tiles (1) arranged in the openings of the intermediate substrate.

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

The invention relates to a method for transferring chips onto a receiver substrate from tiles arranged on a support substrate, comprising: - forming a substrate (10), referred to as the pseudo-donor substrate, comprising the support substrate (2) and the tiles (1), wherein two adjacent tiles are spaced apart by a first distance (d1), - carrying out chemical mechanical polishing on the tiles, - forming a weakened zone in at least one portion of the tiles so as to delimit a respective chip, - bonding the pseudo-donor substrate to the receiver substrate via the tiles, - detaching the tiles along the weakened zone so as to transfer a respective chip onto the receiver substrate, two adjacent chips being spaced apart by a second distance greater than the first distance (d1), - before the bonding step, locally roughening the surface of the tiles and/or the receiver substrate to make regions of the surface unsuitable for bonding, so as to prevent the chips from being transferred in said regions.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for transferring a thin film onto a support substrate, which comprises: providing a bonded assembly that comprises a donor substrate and the support substrate, assembled by direct bonding at their respective front faces, following a bonding interface, the bonded assembly having a local unbonded area within this bonding interface, the donor substrate further comprising a buried brittle plane; separating along the buried brittle plane, initiated at the local unbonded area after microcrack growth in said plane by thermal activation, the separation resulting in the transfer of a thin film from the donor substrate to the support substrate. The method is characterised in that the local unbonded area is generated solely by a roughened area, produced deliberately on at least one of the front faces of the donor and support substrates prior to assembly, free of topology and having a predetermined roughness with an amplitude of between 0.5 nm RMS and 60.0 nm RMS.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a structure (Strc) capable of forming a quantum device, comprising: a silicon carrier substrate (Car); a first layer (Si-L1) of silicon isotope 28Si; a layer (Ox) of silicon oxide; a second layer (Si-L2) of silicon isotope 28Si, wherein the structure is formed by the carrier substrate (Car), the first layer (Si-L1) of silicon isotope 28Si, the layer (Ox) of silicon oxide, and the second layer (Si-L1) of silicon isotope 28Si, stacked in this order, wherein the first layer (SiL1) and the second layer (Si-L2) of silicon isotope 28Si are each made up of at least 99.92% of silicon isotope 28Si.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of first blocks (1) arranged at a distance from one another on a carrier substrate (3), wherein the method comprises: - arranging, on the carrier substrate (3), the first blocks (1) and a plurality of second blocks (2) arranged between the first blocks (1) such that each edge of each first block (1) faces at least one second block (2), wherein the first blocks (1) comprise a first material and the second blocks (2) comprise a second material different from the first material; and - chemical-mechanical polishing of the first and second blocks (1, 2).

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

A method for correcting the thickness of a piezoelectric layer arranged on a piezoelectric-on-insulator substrate comprises: measuring the thickness of at least one intermediate layer located between the piezoelectric layer and a carrier substrate; measuring the thickness of the piezoelectric layer; based on the measurements of the thickness of the at least one intermediate layer and of the piezoelectric layer and on a numerical model of at least one property of the piezoelectric layer as a function of a plurality of pairs of thicknesses of the piezoelectric layer and of the at least one intermediate layer, computing a thickness correction for the piezoelectric layer with a view to obtaining a target value for each property; and applying the thickness correction to the piezoelectric layer using a milling process in a topographically discriminating manner.

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

A method for producing a semiconductor-on-insulator structure comprises the steps of: —joining a support substrate with a donor substrate, the support substrate having an electrical resistivity greater than or equal to 500 Ω·cm and containing interstitial nitrogen and interstitial oxygen, the initial concentration of interstitial oxygen in the support substrate being between 15 and 25 old ppma, the donor substrate including a semiconductor layer, an electrically insulating layer being at the interface between the support substrate and the donor substrate; and—transferring the semiconductor layer onto the support substrate, the method further comprising a nucleation step comprising a heat treatment in order to precipitate part of the oxygen and nitrogen so as to form nuclei of oxygen and nitrogen precipitates, and a stabilization step comprising a heat treatment in order to grow the nuclei to a size of between 10 and 50 nm.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Abstract

A piezoelectric-on-insulator substrate comprises a support substrate having a first acoustic impedance, a piezoelectric layer, especially a layer of lithium tantalate, lithium niobate, aluminum nitride, lead zirconate titanate, langasite or langatate, a dielectric layer having a second acoustic impedance and sandwiched between the piezoelectric layer and the support substrate, an intermediate layer positioned between the support substrate and the dielectric layer. The intermediate layer is a layer having a variable composition, in particular along its thickness, such that the acoustic impedance of the intermediate layer varies, in particular gradually, between the values of the first and the second acoustic impedances. The present disclosure also relates to a method for producing such a piezoelectric-on-insulator substrate and also to a surface acoustic wave device comprising such a piezoelectric-on-insulator substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

Abstract

The invention relates to a method for producing a SOI structure, comprising the following steps: a) providing an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to standard ASTM'79 and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a carrier substrate for the SOI structure after having undergone the subsequent step b); b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on a front face, of a silicon oxide layer other than optionally a native oxide layer, the sequence consisting of: - a first heat treatment defined by a plateau at a temperature higher than 1200°C and lower than 1280°C and with a duration of between 1 second and 60 seconds, by a temperature decrease ramp of between 10°C/s and 70°C/s, and by an argon or argon-hydrogen atmosphere; followed by - a second heat treatment defined by a plateau at a temperature of between 900°C and 1100°C, without an intermediate step before this temperature, under a neutral or oxidising atmosphere, in order to form a carrier substrate comprising: - a stripped surface layer, with a thickness greater than 40 μm and having a micro-defect concentration (BMD) of less than 108/cm3, and - an enriched deep layer, under the stripped surface layer, having a micro-defect concentration (BMD) of between 2.108/cm3and 5.1010/cm3. The invention also relates to a carrier substrate and a SOI structure including the carrier substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions

Abstract

Disclosed is a carrier (100) intended to be split by laser radiation, comprising a carrier substrate (Sprt); on the carrier layer, a splitting layer (Sep) formed from an inorganic material of thickness between 10 nm and 100 nm; and a layer (Brg) forming a Bragg mirror, the splitting layer (Sep) being interposed between the carrier substrate (Sprt) and the layer (Brg) forming the Bragg mirror, the carrier being configured in such a way that the carrier substrate is substantially transparent to laser radiation of a certain wavelength, the layer forming the Bragg mirror is substantially reflective with respect to the laser radiation, and the splitting layer (Sep) can absorb some of the laser radiation, such that the carrier can be split into two parts level with the splitting layer (Sep) under the action of the laser radiation.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

CarCarDonDon) respective overcoat layers (Cap1, Cap2) on the two superlattices (Stck1, Stck2); and assembling (660) the two superlattices (Stck1, Stck2) by placing their respective overcoat layers (Cap1, Cap2) in contact, so that together they form a bonding layer, the first overcoat layer (Cap1) and the second overcoat layer (Cap2) each having a thickness of less than 2 nm.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for controlling the quality of a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the method comprising: a) inspection of a free surface (10a) of the thin layer (10) using a technique coupling visible-light confocal microscopy and photoluminescence imaging, making it possible to detect defects, called secondary defects, b) preliminary identification of the secondary defects, by similarity, on the basis of their visible-light image, by virtue of an image recognition algorithm trained on various types of defects such as holes, bubbles, scratches, and defects of crystalline origin; at the end of step b), each secondary defect is associated with one identified type of defect, with a certain level of similarity, c) final classification of at least certain secondary defects by application of the following first conditions: - if the level of similarity associated with a secondary defect is greater than a high level, said secondary defect is definitively classified in the identified type of defect, - if the level of similarity associated with the secondary defect is between a low level and the high level, the photoluminescence image of said defect is analysed; if the secondary defect is associated with a labelled type of PL defect, said secondary defect is definitively classified in the identified type of defect, - in all other cases, the secondary defect is definitively classified as not a defect.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• C30B 29/36 - Carbides
• G01N 21/64 - FluorescencePhosphorescence
• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer

Abstract

The invention relates to a process for fabricating a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the process comprising the following steps: 1) providing at least one donor substrate made of single-crystal silicon carbide, having a front side and a rear side, the front side potentially having defects, called primary defects; 2) controlling the quality of the - at least one - donor substrate by means of a photoluminescence-based imaging technique, so as to extract a map of the front side, called the first map, cataloguing the primary defects identified as being of micro-hole type, of the complex type consisting of star stacking faults or of point-defect type; 3) transferring a thin layer, obtained from a surface layer of the - at least one - donor substrate, onto a carrier substrate made of polycrystalline silicon carbide, in order to obtain a composite structure and a residual donor substrate; 4) inspecting a free surface of the thin layer of the composite structure by means of a technique for inspecting for defects by means of scattering of an ultraviolet laser beam, so as to extract a map of the free surface, called the second map, cataloguing defects called secondary defects; 5) grading the composite structure, this including a comparison of the first map and of the second map.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01N 21/64 - FluorescencePhosphorescence
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• G01N 21/84 - Systems specially adapted for particular applications

Abstract

CarDonDon) a second superlattice (Stck2) on a second substrate by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers; and assembling (560) the second superlattice (Stck2) on the first superlattice (Stck1) at a dielectric separation layer which separates the first superlattice (Stck1) and the second superlattice (Stck2) and keeps them attached to one another, the first superlattice (Stck1), the separation layer and the second superlattice (Stck2) being stacked in this order.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

CarDonDonDon) a weakening plane (Imp) in the second substrate; assembling (560) the seed layer (Init) on the first superlattice (Stck1) at a dielectric separation layer that separates the first superlattice (Stck1) and the seed layer (Init) and keeps them attached to each other; removing (570A) a portion of the second substrate by fracturing the second substrate at the weakening plane (Imp) after the assembly step (560); exposing (570B) the seed layer (Init) after the step (570A) of fracturing the second substrate; and forming (580) the second superlattice (Stck2) on the exposed seed layer (Init).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

A method of manufacturing a donor substrate for the transfer of a piezoelectric layer onto a support substrate comprises providing a handling substrate and providing a piezoelectric substrate. A polymer layer is deposited on the handling substrate or the piezoelectric substrate. An intermediate layer is formed on a free surface of the piezoelectric substrate, and the piezoelectric substrate is assembled on the handling substrate such that the intermediate layer formed on the piezoelectric substrate is between the polymer layer and the piezoelectric substrate to form the donor substrate. A donor substrate may be manufactured by such a method, and such a donor substrate may be used for transferring a piezoelectric layer to another substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

A method of manufacturing a donor substrate for the transfer of a piezoelectric layer onto a support substrate comprises providing a handling substrate and a piezoelectric substrate. A surface activation treatment is carried out on the surface of the piezoelectric substrate to form an activated surface on the piezoelectric substrate. A polymer layer is deposited on the activated surface of the piezoelectric substrate or on the handling substrate. The piezoelectric substrate is then assembled on the handling substrate in such a way that the polymer layer is between the activated surface of the piezoelectric substrate and the handling substrate. The donor substrate may be used to transfer a layer of piezoelectric material from the donor substrate onto a support substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention relates to a carrier (1) for a composite substrate (S). The carrier comprises a base substrate and a trapping layer (3a) made of polycrystalline silicon arranged on the base substrate (2). The trapping layer has electric traps of a first type having an activation energy of 0.383 eV within a tolerance of 0.008 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2. The trapping layer has electrical traps of a second type having an activation energy of 0.428 eV within a tolerance of 0.016 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

moynuumoynuuu) are determined, prior to carrying out steps b), c) and d), on the basis of a model that relates them to an etched mean thickness of the surface layer and to a mean etching non-uniformity defined by the difference between an etched mean thickness in a central region and in a peripheral region of the surface layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing an active layer of monocrystalline silicon carbide by homoepitaxy on a composite structure, the method comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide extending in a main plane and arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a first thickness along an axis normal to the main plane; 2) forming a local barrier in or on the growth layer, the local barrier extending at a distance from and along the peripheral perimeter, and corresponding to a physical discontinuity of the growth layer chosen from: - a proeminent relief induced by the presence of a material on the growth layer, said material being different from that of the growth layer, - a recessed relief corresponding to an etched region of the growth layer, or - an amorphous domain or domain of crystallinity different from the rest of the growth layer, the local barrier having a thickness, along the axis normal to the main plane, less than the first thickness; 3) epitaxial growth of the active layer on the growth layer.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a substrate and the production method therefor for producing a bidirectional switch, the method comprising: - transferring, to the front face of a carrier substrate, a first seed layer (21) made of a wide-bandgap polar semiconductor material; - transferring, to the rear face of the carrier substrate, a second seed layer (22) made of the wide-bandgap polar semiconductor material, wherein these transfers are carried out so as to expose a surface of a first type (F1) of the first seed layer (21) and a surface of the first type (F1) of the second seed layer (22), and wherein a surface of a second type (F2) of the first seed layer (21) and a surface of the second type (F2) of the second seed layer (22) are at the interface with the front face and the rear face of the support substrate, respectively.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H10D 12/01 - Manufacture or treatment
• H10D 30/01 - Manufacture or treatment
• H10D 30/66 - Vertical DMOS [VDMOS] FETs
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A method is used to fabricate a double semiconductor-on-insulator structure comprising, from a back side to a front side of the structure: a handle substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. The method comprises:—a first step of formation of an oxide layer on the front and back sides of the handle substrate, to form the first electrically insulating layer and an oxide layer on the back side of the handle substrate, —a first step of layer transfer, to transfer the first single-crystal semiconductor layer, —a second step of formation of an oxide layer, to form the second electrically insulating layer, and —a second step of layer transfer, to transfer the second single-crystal semiconductor layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Abstract

A method of manufacturing a composite structure including a thin layer of a first monocrystalline material arranged on a carrier substrate, the method including: providing an initial substrate of a second polycrystalline material; and depositing, by spin coating, at least on one front surface of the initial substrate, a layer of polymer resin including preformed 3D carbon-carbon bonds; performing a first annealing step at a temperature between 120° C. and 180° C. on the initial substrate provided with the polymer resin layer, to form a layer of cross-linked polymer resin; and performing a second annealing step at a temperature greater than 600° C., in a neutral atmosphere, to convert the layer of cross-linked polymer resin into a glassy carbon film. a composite structure includes a thin layer of a first monocrystalline material on a carrier substrate, which includes a glassy carbon film on an initial substrate of a second polycrystalline.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• C30B 29/36 - Carbides

Abstract

A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A method for fabricating a double semiconductor-on-insulator structure comprising the steps of: providing a first donor substrate and a handle substrate, forming a weakened zone in the donor substrate so as to delimit a first semiconductor layer to be transferred, bonding the first donor substrate to the handle substrate, a first electrically insulating layer being at the interface, and detaching at the weakened zone, treating the surface of the first transferred semiconductor layer comprising: a rapid thermal annealing, a thermal oxidation followed by a deoxidation, a smoothing heat treatment at a temperature of above 1000° C. in a non-oxidizing atmosphere, chemical-mechanical polishing, providing a second donor substrate of a second semiconductor layer to be transferred, transferring the second semiconductor layer, a second electrically insulating layer being at the interface.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A method and device for monitoring the weakening of an interface between a layer and a substrate while a weakening anneal is being carried out. The method includes illuminating the first face of the substrate layer assembly with a monochromatic light beam in a first direction; measuring the intensity of the light beam scattered by the substrate layer assembly in at least a second direction, the second direction forming a non-zero angle with the first direction; and determining a state of weakening of the interface from the intensity.

IPC Classes  ?

• G01N 21/47 - Scattering, i.e. diffuse reflection
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method of manufacturing a polycrystalline silicon carbide wafer includes the following stages: heat treatment of a polycrystalline silicon carbide slab; thinning of the polycrystalline silicon carbide slab, the thinning comprising a correction, by withdrawal of material from the polycrystalline silicon carbide slab, of a deformation brought about by the heat treatment.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The present invention relates to a method for producing a composite structure, the method comprising: (a) forming a temporary substrate (3') comprising a carrier substrate (3), wherein a plurality of tile portions (P'1-P'3) or a layer of interest (20) made of a first material are arranged on the carrier substrate (3); (b) forming a removable interface (5) arranged between the carrier substrate (3) and the tile portions or the layer of interest, or in or on the tile portions or the layer of interest; (c) assembling the temporary substrate (3') with a receiver substrate (4) made of a second material that is different from the first material, via the tile portions or the layer of interest; and (d) removing the carrier substrate (3) by dismantling the removable interface (5) so as to transfer at least one portion of the tile portions (P'1-P'3) or of the layer of interest (20) to the receiver substrate (4) to form the composite structure.

IPC Classes  ?

• H01L 21/6835 -
• H01L 21/76254 -
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/762 - Dielectric regions

Abstract

22111211 = 2.85×1018cm-322 = 5.40×1020cm-3, - an interface zone, between the carrier substrate and the working layer, comprising nodules and regions of direct contact between the working layer and the carrier substrate, the nodules comprising a metal or semiconductor material other than silicon carbide, the interface zone having an average resistivity of less than or equal to 0.01 mohm.cm2, a dopant concentration profile along a thickness of the semiconductor structure: - being in the form of a step, and - being devoid of a doping peak in the interface zone, or - exhibiting a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration to within plus or minus 10%. The invention also relates to a process for fabricating such a semiconductor structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The present invention relates to an elastic wave device comprising a piezoelectric material (3) with first domains (3a1, 3a2) of a first polarization direction (13a) and second domains (3b1, 3b2) with a second polarization direction (13b), the first direction being opposite to the second direction, in which the first and second domains are periodically alternated along a direction, called periodic direction, perpendicular to the surface normal of the piezoelectric material, and a pair of interdigitated comb electrodes (15a, 15b), the respective comb teeth (17a1, 17a2, 17b1, 17b2) of which extend mainly in the periodic direction, and to a method for manufacturing such an elastic wave device.

IPC Classes  ?

• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

TTFF) of formation of the carbon layer.

IPC Classes  ?

• C30B 29/36 - Carbides
• C30B 33/02 - Heat treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of manufacturing a structure comprising at least two tiles on a substrate comprises: —placing, on a support substrate, at least two tiles, the tiles being arranged on the support substrate in an incorrect distribution and/or geometry compared with a target distribution and/or geometry; —forming a mask comprising a protective film partially covering the tiles in a pattern defining the target distribution and/or geometry and at least one opening extending around the protective film; and —etching at least one tile through the opening in the mask so as to correct the arrangement of the tiles according to the target distribution and/or geometry.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• C30B 33/08 - Etching

Abstract

A method for transferring a piezoelectric layer onto a support substrate comprises:—providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate,—forming a weakened zone in the piezoelectric substrate so as to delimit the piezoelectric layer to be transferred,—providing the support substrate,—forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate,—bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and-fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.

IPC Classes  ?

• H10N 30/057 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by stacking bulk piezoelectric or electrostrictive bodies and electrodes
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The invention relates to a front-side imager comprising in succession: a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises, between the carrier substrate and the first electrically insulating layer: a second electrically insulating separating layer, and a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 27/146 - Imager structures

Abstract

A method of manufacturing a semiconductor structure, which includes a support substrate of polycrystalline silicon carbide and an active layer of single-crystal silicon carbide, involves: the formation of a support substrate including a stack of a first layer of polycrystalline SiC mainly of polytype 3C and of a second layer of polycrystalline SiC mainly of polytype 4H and/or 6H, the bonding of a donor substrate including an active layer of single-crystal SiC of polytype 4H or 6H to a face of polytype 4H and/or 6H of the support substrate, and the transfer of the active layer onto the support substrate.

IPC Classes  ?

• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.

IPC Classes  ?

• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

A semiconductor structure includes a Silicon-On-Insulator substrate and an epitaxial III-N semiconductor layer stack on top of the Silicon-On-Insulator substrate. The Silicon-On-Insulator substrate has a silicon base layer, an intermediate layer on top of the base layer, and a n-type doped silicon top layer on top of the intermediate layer. The intermediate layer includes a trap-rich layer and a buried insulator on top of a trap-rich layer. The epitaxial III-N semiconductor layer stack, which is on top of the Silicon-On-Insulator substrate, includes a first active III-N layer and a second active III-N layer on top of the first active III-N layer. A two-dimensional Electron Gas is located between the first active III-N layer and the second active III-N layer.

IPC Classes  ?

• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 21/762 - Dielectric regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

A method for manufacturing disassemblable substrates, comprising: (a) providing a first substrate comprising implanted species forming a flat implantation zone and a proximal surface; a second substrate comprising a surface; (b) forming a series of cavities on the proximal surface of the first substrate and/or on the surface of the second substrate; (c) assembling the first and second substrates (1, 2) by direct bonding; and (d) applying a heat treatment to weaken the flat implantation zone. Further, the series of cavities being arranged in such a way as to allow direct bonding between the first and second substrates during step (c); and prevent thermal initiation of the splitting of the weakened flat implantation zone at the end of step (d).

IPC Classes  ?

• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method for fabricating a donor substrate comprises the steps of A: providing a handle substrate, B: providing a target substrate, C: attaching the target substrate to the handle substrate, and D: rectifying, in particular, by grinding, the target substrate attached to the handle substrate, so as to form the donor substrate, the method being characterized in that a waiting time period of a predetermined duration is observed between step C and step D.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/853 - Ceramic compositions

Abstract

The invention relates to a process for transferring a thin layer to a carrier substrate, comprising: - joining a donor substrate (1) and the carrier substrate (2) by direct bonding of their respective front sides (1a, 2a) via a bonding interface (3), to form a bonded assembly (100) having an unbonded local region (31) within this bonding interface (3), the donor substrate (1) further comprising a buried fragile plane (11), - splitting along the buried fragile plane (11), the splitting being initiated in the unbonded local region (31) after growth of microcracks in said plane (11) by thermal activation, and leading to the transfer of a thin layer (10) from the donor substrate (1) to the carrier substrate (2). The process is noteworthy in that the unbonded local region (31) is generated by at least one rough region (31a) produced by scanning a laser beam over at least one of the front sides (1a, 2a) of the donor substrate (1) and carrier substrate (2) before they are joined, the scan covering an area of at least 100 microns by 100 microns and of at most 500 microns by 500 microns.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing a diamond substrate, or a III-V material substrate, for microelectronic applications, the method comprising: - bonding a plurality of monocrystalline diamond tiles or III-V material tiles (20) onto a carrier substrate (1), each tile being spaced apart from the adjacent tiles so as to expose a lateral surface (S2) of each tile; - epitaxially growing diamond or the III-V material from the lateral surface and the upper surface of each tile until a continuous layer (2) of monocrystalline diamond or III-V material is formed and extends over the plurality of tiles (20); - forming, by implanting atomic species, a weakened zone (21) in the continuous layer (2) of monocrystalline diamond or III-V material to define a surface layer (22) to be transferred; - bonding the continuous layer (2) of monocrystalline diamond or III-V material onto a receiver substrate (3); - detaching the continuous layer (2) of monocrystalline diamond or III-V material along the weakened zone (21) so as to transfer the surface layer (22) of monocrystalline diamond or III-V material onto the receiver substrate (3) to form the diamond or III-V material substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present disclosure relates to an intermediate substrate (10) for the manufacture of a semiconductor substrate, the intermediate substrate successively comprising: a a first semiconductor layer (2); b a first thermal barrier layer (5); c a support (13) comprising an absorption layer (3) configured to absorb laser radiation in a given wavelength range, the temperature of the absorption layer (3) increasing as it absorbs the laser radiation, and a separation zone (8) adjacent to the absorption layer (3) configured to thermally degrade due to the increase in temperature of the absorption layer, so as to separate at least part of the support (13) from the rest of the intermediate substrate (10).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 33/06 - Joining of crystals
• H01L 21/762 - Dielectric regions
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) directly disposed on the support (1a). At least one pFET structure is directly residing on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is directly residing on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and a nFET gate structure encapsulating each channel nanosheet of the second stack.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors

Abstract

A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

A method for fabricating a structure comprises preparing a first pseudo-substrate, and in-depth weakening the first pseudo-substrate by ion implantation at a certain depth in the first pseudo-substrate. The first pseudo-substrate is prepared by providing a single crystal substrate comprising a piezoelectric material; forming an oxide layer on a surface of the single crystal substrate; and transferring a piezoelectric layer of the single crystal substrate adjacent the oxide layer to a handle substrate to form the first pseudo-substrate. The method further comprises bonding the first pseudo-substrate to a substrate to provide an assembly, and separating the assembly at the ion-implanted depth of the first pseudo-substrate to form the structure and a second pseudo-substrate. The structure comprises at least a portion of the piezoelectric layer of the single crystal substrate on the substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties
• B32B 9/04 - Layered products essentially comprising a particular substance not covered by groups comprising such substance as the main or only constituent of a layer, next to another layer of a specific substance
• C30B 29/68 - Crystals with laminate structure, e.g. "superlattices"
• C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure
• C30B 33/06 - Joining of crystals
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

Abstract

A compact and robust encapsulation system for protecting a surface wave device comprises a SAW device and a sealing joint, which seals a second substrate to the base substrate of the SAW device so as to form a cavity, and an antenna connection means arranged outside the cavity on the encapsulation system.

IPC Classes  ?

• H03H 9/10 - Mounting in enclosures
• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The invention relates to a polycrystalline silicon carbide carrier for a substrate intended to accommodate a power semiconductor device. The carrier has a first face, referred to as the "front face", and a second face, referred to as the "rear face", and comprises a first surface layer arranged directly under the front face and having a resistivity higher than or equal to 1 ohm.cm and a second surface layer arranged directly under the rear face and having a resistivity strictly lower than 1 ohm.cm.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a donor substrate (1) for transferring a piezoelectric layer onto a support substrate, which comprises the following successive steps: • (a) providing a piezoelectric substrate (5) and a manipulation substrate (2); • (b) depositing a photo-polymerisable adhesive layer (6) on a main face of the manipulation substrate (2) or the piezoelectric substrate (5); • (c) bonding the piezoelectric substrate (5) with the manipulation substrate (2) via the adhesive layer (6) to form a heterostructure (7); • (d) irradiating the heterostructure (7) with a luminous flux to polymerise the adhesive layer (6); • (e) thermally treating the irradiated heterostructure (7); and • (f) thinning the piezoelectric substrate (5) by its face opposite the manipulation substrate (2), so as to form the donor substrate (1).

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks

Abstract

A semiconductor structure for optoelectronic applications; comprises a first layer made of a crystalline semiconductor, the layer being disposed on an intermediate layer including or adjacent to a direct-bonding interface, the intermediate layer being disposed on a second layer made of a crystalline semiconductor material. The intermediate layer is composed of a material that is different from those of the first and second layers, and the attenuation coefficient of which is lower than 100. The refractive index of the intermediate layer differs by less than 0.3 from the refractive index of at least one sub-layer of the first layer adjacent to the intermediate layer, and of at least one sub-layer of the second layer adjacent to the intermediate layer.

IPC Classes  ?

• H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Abstract

The invention relates to a final substrate (S) comprising, consecutively and in contact with one another, an upper layer (5) made of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electrical charge trapping layer (2) and a base substrate (3). The final substrate (S) has a curvature of less than 60 micrometres, preferably less than 40 micrometres. An exposed surface of the upper layer (5) has a roughness of less than 0.3 nm as a root mean square measurement over a field of 30 micrometres by 30 micrometres. The invention also relates to a method for preparing such a substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline SiC carrier substrate includes: forming a polycrystalline SiC layer on a donor substrate, at least a surface portion of which is made of single-crystal SiC; before or after forming the polycrystalline SiC layer, implanting ionic species into the surface portion of the donor substrate, so as to form a plane of weakness delimiting a thin single-crystal SiC layer to be transferred; after the implanting of the ionic species and the forming of the polycrystalline SiC layer, bonding the donor substrate and the polycrystalline SiC carrier substrate, the polycrystalline SiC layer being at the bonding interface; and detaching the donor substrate along the plane of weakness, so as to transfer the polycrystalline SiC layer and the thin single-crystal SiC layer onto the polycrystalline SiC carrier substrate.

IPC Classes  ?

• C30B 33/06 - Joining of crystals
• C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
• C30B 29/36 - Carbides
• C30B 33/02 - Heat treatment

Abstract

The invention relates to a process comprising:  providing a heterostructure comprising a growth substrate (1), an interlayer (2) of two-dimensional material and an epitaxial semiconductor layer (3);  providing a rigid substrate (4) comprising a weakened plane (5);  producing a first assembly by bonding the rigid substrate to the heterostructure, the first side (F) and the epitaxial layer (3) being at the bonding interface;  splitting the first assembly at the interlayer (2) of two-dimensional material, so as to obtain a second assembly resulting from transfer of the epitaxial layer (3) from the heterostructure to the rigid substrate (4);  producing a third assembly by bonding the second assembly to a target substrate (7), the epitaxial layer (3) being at the bonding interface;  splitting the third assembly along the weakened plane (5) of the rigid substrate (4).

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 μm; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 μm; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.

IPC Classes  ?

• H01L 21/763 - Polycrystalline semiconductor regions
• H01L 21/762 - Dielectric regions
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form

Abstract

The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/04 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/082 - Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
• H10N 30/853 - Ceramic compositions
• H10N 35/01 - Manufacture or treatment

Abstract

The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
• H03H 9/00 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

A method for preparing a support substrate having a charge-trapping layer includes introducing a monocrystalline silicon base substrate into a chamber of deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with a carrier gas, performing the following successive steps: forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period; and forming a polycrystalline silicon charge-trapping layer directly on the dielectric layer by introducing a precursor gas containing silicon into the chamber over a second time period, subsequent to the first time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature strictly between 1010° C. and 1200° C.

IPC Classes  ?

• H01L 21/763 - Polycrystalline semiconductor regions
• H01L 21/762 - Dielectric regions
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

A structure comprises a carrier substrate, a plurality of tiles on the carrier substrate, and a plurality of monocrystalline layers of AlN material on the plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material. Each monocrystalline layer of AlN material of the plurality of monocrystalline layers of AlN material is disposed on a respective tile of the plurality of tiles. Also disclosed is substrate for epitaxial growth of monocrystalline layers of AlN material. The substrate comprises a carrier substrate and a plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material.

IPC Classes  ?

• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 23/02 - Epitaxial-layer growth
• C30B 29/36 - Carbides
• C30B 29/40 - AIIIBV compounds
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof