An apparatus for reducing lag includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a gate control circuit configured to control a gate voltage of the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and an area between the gate and the drain.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
2.
GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF
An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.
A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure (150) comprising a barrier layer (156) on a channel layer (154), first and second source/drain regions (164, 166) in the semiconductor layer structure, first and second source/ drain contacts (124, 126) on the respective first and second source/ drain regions, and a longitudinally-extending gate finger (122) that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/ drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/ drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A packaged semiconductor device includes a first bond pad (225), a second bond pad (165, 165'), a first bond wire that includes a first end bonded to the first bond pad (225) and a second end bonded to the second bond pad (165, 165'), and a second bond wire that includes a first end that is electrically connected to the first bond pad (225) and a second end that is electrically connected to the second bond pad (165, 165'). The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad (225) and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.
RF transistor amplifiers an RF transistor amplifier die having a semiconductor layer structure, an interconnect structure having first and second opposing sides, wherein the first side of the interconnect structure is adjacent a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement, and one or more circuit elements on the first and/or second side of the interconnect structure.
H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
9.
POWER SEMICONDUCTOR DEVICES HAVING MULTILAYER GATE DIELECTRIC LAYERS THAT INCLUDE AN ETCH STOP/FIELD CONTROL LAYER AND METHODS OF FORMING SUCH DEVICES
A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/336 - Field-effect transistors with an insulated gate
A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed.
RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
12.
MULTI-STAGE DECOUPLING NETWORKS INTEGRATED WITH ON-PACKAGE IMPEDANCE MATCHING NETWORKS FOR RF POWER AMPLIFIERS
An electronic package houses one or more RF amplifiers (18, 18a, 18b). At least one of an input or output impedance matching network (16, 16a, 16b, 20, 20a, 20b) integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an RF amplifier (18, 18a, 18b), includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the RF amplifier (18, 18a, 18b) at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching networks (16, 16a, 16b, 20, 20a, 20b) may be shared, and may be connected anywhere along the multi-stage decoupling network.
A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
14.
METHODS FOR PILLAR CONNECTION ON FRONTSIDE AND PASSIVE DEVICE INTEGRATION ON BACKSIDE OF DIE
An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
An amplifier includes an input matching network; at least one transistor; an input lead coupled to the at least one transistor; a ground terminal coupled to the transistor; an output lead coupled to the at least one transistor; an output matching circuit coupled to the output lead and to the at least one transistor; and a baseband impedance enhancement circuit having at least one reactive element coupled to the input matching network. The baseband impedance enhancement circuit is configured to reduce resonances of a baseband termination.
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 1/10 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of amplifying elements with multiple electrode connections
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
16.
RF AMPLIFIERS HAVING SHIELDED TRANSMISSION LINE STRUCTURES
RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
Power switching devices include a semiconductor layer structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.
Power switching devices include a semiconductor layer structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that has a longitudinal axis that extends in a first direction on the semiconductor layer structure, the gate fingers spaced apart from each other along a second direction, and a gate connector having a longitudinal axis that extends in the second direction, the gate connector connected to the gate fingers of the plurality of unit cell transistors.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
19.
TRENCHED POWER DEVICE WITH SEGMENTED TRENCH AND SHIELDING
A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.
RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H03F 1/00 - Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H01L 23/00 - Details of semiconductor or other solid state devices
A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.
An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
25.
STACKED RF CIRCUIT TOPOLOGY USING TRANSISTOR DIE WITH THROUGH SILICON CARBIDE VIAS ON GATE AND/OR DRAIN
A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
26.
GROUP III NITRIDE-BASED RADIO FREQUENCY AMPLIFIERS HAVING BACK SIDE SOURCE, GATE AND/OR DRAIN TERMINALS
RF amplifiers are provided that include an interconnection structure (270) and a Group III nitride-based RF amplifier die (210) that is mounted on top of the interconnection structure. The Group III nitride- based RF amplifier die includes a semiconductor layer structure (230) A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal (222), a drain terminal (224) and a source terminal (226) are provided on a lower surface of the semiconductor layer structure that is adjacent the interconnection structure.
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
Synchronization for light emitting diode (LED) pixels in an LED display is provided so that one or more actions of all LED pixels are able to be initiated at the same time, or within a millisecond. LED displays and corresponding systems may include a controller that is configured for sending communication signals to one or more strings of LED pixels. Active electrical elements within each LED pixel may be configured to receive the communication signals, generate corresponding synchronization signals, and respond in a manner that is coordinated with all other LED pixels in a particular LED display. Failure mitigation of LED pixel failures within an LED string is provided where the controller is configured with bidirectional communication ports for communication with the LED string. In a failure mitigation process, the bidirectional communication ports may switch directions to provide communication signals to both sides of an LED string.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H05B 47/18 - Controlling the light source by remote control via data-bus transmission
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
A semiconductor die includes a drift region, an active region in the drift region, and an edge termination region surrounding the active region in the drift region. The drift region has a first doping type. The edge termination region includes a charge compensation region, a number of guard rings, and a counter doping region. The charge compensation region is in the drift region and has a second doping type that is opposite the first doping type. The guard rings are in the charge compensation region, have the second doping type, and a doping concentration that is greater than a doping concentration of the charge compensation region. The counter doping region is in the drift region and overlaps at least a portion of the charge compensation region. The counter doping region has the first doping type.
A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
30.
DISLOCATION DISTRIBUTION FOR SILICON CARBIDE CRYSTALLINE MATERIALS
Silicon carbide (SiC) wafers, SiC boules, and related methods are disclosed that provide improved dislocation distributions. SiC boules are provided that demonstrate reduced dislocation densities and improved dislocation uniformity across longer boule lengths. Corresponding SiC wafers include reduced total dislocation density (TDD) values and improved TDD radial uniformity. Growth conditions for SiC crystalline materials include providing source materials in oversaturated quantities where amounts of the source materials present during growth are significantly higher than what would typically be required. Such SiC crystalline materials and related methods are suitable for providing large diameter SiC boules and corresponding SiC wafers with improved crystalline quality.
e.ge.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor (22). In these embodiments, one or more processing steps required to form a conventional capacitor (12) are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT (10).
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
32.
CIRCUITS AND METHODS FOR CONTROLLING BIDIRECTIONAL CLLC CONVERTERS
A bidirectional power converter includes a first switch circuit coupled to a second switch circuit via a transformer, wherein the first switch circuit is configured to transfer power to the second switch circuit during a charging mode, the second switch circuit is configured to transfer power to the first switch circuit during a discharging mode, and the first switch circuit is configured to operate in a half bridge configuration during a first portion of the charging mode.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.
C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure
C30B 33/04 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
34.
SEMICONDUCTORS HAVING DIE PADS WITH ENVIRONMENTAL PROTECTION AND PROCESS OF MAKING SEMICONDUCTORS HAVING DIE PADS WITH ENVIRONMENTAL PROTECTION
A process of forming a device with a pad structure having environmental protection includes providing a semiconductor body portion, arranging a pad on the semiconductor body portion, providing at least one environment encapsulation portion at least partially on the pad, arranging a supplemental pad on the pad, and arranging the supplemental pad to include side surfaces that extend vertically above the at least one environment encapsulation portion. A device having a pad structure having environmental protection is also disclosed.
A device including a substrate, a passivation layer, a source, a gate, a drain, and the gate including at least one step portion. Where the at least one step portion is arranged within the passivation layer, the at least one step portion includes at least one first surface and at least one second surface, where the at least one first surface is connected to the at least one second surface, where the gate includes a third surface, and where the at least one step portion is connected to the third surface. A process is also disclosed.
Submount structures for light-emitting diode (LED) packages are provided. Submounts may include a base material that is configured to provide high thermal conductivity and a ceramic layer on the base material that is configured to provide high reflectivity for one or more LED chips that are mounted thereon. In certain aspects, the base material may include a ceramic base having a ceramic material that is different than a material of the ceramic layer. In certain aspects, submounts may also include additional ceramic layers configured to provide high reflectivity. In certain aspects, LED packages include electrical traces that are arranged either on one or more ceramic layers or at least partially embedded within one or more ceramic layers. The arrangement of such ceramic layers may provide increased reflectivity in areas where it may be difficult for other reflective materials to be present, such as gaps formed between tightly spaced electrical traces.
A pixelated-LED chip includes an active layer with active layer portions, segregated by streets, that are configured to illuminate different light-transmissive substrate portions to form pixels. A light extraction surface of each substrate portion includes protruding features and light extraction surface recesses that may be formed by sawing. Underfill material may be provided between a pixelated-LED chip and a mounting surface, as well as between pixels and between anodes and cathodes thereof. Certain implementations provide light extraction surface recesses that are non-parallel to each street defined through the active layer. Certain implementations provide light extraction surface recesses that are non-aligned with (e.g., non-parallel to) anode-cathode boundaries of each anode-cathode pair. Such arrangements reduce a likelihood of cracking in portions of a pixelated-LED chip. Methods for fabricating pixelated-LED chips are also provided.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/24 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
38.
STEPPED FIELD PLATES WITH PROXIMITY TO CONDUCTION CHANNEL AND RELATED FABRICATION METHODS
A transistor includes a semiconductor layer structure (24), a source electrode (30) and a drain electrode (30) on the semiconductor layer structure, a gate (32) on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate (33). The field plate includes a first portion (33a) adjacent the gate and a second portion (33b) adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion (32a) of the gate. Related devices and fabrication methods are also discussed.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
39.
Stepped field plates with proximity to conduction channel and related fabrication methods
A transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent the gate and a second portion adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion of the gate. Related devices and fabrication methods are also discussed.
A system configured to increase a reliability of electrical connections in a device. The system including a lead configured to electrically connect a pad of at least one support structure to a pad of at least one electrical component. The lead includes an upper portion that includes a lower surface arranged on a lower surface thereof. The lower surface of the upper portion is arranged vertically above a first upper surface of a first pad connection portion; and the lower surface of the upper portion is arranged vertically above a second upper surface of the second pad connection portion. A process configured to increase a reliability of electrical connections in a device is also disclosed.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/528 - Layout of the interconnection structure
A semiconductor device (10) includes a substrate (12), a drift layer (14), a well region (16), and a source region (18). The substrate (12) has a first conductivity type. The drift layer (14) has the first conductivity type and is on the substrate (12). The well region (16) has a second conductivity type opposite the first conductivity type and provides a channel region (28). The source region (18) is in the well region (16) and has the first conductivity type. A doping concentration of the well region (16) along a surface of the drift layer (14) opposite the substrate (12) is variable such that the well region (16) includes a region of increased doping concentration (30) at a distance from a junction between the source region (18) and the well region (16).
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
42.
RADIO FREQUENCY TRANSISTOR AMPLIFIERS HAVING ENGINEERED INTRINSIC CAPACITANCES FOR IMPROVED PERFORMANCE
Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
43.
LIGHT EMITTING DIODE PACKAGE WITH A PLURALITY OF LUMIPHORIC REGIONS
Solid-state lighting devices including light-emitting diodes (LEDs), and more particularly packaged LED devices are disclosed. LED packages (10) are disclosed herein with arrangements of LED chips (28-1, 28-2) and corresponding lumiphoric regions (42-1, 42-2) that are configured to provide overall light emissions having improved color mixing and emission uniformity. LED packages (10) are further disclosed herein that are configured to be tunable between different colors or correlated color temperatures (CCTs) while providing improved color mixing and emission uniformity. Arrangements may include differing lumiphoric regions that are arranged with various alternating patterns including one or more intersecting lines, rows of alternating lumiphoric regions, patterns that alternate in at least two directions, and checkerboard patterns.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.
Support circuitry for a power transistor includes a feedback switching element and switching control circuitry. The feedback switching element is coupled between a Kelvin connection node and a second power switching node. The switching control circuitry is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from a blocking mode of operation to a conduction mode of operation and cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation.
H03K 17/04 - Modifications for accelerating switching
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
A power module includes a plurality of power semiconductor devices. The plurality of power semiconductor devices includes an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in parallel between a first power switching terminal and a second power switching terminal. The IGBT and the MOSFET are silicon carbide devices. By providing the IGBT and the MOSFET together, a tradeoff between forward conduction current and reverse conduction current of the power module, the efficiency, and the specific current rating of the power module may be improved. Further, providing the IGBT and the MOSFET as silicon carbide devices may significantly improve the performance of the power module.
H03K 17/12 - Modifications for increasing the maximum permissible switched current
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. LED packages are disclosed that include an LED chip with multiple discrete active layer portions mounted on a submount. The LED packages may further include wavelength conversion elements and light-altering materials. The multiple discrete active layer portions may be electrically connected in series, parallel, or in individually addressable arrangements. The LED chip with the multiple discrete active layer portions may provide the LED package with improved brightness, improved alignment, simplified manufacturing, and reduced costs.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/54 - Encapsulations having a particular shape
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 33/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
48.
DEVICE DESIGN FOR SHORT-CIRCUIT PROTECTION OF TRANSISTORS
A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
49.
HIGH ELECTRON MOBILITY TRANSISTORS AND POWER AMPLIFIERS INCLUDING SAID TRANSISTORS HAVING IMPROVED PERFORMANCE AND RELIABILITY
A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
50.
METHODS FOR DICING SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES MADE BY THE METHODS
A method for forming semiconductor devices from a semiconductor wafer includes cutting a first surface of a semiconductor wafer to form a first region that extends partially through the semiconductor wafer and the first region has a bottom portion. The method further includes directing a beam of laser light to the semiconductor wafer such that the beam of laser light is focused within the semiconductor wafer between the first surface and the second surface thereof and the beam of laser light further cuts the semiconductor wafer by material ablation to form a second region aligned with the first region. A resulting semiconductor device is disclosed as well.
H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
51.
High electron mobility transistors having improved contact spacing and/or improved contact vias
A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.
In a Doherty amplifier (30), outputs of first or main (18a) and second or peak (18b) transistors are connected by a combined impedance inverter and harmonic termination circuit (36). The harmonic termination circuit (40) incorporates a predetermined part of the impedance inverter (38), and provides a harmonic load impedance at a targeted harmonic frequency (e.g., the second harmonic). Control of the amplitude and phase of the harmonic load impedance facilitates shaping of the drain current and voltage waveforms to maximize gain and efficiency, while maintaining a good load modulation at a fundamental frequency. Particularly for Group III nitride semiconductors, such as GaN, both harmonic control (26) and output impedance matching circuits (20) may be eliminated from the outputs of each transistor (18). The combined impedance inverter and harmonic termination circuit (36) reduces the amplifier circuit (30) footprint, for high integration and low power consumption.
Nondestructive characterization of crystalline wafers is provided, including defect detection, identification, and counting. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods based on deep neural networks. Certain aspects relate to nondestructive methods for defect characterization of silicon carbide (SiC) wafers. By subjecting SiC wafers to nondestructive defect characterization, SiC wafers in their final state may be characterized and subsequently used for device fabrication, vastly reducing the expense of the characterization process. Nondestructive defect characterization also allows for increased sampling and improved feedback loops between crystalline growth process development and subsequent device production.
Silicon carbide (SiC) wafers (8A) and related methods are disclosed that include intentional or imposed wafer (8A) shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers (8A) due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer (8A) shapes may comprise SiC wafers (8A) with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers (8A), and in particular for large area SiC wafers (8A), may be reduced. Related methods for providing SiC wafers (8A) with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material (70, 90, 92A, 92). Such methods may include laser-assisted separation of SiC (6H) wafers (8A) from bulk crystalline material (70, 90, 92A, 92).
B28D 5/00 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor
B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor by tools other than of rotary type, e.g. reciprocating tools
B23K 26/38 - Removing material by boring or cutting
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
55.
BIAS VOLTAGE CONNECTIONS IN RF POWER AMPLIFIER PACKAGING
In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/552 - Protection against radiation, e.g. light
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
60.
ACTIVE CONTROL OF LIGHT EMITTING DIODES AND LIGHT EMITTING DIODE DISPLAYS
Active control of LEDs, LED packages, and related LED displays by way of pulse wide modulation (PWM) is disclosed. Effective PWM frequencies for LEDs are increased by segmenting duty cycles in which LEDs are electrically activated within individual PWM periods. Segmented duty cycles may be provided by transforming or re-ordering a sequence in which control signals are provided to LEDs. As such, LEDs may be electrically activated and deactivated multiple times within each PWM period. Active electrical elements that are incorporated into one or more LED packages of an LED display may be capable of segmenting the duty cycle within each LED package. Active electrical elements may also be capable of receiving reset signals from a data stream to either initiate a reset action or pass the reset signals along to other active electrical elements of a display.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H05B 47/18 - Controlling the light source by remote control via data-bus transmission
A power amplifier includes a semiconductor die having a main amplifier and a peaking amplifier. The main amplifier includes at least one first transistor, and the peaking amplifier includes at least one second transistor that is different than the first transistor. The peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors. Related fabrication and methods of operation are also discussed.
DS1DS2SHSH1SHSHSH1SH2SH2) may be added to one or both amplifiers (14a, 14b), and sized to effectively control a characteristic impedance of the impedance inverter (38).
A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure arranged with at least one of the following: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.
Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
65.
Power semiconductor devices having top-side metallization structures that include buried grain stop layers
Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
66.
Methods and apparatuses related to shaping wafers fabricated by ion implantation
The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
67.
GROUP III-NITRIDE HIGH-ELECTRON MOBILITY TRANSISTORS WITH BURIED P-TYPE LAYERS AND PROCESS FOR MAKING THE SAME
An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A high electron mobility transistor includes a channel layer (230), a barrier layer (240) on the channel layer, source (250) and drain (252) contacts on the barrier layer, a gate contact (254) between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer (262) that comprises a charge dissipation material and directly contacts the upper surface of the barrier layer and a second passivation layer (264) comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. At least one recess (242) may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
69.
High electron mobility transistors having improved drain current drift and/or leakage current performance
A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A method for removing a portion of a crystalline material (e.g., SiC) substrate includes joining a surface of the substrate to a rigid carrier (e.g., >800 µm thick), with a subsurface laser damage region provided within the substrate at a depth relative to the surface. Adhesive material having a glass transition temperature above 25°C may bond the substrate to the carrier. The crystalline material is fractured along the subsurface laser damage region to produce a bonded assembly including the carrier and a portion of the crystalline material. Fracturing of the crystalline material may be promoted by (i) application of a mechanical force proximate to at least one carrier edge to impart a bending moment in the carrier; (ii) cooling the carrier when the carrier has a greater coefficient of thermal expansion than the crystalline material; and/or (iii) applying ultrasonic energy to the crystalline material.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure
A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another action includes forming additional subsurface laser damage at the first depth position. The substrate surface is illuminated with a diffuse light source arranged perpendicular to a primary substrate flat and positioned to a first side of the substrate, and imaged with an imaging device positioned to an opposing second side of the substrate.
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H03K 17/12 - Modifications for increasing the maximum permissible switched current
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include multiple subsurface laser damage patterns with groups of parallel lines that are non-parallel to one another, but each line is within ±5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate. Further methods involve formation of initial and subsequent subsurface laser damage patterns that are centered at different depths within of a substrate, with the laser damage patterns being registered and having vertical extents that are overlapping.
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
B23K 26/06 - Shaping the laser beam, e.g. by masks or multi-focusing
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
B23K 103/00 - Materials to be soldered, welded or cut
Pixelated-LED chips and related methods are disclosed. A pixelated- LED chip (130) includes an active layer with active layer portions (84-1, 84-2, 84-3) arranged on or over a light-transmissive substrate (15). The active layer portions, which may be independently electrically accessible, are configured to illuminate different light- transmissive substrate portions (86-1, 86-2, 86-3) to form pixels (104a, 104b, 104c). Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/ or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, an underfill material (108) with improved surface coverage is provided between adjacent pixels (104a, 104b, 104c) of a pixelated-LED chip (130). The underfill material (108) may be arranged to cover all lateral surfaces between the adjacent pixels. In some aspects, discontinuous substrate portions are formed before application of underfill materials. In some aspects, a wetting layer (128) is provided to improve wicking or flow of underfill materials (108) during various fabrication steps.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips (54) are provided that include first interconnects (44) electrically coupled to an n-type layer and second interconnects (30a, 30b, 30c) electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
The base (10) of an integrated circuit package (100) comprises a first side (11), and a second side (12) opposing the first side (11). The base (10) further comprises, a base mounting section (20), a die mounting section (30), and a recessed section (40). The recessed section (40) comprises a recess (41) between the die mounting section (30) and the base mounting section (20). The base (10) further comprises an opening (21) extending through the base (10) from the first side (11) to the second side (12). At least a portion of the recess (41) intersects with the opening (21).
H01L 23/043 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
77.
PACKAGED TRANSISTOR DEVICES WITH INPUT-OUTPUT ISOLATION AND METHODS OF FORMING PACKAGED TRANSISTOR DEVICES WITH INPUT-OUTPUT ISOLATION
Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 3/42 - Amplifiers with two or more amplifying elements having their DC paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED packages are disclosed. A light-altering material may be provided in particular configurations within an LED package to redirect light toward a primary emission direction. The light-altering material may be arranged on any of a first face, a second face, or a plurality of sidewalls of an LED chip in the LED package. A lumiphoric material may be arranged on one or more of the sidewalls. A superstrate may be arranged to mechanically support the LED chip from the first face. The light-altering material may be arranged on or dispersed within the superstrate. In certain embodiments, the primary emission direction of the LED package is substantially parallel to the second face of the LED chip in the LED package. An overall thickness or height of the LED package may be less than or equal to 0.25 mm.
BROADBAND IMPEDANCE MATCHING NETWORK USING LOW-PASS TYPE BROADBAND MATCHING, SECOND HARMONIC REFLECTION PHASE SHIFTING AND HIGH PASS COMPLEX CONJUGATE MATCHING IN COMBINATION
111) that transforms the complex conjugate device input impedance to a real impedance. The three-stage impedance matching network provides the fundamental and harmonic frequency impedances for broadband operations, as well as controllability of the second harmonic reflection coefficient phases where the device performances are consistent across the intended bandwidth..
A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.
A multi-cell transistor (100) includes a semiconductor structure (110), a plurality of unit cell transistors (170) that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
83.
MONOLITHIC MICROWAVE INTEGRATED CIRCUITS HAVING BOTH ENHANCEMENT-MODE AND DEPLETION MODE TRANSISTORS
A gallium nitride based monolithic microwave integrated circuit includes a substrate (110), a channel layer (130) on the substrate and a barrier layer (140) on the channel layer. A recess (412) is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode (210, 310) in direct contact with the barrier layer. Second gate (410), source (420) and drain (430) electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer (412) is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor (200, 300), and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor (400).
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.
Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Light emitting diode (LED) devices and systems include a superstrate (e.g., a light-transmissive layer), at least one region of wavelength- conversion material in the light-transmissive layer, and LEDs attached to the superstrate at the location of the wavelength-conversion material. An encapsulant layer is formed over and/or around the LEDs with an opaque or clear material. Additional color filter layers are optionally applied to the light- transmissive layer. A method for producing LED devices and systems includes providing a superstrate with a wavelength-conversion material region formed therein, attaching LEDs to the superstrate at the die-attach layer, forming conductive surfaces on a side of the LED opposite the die- attach layer, dispensing an encapsulant layer to at least partially encapsulate the LEDs, and forming one or more electrical traces to electrically interconnect the conductive surfaces of at least some of the LEDs with each other.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
87.
Power silicon carbide based MOSFET transistors with improved short circuit capabilities and methods of making such devices
A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
88.
STABILIZED FLUORIDE PHOSPHOR FOR LIGHT EMITTING DIODE (LED) APPLICATIONS
A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol.%. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed.
Light emitting diode (LED) devices and systems include a superstrate (e.g., a light-transmissive layer), LEDs attached to the superstrate at a die-attach layer formed thereon, and an encapsulant layer formed over and/or around the LEDs with a non-reflective or clear material. A method for producing LED devices and systems includes providing a superstrate with a die-attach layer formed thereon, attaching LEDs to the superstrate at the die-attach layer, forming conductive surfaces on a side of the LED opposite the die-attach layer, dispensing an encapsulant layer to at least partially encapsulate the LEDs, and forming one or more metal traces to electrically interconnect the conductive surfaces of at least some of the LEDs with each other.
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs that include individually controllable LED chips are disclosed. In some embodiments, an LED package includes electrical connections configured to reduce corrosion of metals within the package; or decrease the overall forward voltage of the LED package; or provide an electrical path for electrostatic discharge (ESD) chips. In some embodiments, an LED package includes an array of LED chips, each of which is individually controllable such that individual LED chips or subgroups of LED chips may be selectively activated or deactivated. A single wavelength conversion element may be provided over the array of LED chips, or separate wavelength conversion elements may be provided over one or more individual LED chips of the array. Representative LED packages may be beneficial for applications where a high luminous intensity with a controllable brightness or adaptable emission pattern is desired.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Solid state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. In some embodiments, an LED package includes electrical connections that are configured to reduce corrosion of metals within the LED package; or decrease the overall forward voltage of the LED package; or provide an electrical path for serially-connected electrostatic discharge (ESD) chips. In some embodiments, an LED package includes at least two LED chips and a material between the two LED chips that promotes homogeneity of composite emissions from the two LED chips. In this manner, LED packages according to the present disclosure may be beneficial for various applications, including those where a high luminous intensity is desired in a variety of environmental conditions. Such applications include automotive lighting, aerospace lighting, and general illumination.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
92.
APPARATUS AND METHODS FOR MASS TRANSFER OF ELECTRONIC DIES
An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
93.
PACKAGED ELECTRONIC CIRCUITS HAVING MOISTURE PROTECTION ENCAPSULATION AND METHODS OF FORMING SAME
An electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
94.
SEMICONDUCTOR LIGHT EMITTING DEVICES INCLUDING SUPERSTRATES WITH PATTERNED SURFACES
A semiconductor light emitting device includes a light emitting diode (LED) chip, a recipient luminophoric medium on the LED chip, a patterned superstrate on the recipient luminophoric medium opposite the LED chip, the patterned superstrate comprising a patterned superstrate on the recipient luminophoric medium opposite the LED chip, the patterned superstrate comprising a patterned surface that is configured to reduce a variation in a color point of a light emitted by the semiconductor light emitting device as a function of an angle off an optical axis of the LED chip
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
95.
LIGHT-EMITTING DIODE PACKAGE WITH LIGHT-ALTERING MATERIAL
Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly packaged LEDs with light-altering materials are disclosed. A light-altering material is provided in particular configurations within an LED package to redirect light from an LED chip within the LED package and contribute to a desired emission pattern of the LED package. The light-altering material may also block light from the LED chip from escaping in a non-desirable direction, such as large or wide angle emissions. The light-altering material may be arranged on a lumiphoric material adjacent to the LED chip in various configurations. The LED package may include an encapsulant on the light-altering material and the lumiphoric material.
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
96.
RF POWER AMPLIFIER WITH FREQUENCY SELECTIVE IMPEDANCE MATCHING NETWORK
An amplifier circuit (400) includes an input port (202), an output port (204), and a reference potential port (214), an RF amplifier device (206) having an input terminal (208) electrically coupled to the input port (202), an output terminal (210) electrically coupled to the output port (204), and a reference potential terminal (212) electrically coupled to the reference potential port (214). An impedance matching network (416) is electrically connected to the output terminal (210), the reference potential port (214), and the output port (204). The impedance matching network (416) includes a reactive efficiency optimization circuit (222) that forms a parallel resonant circuit at a center frequency of the fundamental frequency range. The impedance matching network (416) includes a reactive frequency selective circuit (240) that substantially negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.
A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.
A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
99.
POWER SILICON CARBIDE MOSFET DEVICES AND RELATED METHODS
A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A LED lighting device includes a temperature sensitive component having a temperature limit. A driver controls current delivered to the at least one LED and includes a temperature sensor for determining a temperature of the driver. A controller stores a correlated temperature limit of the driver, the controller controls the driver to reduce the current delivered to the LEDs when the correlated temperature limit is reached. The correlated temperature limit is the temperature of the driver when the temperature of the temperature sensitive component reaches its temperature limit.
patents
