Abstract

The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10K 30/35 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains comprising inorganic nanostructures, e.g. CdSe nanoparticles
• H10K 30/82 - Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
• H10K 30/87 - Light-trapping means
• H10K 39/32 - Organic image sensors

Abstract

The disclosure concerns a method including the steps of: a) providing a structure comprising a semiconductor substrate and, on the side of a first surface of the substrate, at least one first trench filled with an insulating material, vertically extending in the substrate; b) forming, by anisotropic etching from a second surface of the semiconductor substrate opposite to the first surface, at least one second trench vertically extending in the substrate and emerging onto the at least one first trench; and c) widening the at least one second trench by isotropic etching.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 27/146 - Imager structures

Abstract

The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a π/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by π/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.

IPC Classes  ?

• G02B 5/26 - Reflecting filters
• G01J 1/44 - Electric circuits
• G02B 5/20 - Filters
• G02B 13/14 - Optical objectives specially designed for the purposes specified below for use with infrared or ultraviolet radiation

Abstract

The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H04N 25/53 - Control of the integration time
• H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/763 - Polycrystalline semiconductor regions
• H10D 84/01 - Manufacture or treatment
• H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs

Abstract

The invention relates to a hybrid source for generating pairs of entangled photons (30), the hybrid source (100) comprising: - at least one AlGaAs waveguide (10) comprising AlGaAs, the at least one AlGaAs waveguide (10) having a second order nonlinearity, - at least one Silicon-on-Insulator (SOI) platform (20) comprising at least one layer (4, 6, 8) comprising silicon and at least one silicon waveguide (2) comprising silicon, the at least one AlGaAs waveguide (10) comprising AlGaAs being arranged on the at least one SOI platform (20) such that the at least one AlGaAs waveguide (10) is evanescently coupled to the at least one silicon waveguide (2) in a coupling region, wherein pairs of entangled photons (30) generated in the at least one AlGaAs waveguide (10) upon optical pumping are coupled into the at least one silicon waveguide (2).

IPC Classes  ?

• G02F 1/365 - Non-linear optics in an optical waveguide structure

Abstract

The invention relates to a method for manufacturing a microelectronic device (100) having a cavity (20) comprising at least one transistor (11a), the method comprising at least the following step:  Removing the materials from a stack of dielectric layers (1) of the microelectronic device (100), selectively with respect to the materials of a set of interconnection lines (2) and a cover (3) of an active area by vapor-phase HF etching, thus forming the cavity (20) extending laterally in a direction x at least until exposing the walls of the set of interconnection lines (2) opposite the first transistor (11a), and in a direction z perpendicular to the direction x until exposing an upper face of the cover (3) of the active area.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

IPC Classes  ?

• G02F 1/1333 - Constructional arrangements
• G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
• G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour

Abstract

A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

IPC Classes  ?

• H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
• H04N 25/53 - Control of the integration time
• H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.

IPC Classes  ?

• H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

Device (1), for continuous-time energy calculation of an analog signal, comprising: a continuous-time analog-to-digital converter which is configured to convert the analog signal into a request signal (REQ), and a direction signal (DIR); at least one filtering unit (11), configured to output a filtered output signal (Fout), and comprising a delaying module (12) and a calculating module (15), connected to the delaying module (12) and configured calculate the filtered output signal (Fout). Device (1), for continuous-time energy calculation of an analog signal, comprising: a continuous-time analog-to-digital converter which is configured to convert the analog signal into a request signal (REQ), and a direction signal (DIR); at least one filtering unit (11), configured to output a filtered output signal (Fout), and comprising a delaying module (12) and a calculating module (15), connected to the delaying module (12) and configured calculate the filtered output signal (Fout). According to the invention, the device (1) further comprises: at least one pulse combiner (16), connected to the delaying module (12) and configured to output a combined request signal (CREQ); and at least one energy estimator (17), connected to the filtering unit (11) and to the pulse combiner (16), configured to compute a stored energy value (Aout) associated with each pulse of the combined request signal (CREQ).

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03H 17/00 - Networks using digital techniques
• H03H 17/06 - Non-recursive filters
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

IPC Classes  ?

• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode

Abstract

An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.

IPC Classes  ?

• H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• G02B 5/18 - Diffracting gratings
• H10F 39/12 - Image sensors

Abstract

A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H04N 25/53 - Control of the integration time
• H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
• H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
• H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
• H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

The present disclosure relates to a DAC that includes: a first pixel including a first transfer gate coupling a memory node of the first pixel and a capacitive sensing node (SN); a second pixel comprising a first transfer gate coupling a memory node of the second pixel and the capacitive SN; a reset transistor coupling the sensing node to a first voltage supply rail; and a control circuit configured to store electrical charge by activating the reset transistor to apply a reference voltage to the memory node of each of the first and second pixels; and generate a voltage of the DAC at the sensing node by deactivating the reset transistor and controlling the first transfer gates of the first and second pixels to transfer the charge stored.

IPC Classes  ?

• H03M 1/66 - Digital/analogue converters
• H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An image sensor includes photodetection pixels formed inside and on top of a semiconductor substrate. An interconnection network coats a surface of the semiconductor substrate. The interconnection network includes a level of conductive vias in contact, by their lower surface, with the photodetection pixels. The conductive vias are made of doped polysilicon and have a heavier doping on their lower surface side than on their upper surface side.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

IPC Classes  ?

• H01L 27/146 - Imager structures
• G02B 1/10 - Optical coatings produced by application to, or surface treatment of, optical elements
• G02B 1/14 - Protective coatings, e.g. hard coatings
• G02B 3/00 - Simple or compound lenses

Abstract

A variable-capacitance diode is formed in a doped semiconductor substrate of a first conductivity type. The diode includes a first doped region of a second conductivity type in semiconductor substrate. A second doped region of the first conductivity type in a portion of the first doped region and a third doped region of second conductivity type in a further portion of the first doped region form a PN junction of the diode. First insulating trenches laterally delimit the each PN junction. Doped areas having a doping level heavier than the first doped region are provided within the first doped region under and in contact with a bottom of each first insulating trench. The diode is surrounded by a second insulating trench deeper than the first insulating trench.

IPC Classes  ?

• H01L 29/93 - Variable-capacitance diodes, e.g. varactors
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 29/66 - Types of semiconductor device
• H01L 29/861 - Diodes

Abstract

An embodiment light sensor includes an array of pixels arranged in rows and in columns. Each pixel comprises a photodiode, a sense node coupled to the photodiode, and an initialization transistor connected to the sense node. N successive pixels of a column or of a row are associated, where N is greater than or equal to 2. The initialization transistor of a first one of the pixels arranged at one end of the association of the N pixels is connected between the sense node of the first one of the pixels and a node of application of an initialization potential. For each two successive pixels among the N pixels, the initialization transistor of one of the pixels that is the most distant from the end is connected between the sense nodes of the two pixels.

IPC Classes  ?

• G01J 1/44 - Electric circuits

Abstract

A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

IPC Classes  ?

• H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• H10F 71/00 - Manufacture or treatment of devices covered by this subclass
• H10F 77/14 - Shape of semiconductor bodiesShapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies

Abstract

The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.

IPC Classes  ?

• H01H 37/34 - Means for transmitting heat thereto, e.g. capsule remote from contact member
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A device for testing an optical device, comprising a first structure comprising a substrate made of a first material and at least two first pillars of cylindrical shape made of a second material crossing the substrate, the second material having an optical index different from the optical index of the first material.

IPC Classes  ?

• G01M 11/02 - Testing optical properties

Abstract

The integrated circuit includes a semiconductor substrate having a front face including isolation structures that extend vertically into the substrate from the front face as far as a first depth, and an interconnection part comprising metal levels incorporating at least one passive component, above the front face of the substrate. The integrated circuit further includes a dielectric structure that is vertically aligned with the position of the at least one passive component, and that extends vertically into the substrate from the front face as far as a second depth that is greater than the first depth.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A reception element receives an analog signal. The received analog signal is converted by a reception chain into a digital signal. Based on the digital signal and a first filtering operation, a correction chain generates a correction digital signal reconstituting dynamic nonlinearities generated by the reception chain. A corrected signal from which the reconstituted dynamic nonlinearities have been removed is then generated by subtracting the correction digital signal from the digital signal.

IPC Classes  ?

• H04B 1/12 - Neutralising, balancing, or compensation arrangements

Abstract

The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.

IPC Classes  ?

• G02B 26/00 - Optical devices or arrangements for the control of light using movable or deformable optical elements
• G01J 3/26 - Generating the spectrumMonochromators using multiple reflection, e.g. Fabry-Perot interferometer, variable interference filter
• G02B 5/28 - Interference filters

Abstract

According to one aspect, there is proposed a method for assembling two integrated circuit wafers. The method includes removing by abrasion of a portion of an assembly face of a first wafer on a perimeter of the first wafer, and bonding the assembly face of the first wafer to an assembly face of a second integrated circuit wafer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

A first wafer includes a first semiconductor layer and first metal contacts on a side of a first surface of the first semiconductor layer. A second wafer includes a second semiconductor layer and second metal contacts on a side of a first surface of the second semiconductor layer. A handle is bonded onto a surface of the second wafer opposite to the second semiconductor layer. The second semiconductor layer is then removed to expose the second metal contacts. A bonding is then performed between the first and second wafers to electrically connect the first metal contacts to the second metal contacts.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic device includes an insulating first layer covering a second layer made of a doped semiconductor material. A cavity is formed to cross through the first layer and reach the second layer. Insulating spacers are forming against lateral walls of the cavity. A first doped semiconductor region fills the cavity. The first doped semiconductor region has a doping concentration decreasing from the second layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/737 - Hetero-junction transistors

Abstract

A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A transistor includes a source region, a drain region and a body region arranged in a semiconductor layer. A gate region tops the body region. The body region includes a first doped layer and a second layer between the first doped layer and the gate region. The second layer is an epitaxial layer that is less heavily doped than the first doped layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices

Abstract

A device includes a first pixel, based on quantum dots, configured to deliver event-based data for generating an event-based image, and second pixels, each second pixel based on quantum dots, configured to deliver light intensity data for generating a light intensity image.

IPC Classes  ?

• G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
• B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals

Abstract

The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.

IPC Classes  ?

• G02B 5/28 - Interference filters
• G01J 3/28 - Investigating the spectrum

Abstract

An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

An embodiment provides a method of forming a semiconductor device. A first silicon layer is deposited in a trench of a semiconductor substrate as an amorphous layer. A second silicon layer is deposited on top of and in contact with the first silicon layer as a polysilicon layer. After depositing the second silicon layer, the first silicon layer includes polysilicon having an average grain size different than an average grain size of the second silicon layer. A third semiconductor layer is deposited on top of and in contact with the second silicon layer to at least partially fill the trench.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

The present description concerns an image sensor formed inside and on top of a semiconductor substrate, the sensor comprising a plurality of pixels, each comprising a photodetector formed in the substrate, the sensor comprising at least first and second bidimensional metasurfaces stacked, in this order, in front of said plurality of pixels, each metasurface being formed of a bidimensional array of pads, the first metasurface having a first optical function and the second metasurface having a second optical function different from the first optical function.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/732 - Vertical transistors
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation

Abstract

A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/40 - Electrodes

Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

IPC Classes  ?

• G01J 1/44 - Electric circuits
• H04N 25/70 - SSIS architecturesCircuits associated therewith
• H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

The present description concerns a polarimetric image sensor formed inside and on top of a semiconductor substrate, the second comprising a plurality of pixels, each comprising: —a photosensitive region formed in the semiconductor substrate; —a diffraction structure formed on the side of an illumination surface of the photosensitive region; and —a polarization structure formed on the side of the diffraction structure opposite to the photosensitive region.

IPC Classes  ?

• G01J 3/447 - Polarisation spectrometry
• G01J 3/18 - Generating the spectrumMonochromators using diffraction elements, e.g. grating

Abstract

The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

IPC Classes  ?

• H10B 20/00 - Read-only memory [ROM] devices
• H01L 23/00 - Details of semiconductor or other solid state devices
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

The present disclosure relates to an image sensor including a plurality of pixels formed in and on a semiconductor substrate and arranged in a matrix with N rows and M columns, with N being an integer greater than or equal to 1 and M an integer greater than or equal to 2. A plurality of microlenses face the substrate, and each of the microlenses is associated with a respective pixel. The microlenses are arranged in a matrix in N rows and M columns, and the pitch of the microlens matrix is greater than the pitch of the pixel matrix in a direction of the rows of the pixel matrix.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A device includes a single photon avalanche diode in a portion of a substrate, wherein the portion has an octagonal profile. The octagonal profile is delimited by a wall forming an octagonal contour around the portion. The device further includes an array of diodes, wherein each diode is located in a corner between four adjacent single photon avalanche diodes. Each single photon avalanche diode further includes a doped anode region. A shallow trench isolation is formed in each doped anode region. A polysilicon line forming a resistor is supported at the upper surface of the shallow trench isolation.

IPC Classes  ?

• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
• H01L 27/146 - Imager structures
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions

Abstract

A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

IPC Classes  ?

• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A device includes a single photon avalanche diode in a substrate and a resistor. The resistor is provided resting on an insulating trench located in a doped anode region of the single photon avalanche diode.

IPC Classes  ?

• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 21/762 - Dielectric regions
• H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions

Abstract

An image sensor is includes a plurality of pixels. Each of the pixels includes a silicon photoconversion region and a material that at least partially surrounds the photoconversion region. The material has a refraction index smaller than the refraction index of silicon, and the interface between the photoconversion region of the pixel and the material is configured so that at least one ray reaching the photoconversion region of the pixel undergoes a total reflection or a plurality of successive total reflections at the interface.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/762 - Dielectric regions
• H01L 21/321 - After-treatment

Abstract

Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

IPC Classes  ?

• G02B 5/02 - Diffusing elementsAfocal elements
• C23C 16/34 - Nitrides
• C23C 16/56 - After-treatment
• C23C 18/12 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material

Abstract

The semiconductor device of a silicon on insulator type includes a NMOS transistor in a P-type well of the carrier substrate, a PMOS transistor in an N-type well of the carrier substrate, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition is achieved when a first non-zero negative voltage is applied to the P-type well and a first non-zero positive voltage is applied to the N-type well. The NMOS and PMOS transistors are configured to have nominal threshold voltages in the neutral back bias condition.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/786 - Thin-film transistors
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS

Abstract

A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration ; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/732 - Vertical transistors
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A method of manufacturing a PN junction includes successive steps for: forming at least one trench in a semiconductor substrate of a first conductivity type; and filling the at least one trench with a semiconductor material of a second conductivity type, different from the first conductivity type.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/762 - Dielectric regions

Abstract

A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/8234 - MIS technology
• H01L 29/40 - Electrodes

Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

IPC Classes  ?

• H01L 27/146 - Imager structures
• G01J 1/44 - Electric circuits
• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
• H04N 25/70 - SSIS architecturesCircuits associated therewith

Abstract

The present description relates to a method of manufacturing an end of an interconnection structure of an integrated circuit, the method including: providing an integrated circuit including an interconnection structure including copper interconnection elements at least partly extending through an insulating layer and flush with a first surface of said interconnection structure; forming a protection layer on the first surface of the interconnection structure, said protection layer including a material adapted to protecting the copper of the interconnection elements; forming a passivation layer on the protection layer, the passivation layer having a first thickness; and forming a first opening in the passivation layer across a second thickness smaller than the first thickness, to keep a residual passivation layer at the bottom of the first opening.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

In accordance with an embodiment, a method for manufacturing an optical device on a support substrate includes: forming first microlens structures on the support substrate using a first photolithography process such that the first microlens structures are separated from one another; deforming the first microlens structures so as to give the first microlens structures a curved shape, wherein the first microlens structures are separated from one another by spacer regions after deformation; forming second microlens structures substrate using a second photolithography process such that the second microlens structures extend over the first microlens structures; and deforming the second microlens structures such that the second microlens structures have a curved form matching the curved shape of the first microlens structures and extend partly into the spacer regions between the first microlens structures.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

An optoelectronic device is manufactured by an epitaxial growth, on each first layer of many first layers spaced apart from each other on a first support, wherein the first is made of a first semiconductor material, of a second layer made of a second semiconductor material. A further epitaxial growth is made on each second layer of a stack of semiconductor layers. Each stack includes a third layer made of a third semiconductor material in physical contact with the second layer. Each stack is then separated from the first layer by removing the second layer using an etching that is selective simultaneously over both the first and third semiconductor materials. Each stack is then transferred onto a second support. Each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.

IPC Classes  ?

• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present description concerns a manufacturing method comprising the following steps: providing a silicon substrate having a via penetrating into the substrate from its front surface and comprising a silicon conductive core and a silicon oxide insulating sheath; etching the substrate from its rear surface, selectively over the sheath so that a portion of said at least one via protrudes from the rear surface; depositing a silicon oxide insulating layer on the rear surface; polishing the insulating layer to expose the core while leaving in place a portion of the thickness of the insulating layer; and forming a conductive electrode in contact with the core.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The present description concerns a manufacturing method comprising, for each photodetector of an array of photodetectors of a light sensor, a use of a mask obtained by directed self-assembly of a block copolymer to form, by a first etch step, at least one first structure on the side of a first surface of the photodetector intended to receive light.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The present disclosure is directed to conductive structures that may be utilized in a radio-frequency (RF) switch. The embodiments of the conductive structures of the present disclosure are formed to balance the “on” resistance (Ron) and the “off” capacitance (Coff) such that the Ron·Coff value is optimized such that the conductive structures are relatively efficient as compared to conventional conductive structures within conventional RF switches. For example, the conductive structures include various metallization layers that are stacked on each other and spaced apart in a selected manner to balance the Ron and the Coff as to optimize the Ron·Coff figure of merit as a lower Ron·Coff is preferred.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

An integrated circuit includes at least one silicon region and at least one metal pillar in contact with the at least one silicon region at an ohmic coupling region. The at least one metal pillar is formed by: depositing a layer of titanium on the at least one silicon region; depositing atomic layers of titanium nitride on the layer of titanium; and annealing at a temperature of between 715° C. and 815° C. for a period of between 5 seconds and 30 seconds. This forms a titanium silicide for the ohmic coupling region in a volume having the appearance of a spherical cap or segment.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A photodiode is formed in a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes a first N-type semiconductor region formed by epitaxial growth and a second N-type semiconductor region (that is more heavily doped than the first region) extending into the first N-type semiconductor region from the first surface. The dopant concentration of the first N-type semiconductor region gradually increases between the second surface and the first surface of the semiconductor substrate. An implanted heavily P-type doped region is formed in the second N-type semiconductor region at the first surface.

IPC Classes  ?

• H01L 27/146 - Imager structures
• G01S 7/481 - Constructional features, e.g. arrangements of optical elements
• G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging

Abstract

An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

An electronic device includes a first electronic chip, a second electronic chip, and an interconnection circuit. A first region of a first surface of the first electronic chip is assembled by hybrid bonding to a third region of a third surface of the interconnection circuit. A second region of a second surface of the second electronic chip is assembled by hybrid to a fourth region of the third surface of the interconnection circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnection circuit. The first surface of the first electronic chip further includes a fifth region which is not in contact with the interconnection circuit. This fifth region includes a connection pad electrically connected by a connection element to a connection substrate to which the interconnection circuit is mounted.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A device includes at least one capacitor. The capacitor includes an assembly of two metal pads and at least two metal plates, each plate extending at least from one pad to the other, a first insulating layer conformally covering said assembly, a second conductive layer conformally covering the first layer.

IPC Classes  ?

• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind

Abstract

A device includes a first layer, having a copper track located therein. The first layer is covered with a second layer including a cavity. The cavity exposes at least a portion of the track. The portion is covered with a third layer of titanium nitride doped with silicon.

IPC Classes  ?

• H01G 4/008 - Selection of materials
• H01G 4/33 - Thin- or thick-film capacitors
• H01G 4/30 - Stacked capacitors
• H01G 4/012 - Form of non-self-supporting electrodes
• H01G 4/228 - Terminals

Abstract

A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.

IPC Classes  ?

• G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
• G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
• G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure

Abstract

An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

In accordance with an embodiment, a method for manufacturing a semiconductor device includes forming a first front layer and a first rear layer of a first material respectively on a front main face and a rear main face of a semiconductor substrate wafer; forming a first plurality of trenches and a second plurality of trenches respectively in a surface of the first front layer and in a surface of the first rear layer; forming a second front layer of a second material on the first front layer, where the second front layer extends over the first front layer, in the first plurality of trenches, and between the first plurality of trenches on the surface of the first front layer; and forming a second rear layer of the second material on the surface of the first rear layer, wherein the second rear layer extends over the first rear layer, in the second plurality of trenches, and between the second plurality of trenches on the surface of the first rear layer.

IPC Classes  ?

• G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films

Abstract

A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

IPC Classes  ?

• G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure

Abstract

First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

Integrated circuits are supported by a semiconductor substrate wafer. Each integrated circuit includes an electrically active area. A thermally conductive protective structure is formed around the active areas of the various integrated circuits along scribe paths. The protective structure is located between the electrically active areas of the integrated circuits and a laser ablation area of the scribe paths. Separation of the integrated circuits is performed by scribing the semiconductor substrate wafer along the scribe paths. The process for scribing includes performing a laser ablation in the laser ablation area and then performing one of an etching or a physical scribing.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

An integrated optical sensor includes a photon-detection module of a single-photon avalanche photodiode type. The detection module includes a semiconductive active zone in a substrate. The semiconductive active zone includes a region that contains germanium with a percentage between 3% and 10%. This percentage range is advantageous because it makes it possible to obtain a material firstly containing germanium (which in particular increases the efficiency of the sensor in the infrared or near infrared domain) and secondly having no or very few dislocations (which facilitates the implementation of a functional sensor in integrated form).

IPC Classes  ?

• H01L 31/0312 - Inorganic materials including, apart from doping materials or other impurities, only AIVBIV compounds, e.g. SiC
• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode

Abstract

A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

IPC Classes  ?

• G02B 6/124 - Geodesic lenses or integrated gratings
• G02B 6/34 - Optical coupling means utilising prism or grating
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• G02B 6/30 - Optical coupling means for use between fibre and thin-film device
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching

Abstract

The present disclosure relates to a memory cell (1) and to a method of erasing the memory cell (1). The memory cell comprises a doped well (100) of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region (106) of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (100); a buried doped channel (118) of the second conductivity type extending in the doped well (100); and a gate stack (108) resting on the doped well (100), above the buried doped channel (118). The gate stack (108) comprises a first layer (110) adapted to trap charges, a second insulating layer (112) resting on the first layer and a third conductive layer (114) resting on the second layer.

IPC Classes  ?

• H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

IPC Classes  ?

• H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• H10F 10/165 - Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
• H10F 71/00 - Manufacture or treatment of devices covered by this subclass
• H10F 77/122 - Active materials comprising only Group IV materials

Abstract

An avalanche photodiode includes a stack of layers. The stack of layers includes an avalanche diode (of PN or PIN type) and a layer having quantum dots located therein. The stack of layers further includes: a charge extraction layer over the layer which includes quantum dots; a transparent conducting layer over the charge extraction layer; and an insulating layer over the transparent conducting layer. The quantum dots includes ligands formed by molecules of dopants.

IPC Classes  ?

• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
• H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
• H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
• H01L 27/144 - Devices controlled by radiation

Abstract

A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

IPC Classes  ?

• H01L 21/8234 - MIS technology
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details

Abstract

An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.

IPC Classes  ?

• H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

The present description concerns a method that includes the compression, by a processor, of an image comprising first patterns by transforming the image into a first representation formed of two-point elements. The method also includes the execution, by a neural network, of an inference operation on the first representation to generate a second representation formed of two-point elements. The method further includes the generation of a lithographic mask based on the decompression of the second representation.

IPC Classes  ?

• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G03F 7/20 - ExposureApparatus therefor

Abstract

An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01M 11/00 - Testing of optical apparatusTesting structures by optical methods not otherwise provided for
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/27 - Optical coupling means with polarisation selective and adjusting means
• G02B 6/28 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals
• G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
• G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits