A voltage regulator includes a pre-regulation circuit and a low drop-out voltage regulator. The pre-regulation circuit is configured to generate a first power supply voltage based on an input voltage. The low drop-out voltage regulator is configured to generate a second power supply voltage based on the first power supply voltage. Additionally, the low drop-out voltage regulator is configured to filter a low-frequency component of the first power supply voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
2.
METHOD, SYSTEM, AND DEVICE FOR SOFTWARE AND HARDWARE COMPONENT CONFIGURATION AND CONTENT GENERATION
System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
An electronic device is configured to support at least two configurations, one of the configurations being installed. The device includes a memory. In a limited-access region of the memory, a binary word is stored. That binary word has: a first value representative of the version of the installed configuration; and at least one second value indicating which configurations can be installed. A method of configuration of the electronic device includes determining, according to the second value, whether the configuration which attempts to be installed is permitted.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
6.
METHOD FOR DEMODULATING A RF SIGNAL IN THE PRESENCE OF INBAND HARMONIC SPURS
The present disclosure relates to a method for demodulating a radio frequency (RF) signal comprising the steps of determining the nearest harmonic of a clock signal from a central frequency (Frx) of a received frequency band; and, if said nearest harmonic is in said frequency band, setting an intermediate frequency (IF) of a Near Zero Intermediate Frequency (NZIF) receiver to the difference (SpurOffset) between said central frequency (Frx) and said nearest harmonic.
The present disclosure relates to a method for demodulating a RF signal comprising the steps of: detecting if an analog to digital converter (ADC) of a Near Zero Intermediate Frequency (NZIF) receiver is in a clipping state; and if yes: determining and storing a first value (RSSI1) representative of the energy of a received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a first intermediate frequency (IF1); determining and storing a second value (RSSI2) representative of the energy of the received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a second intermediate frequency (IF2) corresponding to the opposite value of the first intermediate frequency (IF1), selecting the intermediate frequency corresponding to the lowest value of said first and second values.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
A device executes an authentication process protected by an authentication counter that is incremented in case of an authentication failure. The incrementation of the counter is protected against unexpected device power-off or power-off attacks. A non-volatile memory is divided into pairs of cells. The protecting includes writing a fixed value D into an active pair of two consecutive cells. As long as successful authentications occur, the content of the first cell is overwritten by a random value. When a failed authentication occurs, the content of the second cell is overwritten by a random value and the next two consecutive cells are written with the fixed value D. Those cells form the active pair and the protection process is repeated. This mechanism facilitates preventing the lack of incrementation of the authentication counter in case of unexpected device power-off during the processing of a failed authentication.
System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
The system-on-chip includes at least one master device, at least one slave resource, an interconnection bus including an error notification channel, and a resource isolation system including, for each resource, a protection circuit configured to block or transmit transactions addressed to the resource via the interconnection bus, according to access rights of the resource and the transaction. The protection circuit is capable of generating a notification signal on the error notification channel of the interconnection bus in case of blockage of a transaction.
The system-on-chip includes at least one microprocessor domain including a microprocessor and at least one resource; and a resource isolation system including a filtering circuit for each resource and configured to detect a security, privilege and compartmentalization access rights violation for the resource, by transactions arriving at the resource. The filtering circuit is configured, in the event of a violation of at least one access right to the resource by a transaction, to generate a first error signal representative of the violated access right to the resource, and a second error signal representative of at least one access right of this transaction.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
12.
METHOD FOR MOTION ESTIMATION IN A VEHICLE, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT
A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
G01S 19/47 - Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial
13.
DC-DC converter with steady state current limitation
In an embodiment a DC to DC conversion circuit includes a DC to DC converter connected to an input path and an output path and a current limiting circuit including a circuit configured to detect when an input or output current of the DC to DC converter exceeds or falls below a current threshold and a controller configured to store a first voltage level of an output voltage of the DC to DC converter in response to the input or output current exceeding the current threshold, to store a second voltage level of the output voltage in response to the input or output current falling below the current threshold and to set a control signal based on the first and second voltage levels.
A method of detecting network anomalies includes the reception, via an interface of an electronic device, of a first stream of packets sent by a source that is external and/or the transmission of a first stream of packets to a destination external; the computation, by a processing circuit, of a first packet stream identifier based on at least one of: a packet source address of the packets of the first stream; and a packet destination address of the first stream; searching, in an ordered dynamic data structure stored in a memory and including a plurality of entries. The searching is performed based on the value of the first packet stream identifier with respect to one or more search threshold values; and based on metadata associated with the first entry, blocking reception of the first stream of packets.
The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.
In an embodiment a method includes executing, during a first phase, one or more first codes stored in a first immutable zone of a non-volatile memory of an electronic device, forbidding, by an access control circuit of the non-volatile memory, execution of any codes stored in a second zone of the non-volatile memory during the first phase, executing, during a second phase, one or more second codes stored in the second zone and forbidding, by the access control circuit, any access to the first zone during the second phase.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.
In an embodiment a method includes detecting, by a monitoring circuit, on a bus of a device during execution by a processor of a code stored in a memory, an address for reading from the memory, wherein the device comprises the processor, the memory, the monitory circuit and the bus coupled to the memory, comparing, by the monitoring circuit, the address with one or more first addresses and controlling, by the monitoring circuit, a clock control circuit to prevent an activation of one or more peripheral circuits when the address is part of the one or more first addresses.
System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.
H04B 5/79 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for data transfer in combination with power transfer
The present description concerns a communication device including a first communication circuit coupled to a first antenna port of the communication device; a switch having first, second and third terminals, the first terminal being coupled to a second antenna port of the communication device, the switch being configured to switch between a first state in which the first terminal is coupled t the second terminal and a second state in which the first terminal is coupled to the third terminal; a third port coupled to the second terminal of the switch; and a second communication circuit coupled to the third terminal.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
24.
METHOD FOR MANAGING A MEMORY IN A SYSTEM-ON-A-CHIP
In accordance with an embodiment, a method for managing a memory within a system-on-a-chip including a processor, a memory and a firewall device, includes: generating, by the processor, a request to access the memory, where the request has a access permission level; controlling, by the firewall device, access to the at least one memory region of the memory as a function of the access permission level of the request and a respective access permission level associated with at least one memory region; and erasing, by the firewall device, the at least one memory regions when its respective access permission level is modified, where erasing comprises performing a hardware-implemented erasure.
In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.
In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.
A device includes a memory, a first firmware copy of the device stored in a first position of the memory and a second firmware copy of the device stored in a second position of the memory, where each of the first firmware copy and the second firmware copy includes instructions, when executed by the device, perform an operation of the device; and a first delta copy associated with the first firmware copy. The first delta copy includes instructions that differ from the first firmware copy when executed at the first position and are the same when executed at the second position. The device is configured to receive the first delta copy from an external system and store the first delta copy in the memory.
In accordance with an embodiment, a method for transaction between an application executed by a processor and a peripheral via a hardware abstraction layer includes: configuring the peripheral comprising writing a transaction configuration emitted by the application into configuration registers of the peripheral via the hardware abstraction layer; verifying compliance of the transaction configuration written in the configuration registers; and executing the transaction only when the transaction configuration written in the configuration registers is compliant based on the verifying.
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
30.
Integrated circuit comprising a non-volatile memory
In an embodiment an integrated circuit includes a non-volatile memory having a plurality of memory cells, wherein each memory cell is configured to store information, and wherein each memory cell is configured to provide a reading current having an intensity dependent on a value stored in the memory cell when the memory cell is selected for reading; and a sense amplifier including a first amplifier configured to amplify the reading current of each memory cell selected for reading, an oscillation generator configured to generate on basis of the amplified signal a signal having oscillations according to a frequency dependent on the intensity of the current of the amplified signal, a counter configured to count the oscillations of the signal generated by the oscillation generator over at least one given period of time and a digital processing circuit configured to determine a value represented by the amplified signal on basis of the value counted during the at least one given period of time using a lookup table between values countable by the counter and values representable by the amplified signal.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
31.
Method, system, and device for software and hardware component configuration and content generation
System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
A method includes protecting a boot sequence of a processing device by incrementing a counting value generated by a monotonic counter, then a first time period after the beginning of the boot sequence, comparing, by the protection circuit, the counting value with a first reference value, and, if the counting value is smaller than the first reference value, changing, by the protection circuit, the counting value to the first reference value.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
H03K 21/38 - Starting, stopping, or resetting the counter
35.
Method for verifying an execution of a software program
A method can be used for verifying an execution of a compiled software program stored in a program memory of a processor and executed by the processor. A write operation includes assigning a destination address in a register of the processor and writing a datum at a location pointed to by the destination address contained in the register. A verification operation includes reassigning the same destination address in the same register, reading the datum contained at the location pointed to by the destination address contained in the register after the reassignment, and comparing the read datum and the written datum.
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
36.
System on chip (SOC) comprising a program installation software for updating a program
A system on chip includes a non-volatile memory and a processor configured to execute an operating system which receives data according to a first communication protocol and program installation software that communicates with the non-volatile memory according to a second communication protocol. The operating system functions to: determine whether data received according to the first communication protocol is program data, make the program data available to the installation software, and inform the installation software that program data has been received. The installation software then stores the program data in the non-volatile memory.
In an embodiment a method for managing access rights of software tasks executed by a processing unit (CPU) using a cache memory containing execution data of the tasks in memory locations, each execution data having an attribute representative of a level of access right of the respective task, includes changing the attributes of the locations of the cache memory when the access rights of at least one task changes and retaining the execution data contained in the locations of the cache memory.
In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/24 - Automatic control of frequency or phaseSynchronisation using a reference signal directly applied to the generator
39.
DC-dC converter with steady state current limitation
In an embodiment a current limiting circuit includes a circuit configured to detect when an input or output current of a DC to DC converter exceeds or falls below a threshold and a controller configured to store a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold, store a second value representative of the level of the output voltage in response to the input or output current falling below a further threshold and modify a control signal based on the first and second values, wherein the control signal is modified based on the first and second values so that the control signal brings the output voltage to an intermediate voltage level between the level of the output voltage represented by the first value and the level of the output voltage represented by the second value.
According to one aspect, a method adds an additional function to a computer program installed on a microcontroller, the computer program using a table configured to associate an identifier of the additional function with a pointer to a memory address. The method includes the microcontroller obtaining a compiled code of the additional function and an identifier of this additional function, the microcontroller recording the compiled code of the additional function in a section of a memory, and recording in memory a pointer in the table, the pointer being aimed at the address of the memory section in which the compiled code of the additional function is recorded, the pointer being associated in the table with the identifier of the additional function.
The present disclosure relates to a method for authenticating instructions and operands in an electronic system comprising a controller. The method includes extracting instructions and operands via a first circuit of the controller from at least a first memory internal to the controller using a matrix bus of the controller, collecting, on the matrix bus, via a second circuit internal to the controller, instructions and operands during their transmission to the first circuit, and generating a word representative of the instructions and operands.
The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
In an embodiment a method for debugging a processing device includes generating, by a monotonic counter of the processing device, a first count value, transmitting, by the monotonic counter, the first count value to a debug access control circuit, comparing, by the debug access control circuit of the processing device, the first count value with one or more reference values and authorizing or preventing debug access, by the debug access control circuit, based on the comparison.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
46.
Electronic system comprising a plurality of microprocessors
The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.
A method includes receiving, by a device, of a control signal identifying a first application from among a plurality of compressed applications stored in a non-volatile memory of the device. The first application is stored in a first location of the non-volatile memory. The device decompresses the first application. The decompressing includes storing the decompressed first application into the non-volatile memory at least partially into the first location, and into a second location storing a second compressed application among the plurality of applications. The decompressed first application overwriting at least a portion of the second compressed application. The method may be performed as part of a customization process of an integrated circuit including the non-volatile memory.
A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
49.
Method of resetting a master device of a system on chip and corresponding system on chip
The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
According to one aspect, a method for compiling by a compilation tool a source code into a computer-executable code comprises receiving the source code as input of the compilation tool, translating the source code into an object code comprising machine instructions executable by a processor, then introducing, between machine instructions of the object code, additional instructions selected from illegal instructions and no-operation instructions so as to obtain the executable code, then delivering the executable code as output of the compilation tool.
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/55 - Detecting local intrusion or implementing counter-measures
In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.
A system including a first port configured to simultaneously couple with a first device and a second device; and a management circuit configured to route a data signal received from a first controller to the first device in response to receiving a first-device direction from the first controller and route the data signal received from the first controller to the second device in response to receiving a second-device direction from the first controller unless an override condition for the management circuit is satisfied.
In an embodiment a method for generating a random number includes selecting, by a first object, first symbols from an entropy pool of the first object, wherein the first object is an object of a group of mutually connected objects which are substantially identical, and wherein the entropy pool is fed with second symbols by objects of the group of mutually connected objects, applying, by the first object, a hash function to the first symbols to generate a random seed and generating, by the first object, the random number from the random seed.
A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 19/073 - Special arrangements for circuits, e.g. for protecting identification code in memory
H05B 45/10 - Controlling the intensity of the light
55.
DC-DC converter regulation circuit and method for determining overshoot duration
An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
G01S 19/47 - Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial
57.
Device and method for a frequency modulated signal
A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.
G06F 9/22 - Microcontrol or microprogram arrangements
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.
A method for monitoring an activity of a connected object including a monitoring device, includes: performing, by a measurement stage of the monitoring device, a first periodic measurement of an internal signal representative of an activity of the connected object; performing, by a computation stage of the monitoring device, a first non-cryptographic computation of an activity parameter representative of the activity from the internal signal measured during the first periodic measurement; comparing, by a comparison stage of the monitoring device, between the activity parameter on completion of the first non-cryptographic computation and a range of settings of corresponding to the activity parameter; and triggering, by a control stage of the monitoring device, a safety action in response to a determination that the activity parameter is outside of the range of settings.
G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
H04L 43/0817 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
G06F 1/3209 - Monitoring remote activity, e.g. over telephone lines or network connections
G08B 21/02 - Alarms for ensuring the safety of persons
System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
An electronic device includes a connector (e.g., a USB connector), a first element configured to operate the connector as a host device connector, a second element configured to operate the connector as a peripheral device connector, and a third element configured to generate a first signal upon connection of the connector. The first signal is indicative of whether the device is to operate as a host device or a peripheral device.
An embodiment system for protecting a memory comprises security software configured to determine, from an exception generated during an unauthorized action attempt in the memory, whether the security software can perform the action.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
A key generation method, device and system are disclosed. In an embodiment a method for generating a symmetrical key includes generating, by an electronic device, the symmetrical key as a function of an update program for updating software and a secret value held by the electronic device.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
The present description concerns a method for authenticating instructions and operands in an electronic system comprising a controller, the method comprising: extraction of the instructions and operands, by a first circuit (102) of the controller, from at least one first memory (104) internal to the controller, via a matrix bus (106) of the controller; fetching, on the matrix bus (106), by a second circuit (110) internal to the controller, of the instructions and operands during the transmission of same to the first circuit (102); and generation of a word representative of the instructions and operands (DIGEST).
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.
An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
70.
Device and method for managing an encrypted software application
An embodiment integrated circuit comprises a first memory zone having a first level of access rights that is configured to store at least one first software application containing encrypted instructions, means for verifying the integrity of the first software application, an encryption/decryption means, for example a first logic circuit, that is configured to decrypt the encrypted instructions which are considered to exhibit integrity, a processing unit that is configured to execute the decrypted instructions, the first logic circuit being further configured to encrypt the data generated by the execution operation and a second means, for example a second logic circuit, that is configured to store the encrypted data in a second memory zone having a second level of access rights that is identical to the first level of access rights.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
71.
Modification of a memory of a secure microprocessor
A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.
G06F 3/06 - Digital input from, or digital output to, record carriers
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
72.
Method and device for managing operation of a computing unit capable of operating with instructions of different sizes
An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.
A method for limiting an input or output current of a DC-DC converter and a current limiting circuit are disclosed. In an embodiment a method for limiting an input or output current of a DC to DC converter includes storing a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold and modifying a control signal based on the first value.
A display system comprises a processing circuit configured to receive image data from a video source, and generate a current image frame by generating pixel data as a function of the image data and storing the pixel data to a frame buffer. A graphic video driver is configured to display the image frame by reading the pixel data from the frame buffer and generating drive signals for the graphic display as a function of the pixel data read. The processing circuit also is configured to insert integrity data into the pixel data of the current image frame, wherein the position of the integrity data within the pixel data changes. The display system comprises a further processing circuit configured to read the pixel data from the frame buffer and verify whether the position of the integrity data within the pixel data changes.
Some embodiments include a method of communication between a master device and N slave devices on a synchronous data bus. The method includes selecting a slave device from among the N slave devices using a selection channel, where the master device and the N slave devices are coupled in series through the selection channel. The method also includes transmitting data between the master device and the selected slave device using a transmission channel, where the master device and the N slave devices are coupled in parallel through the transmission channel.
A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.
In one embodiment, a system on chip includes a dynamic voltage and frequency scaling (DVFS) power supply, a secure environment, a non-secure environment, and a power supply management control module. The secure environment is configured to generate a secure instruction defining a permitted operating point of voltage and frequency for the DVFS power supply. The non-secure environment is configured to generate a request to modify the DVFS power supply, where the request to modify includes a voltage-frequency operating point. The power supply management control module is configured to scale the DVFS power supply to the permitted operating point, in response to the request to modify the DVFS power supply.
G06F 21/81 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
A method for managing the operation of a group of a plurality of connected objects includes exchanging information between two of the connected objects of the group. The information relates to a state of each connected object participating in the exchanging of information. The method also includes triggering an action on a connected object participating in the exchanging of information. The triggering is based on the information received by this object.
A method for transmitting power includes providing power using a contactless power transfer from a transmitter to a receiver that is mutually coupled with the transmitter. The method also includes managing and regulating the contactless power transfer being provided, where the managing and regulating are integrally and autonomously performed by the transmitter.
H01F 27/42 - Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors or choke coils
H01F 37/00 - Fixed inductances not covered by group
H01F 38/00 - Adaptations of transformers or inductances for specific applications or functions
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
A method for monitoring an activity of a connected object including a monitoring device, includes: performing, by a measurement stage of the monitoring device, a first periodic measurement of an internal signal representative of an activity of the connected object; performing, by a computation stage of the monitoring device, a first non-cryptographic computation of an activity parameter representative of the activity from the internal signal measured during the first periodic measurement; comparing, by a comparison stage of the monitoring device, between the activity parameter on completion of the first non-cryptographic computation and a range of settings of corresponding to the activity parameter; and triggering, by a control stage of the monitoring device, a safety action in response to a determination that the activity parameter is outside of the range of settings.
A USB Type-C device supporting a bidirectional power supply, includes: a first device terminal configured to be coupled to a second USB Type-C device; a second device terminal configured to be coupled to a rechargeable DC voltage power source; and a reversible switched-mode power supply coupled to the first device terminal and the second device terminal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The electrical relay device comprising a component of electrical relay type including a controllable motor, and a switching module including at least one fixed electrical contact, and at least one movable electrical contact that is mechanically coupled to the motor and configured to be placed, using the motor, in at least one position, referred to as the disconnected position, in which it does not make contact with a fixed electrical contact, or in at least one position, referred to as the connected position, in which it does make contact with the at least one fixed electrical contact.
H01H 47/00 - Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
H01H 3/42 - Driving mechanisms, i.e. for transmitting driving force to the contacts using cam or eccentric
H01H 53/00 - Relays using the dynamo-electric effect, i.e. relays in which contacts are opened or closed due to relative movement of current-carrying conductor and magnetic field caused by force of interaction between them
H02N 2/00 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
H02P 7/06 - Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current
Some embodiments include a method of communication between a master device and N slave devices on a synchronous data bus. The method includes selecting a slave device from among the N slave devices using a selection channel, where the master device and the N slave devices are coupled in series through the selection channel. The method also includes transmitting data between the master device and the selected slave device using a transmission channel, where the master device and the N slave devices are coupled in parallel through the transmission channel.
A method for vehicle parking assistance during a parking maneuver of the vehicle includes detecting an obstacle in a detection space outside the vehicle. Successive measurements are taken of the distance or distances separating the vehicle and the obstacle and the position or positions of the obstacle relative to the vehicle. Depending on the results of the measurements, human speech voice messages are generated that provide parking assistance. The voice messages are broadcasted in the passenger compartment of the vehicle.
An embodiment method for controlling a physical object to be shared by several potential users and in an enclosure in an open state or in a closed state includes detecting a presence or an absence of the object in the enclosure in the closed state via a first wireless link between the object and a reader situated in the enclosure, the first wireless link being contained in the enclosure in the closed state. The method also includes transmitting a first information item representative of the presence or of the absence of the object in the enclosure to a computer server via a second link and an internet network, the computer server being accessible via a website configured to be managed by an administrator.
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G07C 9/00 - Individual registration on entry or exit
E05G 1/10 - Safes or strong-rooms for valuables with alarm, signal, or indicator
G06K 9/66 - Methods or arrangements for recognition using electronic means using simultaneous comparisons or correlations of the image signals with a plurality of references, e.g. resistor matrix references adjustable by an adaptive method, e.g. learning
G08B 25/00 - Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
86.
Method and device for the contactless energy transfer to an apparatus equipped with a loudspeaker
A device includes a first module having an electromagnetic loudspeaker having an inductive element configured to drive a membrane of the electromagnetic loudspeaker. A second module is coupled between the inductive element and a load. The second module is configured to carry out a contactless transfer of energy from an emitter to the load via the inductive element.
A stepper motor is driven according to step driving modes including a full-step driving mode, a half-step driving mode and micro-stepping modes. The stepper motor may also be driven in an acceleration phase. A method of controlling the stepper motor includes controlling the current step driving mode of the motor by a processing unit. During the acceleration phase of the stepper motor and the stepper motor being in driven in a current step driving mode other than the full-step driving mode, the processing unit tests, after each speed increase, if a remaining computing power of the processing unit is sufficient for control of the stepper motor to remain in the current step driving mode, and if not the processing unit, in presence of a first switching condition, switches control of the stepper motor to the driving mode having the closest coarser step.
G05D 3/18 - Control of position or direction using feedback using an analogue comparing device delivering a series of pulses
G04C 3/02 - Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means wherein movement is regulated by a pendulum
G05B 19/40 - Open loop systems, e.g. using stepping motor
G06K 13/20 - Conveying record carriers from one station to another, e.g. from stack to punching mechanism the record carrier being longitudinally extended, e.g. punched tape Details
A method for reading or writing data at an address of a memory is disclosed. The data includes a number of consecutive words that each has a plurality of bits. The words are transferred to or from the memory in synchronization with a clock signal so that each word is transferred in one cycle of the clock signal. The bits are scrambled or unscrambled by applying a logic function to the bits of each word. The logic function is identical for the scrambling and the unscrambling and makes use of a bit-key that is dedicated to the word and is identical for the scrambling and the unscrambling. Each bit-key comes from a pseudo-random series generated based on the address.
A module incorporated within a system-on-a-chip operating in a steady-state power supply phase is powered by supplying to the module a regulated power supply voltage obtained from a feedback control loop. The receives a main power supply voltage and a negative feedback voltage. The negative feedback voltage is generated inside the system-on-a-chip starting from an effective supply voltage of the module and from a setpoint signal corresponding to a desired regulated power supply voltage.
The receiver for a satellite positioning system includes at least one receive channel with an input stage configured to receive a satellite signals having different constellation frequencies belonging to one frequency band or to different frequency bands. The receive channel further includes a frequency transposition stage connected to the input stage (EE) and including a controllable local oscillator device configured to deliver different frequency transposition signals respectively adapted to the different constellation frequencies. A processing stage of the receive channel is connected to the frequency transposition stage and includes a control circuit configured to control the local oscillator device to sequentially and cyclically deliver the different frequency transposition signals.
G01S 19/24 - Acquisition or tracking of signals transmitted by the system
G01S 19/09 - Cooperating elementsInteraction or communication between different cooperating elements or between cooperating elements and receivers providing processing capability normally carried out by the receiver
G01S 19/35 - Constructional details or hardware or software details of the signal processing chain
91.
Method for managing contactless power transfer from a transmitter to a receiver, and corresponding transmitter
Contactless power transfer from a transmitter to a receiver is managed. A magnetic field is generated by the transmitter from a command at a control frequency for a switching resonant circuit. The receiver communicates information to the transmitter through modulation of the magnetic field. The modulation is detected by the transmitter so as to extract the information. An adjustment of the control frequency is then made according to the received information. The modulation detection involves detecting variations in the control frequency.
H01F 38/00 - Adaptations of transformers or inductances for specific applications or functions
H02J 5/00 - Circuit arrangements for transfer of electric power between ac networks and dc networks
H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves
B60L 11/18 - using power supplied from primary cells, secondary cells, or fuel cells
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
92.
Method for powering a module incorporated within a system-on-a-chip and corresponding electronic device
A module incorporated within a system-on-a-chip operating in a steady-state power supply phase is powered by supplying to the module a regulated power supply voltage obtained from a feedback control loop. The receives a main power supply voltage and a negative feedback voltage. The negative feedback voltage is generated inside the system-on-a-chip starting from an effective supply voltage of the module and from a setpoint signal corresponding to a desired regulated power supply voltage.
Method for managing, in a receiver, a radio service continuity based on synchronized broadcasts of identical audio contents on different frequencies, comprising, the receiver being tuned to a first frequency corresponding to a first broadcast of a first audio content, a detection in the receiver of a second audio content broadcast on a second frequency, having a level of quality above a threshold and paired with the first audio content.
patents
