Abstract

A memory device comprises a memory array having memory cells in a set of memory portions and addressable via a pair of row and column values, a set of sense amplifier circuits coupled to and interposed between adjacent memory portions, a control logic circuit configured to provide at least one address signal indicating a pair of row and column values to localize at least one addressed memory cell, and to issue read or write access requests towards the at least one addressed memory cell, a first set of access devices configured to couple an addressed memory cell in a respective memory portion to a respective sense amplifier circuit in response to a read access request, and a second set of access devices configured to couple an addressed memory cell in a respective memory portion to a main programming bitline in response to a write access request.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The present disclosure relates to a method of manufacturing a light sensor comprising a matrix of pixels each associated to a micro-lens having a shift with respect to the pixel. For each axis of a plurality of axes passing by the optical center of the matric, for each pixel on the axis, and for each of a plurality light incident angles, a response value of the pixel is obtained. Based on the response values, for each axis and each pixel on the axis, a first function providing the light incident angle for which the pixel has the best response value is determined. For each axis and each pixel on the axis, a second value of the shift for bringing closer the first function to a target function is determined. The sensor is manufactured using the second values of shift.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.

IPC Classes  ?

• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Abstract

A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.

IPC Classes  ?

• H03L 7/08 - Details of the phase-locked loop
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H03K 3/037 - Bistable circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

Various embodiments of the present disclosure disclose improved BIST systems and methods for testing digital devices. A method for testing a digital device includes receiving, based at least in part on an input signal, an output signal from a device under testing (DUT). The output signal is processed to generate a noise signal and a recovered signal for the DUT. The controller may generate a signal to noise power ratio based at least in part on the noise and recovered signals and compare the signal to noise power ratio to a predetermined power threshold to generate a performance metric.

IPC Classes  ?

• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G06F 11/30 - Monitoring

Abstract

The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

IPC Classes  ?

• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
• G11C 29/36 - Data generation devices, e.g. data inverters

Abstract

A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.

IPC Classes  ?

• G11B 5/60 - Fluid-dynamic spacing of heads from record carriers

Abstract

According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.

IPC Classes  ?

• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers

Abstract

The present disclosure is directed to kickback detection for devices, such as handheld drills. Kickback is detected using a gyroscope and an accelerometer, and is detected at the end of each of a plurality of time windows. At the end of each time window, kickback is detected based on, for example, a variance of a norm of gyroscope measurements. False kickback detections are then removed based on, for example, a minimum and a mean of accelerometer measurements. Kickback detection is completed before the next time window begins.

IPC Classes  ?

• B25F 5/00 - Details or components of portable power-driven tools not particularly related to the operations performed and not otherwise provided for

Abstract

Apparatuses, systems, and methods for radio frequency communication circuit are provided. For example, a radio frequency communication device includes a clock signal generator configured to deliver a clock signal, based on a time base common to a communication mode and to a standby mode, from a first reference signal and a second reference signal.

IPC Classes  ?

• H04B 1/40 - Circuits
• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
• H04L 7/00 - Arrangements for synchronising receiver with transmitter

Abstract

A debug method implemented by a first near field communication (NFC) device includes a step of storing, in a memory of the first NFC device, one or more parameters which are associated with the operation of the first NFC device during a communication with a second distant NFC device. The first NFC device then uses an answer to select (ATS) communication, sent in response to receipt of an answer to select (ATS) communication, to send the stored one or more parameters to the second distant NFC device.

IPC Classes  ?

• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips

Abstract

A transistor suited for use as an RF switch includes a semiconductor layer and a stack of a gate insulator layer and a conductive gate layer. A length of the conductive gate layer is smaller on the side of a lower surface, located in the vicinity of the gate insulator layer, and is greater on the side of an upper surface, opposite to the lower surface. Lateral sides of the conductive gate layer are covered, on a lower portion, with a first material and, on an upper portion, with a second material. The first material has a Young's modulus greater than a Young's modulus of the second material.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes

Abstract

An integrated circuit comprises processing circuitry and near-field communication (NFC) circuitry comprising read/write (RW) circuitry and card emulation (CE) circuitry. The processing circuitry selectively performs a direct loopback test by (i) causing the RW circuitry to transmit first test data, (ii) causing the CE circuitry to receive the transmitted first test data, and (iii) comparing the received first test data and the transmitted first test data. The processing circuitry selectively performs a reverse loopback test by (i) causing the RW circuitry to generate a continuous wave, (ii) causing the CE circuitry to modulate second test data onto the continuous wave and transmitting the modulated continuous wave, (iii) causing the RW circuitry to receive and demodulate the modulated continuous wave to extract the second test data, and (iv) comparing the extracted second test data and the second test data prior to being modulated by the CE circuitry.

IPC Classes  ?

• H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems

Abstract

Systems, apparatuses, and methods for an on chip dynamic IR oscilloscope are provided. An oscilloscope circuitry may comprise sensor circuitry, voltage generator circuitry, finite state machine, and latch circuitry. The sensor circuitry may include digital logic circuitry, sample and hold circuitry, and sense amplifier circuitry. The voltage generator circuitry may include a voltage generator, analog buffers, switches, and high speed buffer. The finite state machine may control the sensor circuitry to sample a voltage waveform and the voltage generator circuitry to generate a reference voltage that may change over time. The sensing amplifier circuitry may compare the samples to the reference voltage to generate flags when a sample exceeds a reference voltage. The flags may be used to stored the voltages associated with the flags, which may be used to redraw the waveform sampled.

IPC Classes  ?

• G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
• G11C 27/02 - Sample-and-hold arrangements

Abstract

A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

Abstract

The present disclosure relates to a method of training a neural network using a circuit comprising a memory and a processing device, an exemplary method comprising: performing a first forward inference pass through the neural network based on input features to generate first activations, and generating an error based on a target value, and storing the error to the memory; and performing, for each layer of the neural network: a modulated forward inference pass; before, during or after the modulated forward inference pass, a second forward inference pass based on the input features to regenerate one or more first activations; and updating one or more weights in the neural network based on the modulated activations and the one or more regenerated first activations.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06N 5/046 - Forward inferencingProduction systems

Abstract

A method for transmission of monochrome video data of a monochromatic image, wherein three different source monochromatic pixels are encoded by a transmitting device into one compressed three-color pixel; the compressed three-color pixel are transmitted by the transmitting device. The transmitted compressed three-color pixel are received at a receiving device; and the compressed three-color pixel decoding are decoded by the receiving device into three different sink monochromatic pixels. The transmitting device acquires the three different source monochromatic pixels, extracts a single-color value from each of the three different source monochromatic pixels, and generates the compressed three-color pixel using the single-color values extracted from the three different source monochromatic pixels. The receiving device extracts the single-color value from the compressed three-color pixel and associates each of the single-color values extracted from the compressed three-color pixels to a respective pixel of the three different sink monochromatic pixels.

IPC Classes  ?

• H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
• G06V 10/56 - Extraction of image or video features relating to colour

Abstract

A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

IPC Classes  ?

• H03K 4/06 - Generating pulses having essentially a finite slope or stepped portions having triangular shape
• H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/30 - Power supply circuits
• G11C 16/32 - Timing circuits

Abstract

A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

IPC Classes  ?

• G11C 8/20 - Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• G11C 11/418 - Address circuits

Abstract

A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

IPC Classes  ?

• G11C 8/20 - Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• G11C 11/418 - Address circuits

Abstract

According to an embodiment, an LLC resonant converter includes a switching bridge having a plurality of power switches. The switching bridge is configured to receive a DC voltage input and generate a square waveform based on a pulse-modulated frequency (PFM) signal at the switching bridge. The LLC resonant converter further includes a resonant tank circuit coupled to the switching bridge. The resonant tank circuit includes a resonant inductor. The resonant tank circuit is excited in response to receiving the square waveform. The PFM signal is adjusted such that an elapsed time between a rising edge of a Drain-Source Voltage of a power switch and a zero-crossing point of current flowing through the resonant inductor falls within a predetermined range corresponding to the resonant tank circuit operating at its resonant frequency.

IPC Classes  ?

• H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/00 - Conversion of DC power input into DC power output
• H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Abstract

Methods, systems, and devices for fault detection at pulse width modulation converters are described. An example of one such method includes receiving a first signal including a first pulse width modulation waveform. The first signal may be for controlling a switching component via a first node. A second signal may be received. The second signal may include a second pulse width modulation waveform. The second signal may be output by a second node of the switching component. One or more operations may be performed to compare the second signal with one or more other signals or one or more thresholds. A third signal may be transmitted based at least in part on the comparison of the second signal with the one or more other signals or thresholds. The third signal may indicate whether a fault has occurred at the switching component.

IPC Classes  ?

• H02H 7/122 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers for inverters, i.e. DC/AC converters
• H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation

Abstract

The present disclosure is directed to lift-up gesture detection for electronic devices. An initial lift-up gesture is detected in response to an orientation change and a lift-up motion of the device being detected. The initial lift-up gesture is validated as a true lift-up gesture in a case where a shaking motion of the device is not being detected when the initial lift-up gesture is detected. If a shaking motion of the device is detected when the initial lift-up gesture is detected, the initial lift-up gesture is rejected.

IPC Classes  ?

• G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

Abstract

An example gesture detection method includes detecting at a first time a first touch on a touch panel, where the first touch covers a first area of the touch panel, and then determining whether the first touch is within a track region that surrounds a fingerprint sensing region. The method includes determining whether the first touch is within the fingerprint sensing region, the fingerprint sensing region including a sensing surface of a fingerprint sensor. The method includes determining a first fraction of the fingerprint sensing region covered by the first touch and determining whether the first fraction exceeds a first threshold. The first threshold is a majority of the fingerprint sensing region. The method includes determining a second fraction of all of the first area that is within the fingerprint sensing region and determining whether the second fraction exceeds a second threshold, where the second threshold is a fraction indicative of a majority of an area associated with the corresponding touch. The method includes based on determining that the second fraction exceeds the second threshold, determining whether the first touch is valid.

IPC Classes  ?

• G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
• G06F 3/047 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
• G06V 40/12 - Fingerprints or palmprints
• G06V 40/13 - Sensors therefor

Abstract

Various examples in accordance with the present disclosure provide an operational amplifier with low noise and wide output swing.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

First signal processing is applied to a first input signal oscillating at an input frequency and a first set of control signals to generate a first output signal oscillating at a multiple of the input frequency with an amplitude controlled by a control signal in the first set of control signals. Second signal processing is applied to a second input signal oscillating in quadrature at the input frequency and a second set of control signals to generate a second output signal that oscillates at the multiple of the input frequency with an amplitude controlled by a control signal in the second set of control signals. A further output signal, generated in response to the first and second output signals, oscillates at the multiple of the input frequency with a phase shift controlled by a ratio of control signal amplitudes for the first and second sets of control signals.

IPC Classes  ?

• G01S 7/35 - Details of non-pulse systems
• G01S 7/03 - Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
• G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles

Abstract

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits

Abstract

An example apparatus, method, and computer program product for preserving privacy while capturing imagery data in a surveillance setting are provided. In some embodiments, the example apparatus includes an event-based capture mechanism and a standard illuminance capture mechanism, electrically connected to a controller. The event-based capture mechanism is configured to generate an event-based image, while the standard illuminance capture mechanism is configured to generate a standard illuminance image. The controller includes program code configured to cause the controller to receive, from the event-based capture mechanism, the event-based image, detect an object of interest in the event-based image, activate the standard illuminance capture mechanism based at least in part on a classification of the object of interest, and receive, from the standard illuminance capture mechanism, a standard illuminance image.

IPC Classes  ?

• H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
• G06F 21/84 - Protecting input, output or interconnection devices output devices, e.g. displays or monitors
• G06V 20/52 - Surveillance or monitoring of activities, e.g. for recognising suspicious objects
• G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestriansBody parts, e.g. hands
• H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
• H04N 23/611 - Control of cameras or camera modules based on recognised objects where the recognised objects include parts of the human body

Abstract

An integrated circuit package includes an integrated circuit die. The integrated circuit die includes core circuitry implemented in one or more layers of semiconductor material, a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry, a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry, a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster, and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry. The integrated circuit package includes a passivation layer on the integrated circuit die and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A manufacturing process vertical-conduction power device includes: from a layer containing semiconductor material with a lattice structure having spatial symmetry, growing an epitaxial layer, having the lattice structure with spatial symmetry and a first electrical conductivity; forming body having regions a second electrical conductivity, opposite to the first electrical conductivity, in the epitaxial layer; and forming a current-spreading layer in the epitaxial layer between the body regions. Forming the body regions includes carrying out a body channeling ion implantation, using a body mask. Forming the current-spreading layer includes: forming shallow damaged regions in the body regions through the body mask so that the lattice structure is altered in the shallow damaged regions; and carrying out a current-spreading channeling ion implantation, using the shallow damaged regions as implantation mask.

IPC Classes  ?

• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
• C30B 29/36 - Carbides
• C30B 33/08 - Etching
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A MEMS (MicroElectroMechanical System) device includes: a supporting body; a movable mass, constrained to the supporting body by flexures so as to be able to oscillate in a main direction; an actuator device, configured to apply to the movable mass an electrostatic actuation force, transverse to the main direction; and a control circuit configured to detect stiction conditions, in which the movable mass is stuck to the supporting body by a stiction force, and for driving the actuator device in response to recognition of the stiction conditions. The actuation force is a variable force with an actuation frequency band containing at least one resonance frequency in a direction transverse to the main direction of a mechanical system comprising the movable mass stuck to the supporting body.

IPC Classes  ?

• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
• G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up

Abstract

An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

An in-memory computation (IMC) system includes an in-memory computation circuit formed by a first phase change memory (PCM) array configured to store the computational weights for an in-memory computation operation. A data storage circuit is formed by a second PCM array configured to store backup data for the computational weights for the in-memory computation operation. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. A control circuit operates to read the backup data from the second PCM array and write to the first PCM array to refresh the computational weights for the in-memory computation operation from the backup data.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

Methods, systems, and devices for improving passivation layer durability are described. A device may include a semiconductor substrate elongated along a first direction and a second direction. The first direction may be parallel to a width of the semiconductor substrate and the second direction may be parallel to a depth of the semiconductor substrate. The device may include one or more layers formed above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate. At least a region of the one or more layers may include circuitry. The device may include a passivation layer formed above the one or more layers with respect to the third direction. The passivation layer may include a plurality of cavities that each extend through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping with respect to the first direction and the second direction.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

An example method, apparatus, and pulse oximeter device for determining a blood oxygen saturation value in a subject are provided. The example apparatus may include a light source configured to emit monochrome light of a single emitted wavelength. The light source may be positioned to direct the monochrome light at a portion of a subject. The example apparatus may further include a light sensing diode configured to receive an unabsorbed portion of the monochrome light. The apparatus may also include a controller configured to determine a blood oxygen saturation value based on one or more characteristics of the unabsorbed portion of the monochrome light comprising light of the single emitted wavelength.

IPC Classes  ?

• A61B 5/1455 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value using optical sensors, e.g. spectral photometrical oximeters
• A61B 5/00 - Measuring for diagnostic purposes Identification of persons

Abstract

A method of operating a touch screen panel includes initiating a communication between the panel and an active pen and determining a touch zone of the panel. The touch zone includes communication channels that are operating by touch while bi-directional communication is occurring between the panel and active pen. Communications channels within the touch zone are disabled and communication between the panel and the active pen can occur while the communications channels within the touch zone are disabled. When it is determined that the communication between the panel and the active pen has stopped, communications channels continue to be disabled within the touch zone for a set time delay while no communication occurs between the panel and the active pen. After the set delay time, the communication channels within the touch zone are enabled.

IPC Classes  ?

• G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Abstract

A method for determining whether an electronic device is located on a stationary surface includes generating, by a first motion sensor of an electronic device, first sensor data over an acquisition time window. The method includes determining, by a first feature detection circuit of the electronic device, at least one first orientation-independent feature for the acquisition time window based on the first sensor data. The method further includes executing, by a first classifying circuit of the electronic device, a first machine learning classification to determine whether the electronic device is steady or is in motion. And the method further includes, in response to determining the electronic device is steady, executing, by a second classifying circuit of the electronic device, a second machine learning classification to determine whether the electronic device is on a stationary surface or is on a semi-stationary surface based on the at least one first orientation-independent feature.

IPC Classes  ?

• G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
• G01C 19/00 - GyroscopesTurn-sensitive devices using vibrating massesTurn-sensitive devices without moving massesMeasuring angular rate using gyroscopic effects
• G01P 13/00 - Indicating or recording presence or absence of movementIndicating or recording of direction of movement

Abstract

A method comprising encrypting data values by a fully homomorphic encryption using a secret key to obtain encrypted data values, aggregating encrypted remote data in an encrypted aggregated value by performing a sum of the respective encrypted data values, performing one or more functions on the basis of the set of data values at the using entity, supplying the encrypted aggregated value to the using entity, which is configured to receive the secret key from a separated entity, decrypting the encrypted aggregated value using the secret key to obtain a decrypted sum of data values, performing data-related functions on the basis of the decrypted sum of the respective data values at the using entity.

IPC Classes  ?

• H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
• H04L 9/08 - Key distribution

Abstract

An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A semiconductor electronic device is formed in a die having a substrate of semiconductor material of a first conductivity type. The device has a first electronic component based on heterostructure, which has a body structure of semiconductor material that extending, in the die, on the substrate, and an epitaxial multilayer extending in contact with the body structure and having a heterostructure. The body structure of the first electronic component has a first doped region of semiconductor material that extends between the heterostructure and the substrate and has a second conductivity type different from the first conductivity type.

IPC Classes  ?

• H01L 27/095 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/66 - Types of semiconductor device
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

For manufacturing a semiconductor electronic device a wafer is provided which has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based on the single semiconductor material is formed from the epitaxial region and a second electronic component based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions in the epitaxial region, after the step of growing an epitaxial multilayer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. The user-selected configuration information includes code generation strategy selections. A configuration store is generated based on the user's selections, and includes a code generation strategy parameters file. The configuration store and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device.

IPC Classes  ?

• G06F 8/34 - Graphical or visual programming
• G06F 8/77 - Software metrics

Abstract

Provided is a coupler including a first assembly of an input unit element, an intermediate unit element, and an output unit element. Each unit element includes a first coil and a second coil arranged in a cross having a general “H” shape. A first input terminal and a second input terminal of the intermediate unit element are coupled to a first output terminal and to a second output terminal of the input unit element, a first output terminal and a second output terminal of the intermediate unit element are coupled to a first input terminal and to a second input terminal of the output unit element, and the input unit element is spatially positioned between the intermediate unit element and the output unit element.

IPC Classes  ?

• H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers

Abstract

According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 1/08 - Clock generators with changeable or programmable clock frequency

Abstract

A DC-DC converter includes a primary-side control-circuit having an oscillator driving a transformer in response to assertion of a PWM-signal to transmit power from the primary to the secondary and ceasing in response to deassertion of the PWM-signal, and a receiver demodulator circuit receiving/demodulating a feedback signal sent from the secondary to the primary by comparing an instantaneous value of an envelope indicative of voltages at the primary-coil to an average-value of the envelope to produce a reset-signal. A PWM circuit asserts the PWM-signal in response to a set-signal and deasserts the PWM-signal in response to assertion of the reset-signal. A secondary-side control-circuit rectifies the received power, asserts an intermediate feedback-signal if feedback indicative of the output voltage is greater than a reference-voltage, and connects a capacitance between the secondary and ground in response to assertion of the intermediate feedback-signal to modulate and send the feedback to the primary.

IPC Classes  ?

• H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
• H02M 1/00 - Details of apparatus for conversion

Abstract

Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination domain current buffer signal indicates a first or second data buffer in a source clock domain as a current buffer for use during a current data transfer cycle. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicating the current buffer generated. A source data transfer request signal is generated based on the source domain current buffer signal and the source data transfer request signal synchronized to generate a destination domain data transfer request signal. Transfer of data between a memory in the destination clock domain is delayed to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals

Abstract

A method includes generating, by a first motion sensor of an electronic device, first sensor data over an acquisition time window; generating first process data by processing the first sensor data to determine whether or not the electronic device is located on a stationary surface; determining whether or not the electronic device is in a stable state based on the first process data. The stable state is indicative of whether the electronic device has remained on a stationary surface or not for a first predefined time. The method includes stopping the processing of the first sensor data in response to determining that the electronic device has been in the stable state for a second predefined time.

IPC Classes  ?

• G01P 13/02 - Indicating direction only, e.g. by weather vane
• G01P 15/14 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of gyroscopes
• G06F 1/16 - Constructional details or arrangements

Abstract

A computer system is provided including a memory configured to store a computer program product, a processor configured to execute said computer program product, and a memory circuit. The computer program product includes at least one instruction to duplicate in the memory circuit a return address defined upon function call, and at least one instruction to compare a value of the return address stored in a call stack at the value of the return address duplicated in the memory circuit and to permit a function return branching only if these two values are identical.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Electronic device, comprising: a semiconductor body having a surface, an electrical conductivity P and a first doping value; at least one gate region on the surface; one or more source regions, having a second electrical conductivity N, extending in the semiconductor body at the surface and at a first side of the gate region; and at least one body contact region, of P+ type, extending in the semiconductor body at the surface and at the first side of the gate region 22. The first gate region has the shape of a stripe with main extension along a first direction. The first body contact region has a tapered shape along said first direction. The one or more source regions are adjacent to, and at least partially surround, the first body contact region.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor electronic device has a substrate region of semiconductor material; a first electronic component based on heterostructure, which has an epitaxial multilayer that extends on the substrate region and includes a heterostructure; and a separation region that extends on the substrate region. The separation region includes a polycrystalline region of semiconductor material of polycrystalline type which is arranged, along a first direction, alongside the epitaxial multilayer. The electronic device also has an epitaxial region of a single semiconductor material of monocrystalline type which extends on the substrate region. The polycrystalline region extends, along the first direction, between the epitaxial multilayer and the epitaxial region.

IPC Classes  ?

• H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

To manufacture a semiconductor electronic device a wafer is provided that has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based upon the single semiconductor material is formed starting from the epitaxial region and a second electronic component based upon a heterostructure is formed starting from the heterostructure. To grow an epitaxial multilayer, a growth mask is formed on the substrate layer; an opening is made in the growth mask, thereby exposing the second portion of the substrate layer; and the epitaxial multilayer is grown on the second portion of the substrate layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

Content is generated for a programmable computing device based on user-selected configuration information. The user-selected configuration information includes a user-selected versatile component. User-selectable versatile component configuration options for the user-selected versatile component are presented and versatile component configuration option selections for the user-selected versatile component are received. Settings for an instance of the user-selected versatile component are generated based on the received component configuration option selections. A configuration store is generated or updated based on the settings for the user-selected versatile component. Content for the programmable computing device is generated based on the configuration store. Generating the content includes associating the instance of the user-selected versatile component with a software component, with a hardware component, or combinations thereof, based on one or more of the received versatile component configuration option selections. The generated content is provided to the programmable computing device.

IPC Classes  ?

• G06F 9/445 - Program loading or initiating
• G06F 3/0482 - Interaction with lists of selectable items, e.g. menus

Abstract

A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

IPC Classes  ?

• H02K 17/14 - Asynchronous induction motors for multi-phase current having windings arranged for permitting pole-changing
• G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
• H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
• H03K 19/003 - Modifications for increasing the reliability
• H03M 1/12 - Analogue/digital converters

Abstract

A test circuit includes a set of electronic switches having a current path between a first node and a ground node, where each electronic switch has a respective control node. A set of coupling channels have one end coupled to a common test node and other ends coupled to the respective control nodes of electronic switches. A stress voltage supply source is coupled to the common test node. A set of comparator circuits includes comparator circuits having a first input node coupled, via sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to a threshold voltage node. A method of operating the test circuit is also disclosed.

IPC Classes  ?

• G01R 31/27 - Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects due to surrounding elements
• G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
• G01R 31/26 - Testing of individual semiconductor devices
• G01R 31/30 - Marginal testing, e.g. by varying supply voltage
• G01R 31/52 - Testing for short-circuits, leakage current or ground faults

Abstract

The present description concerns a method of controlling a first NFC device comprising an NFC controller coupled to an antenna, wherein a mode of charge of a second remote NFC device by the antenna is interrupted as a result of a detection, by the NFC controller, of an impedance change of the antenna, the interruption being followed by the starting of a communication, via the antenna, with a third remote NFC device.

IPC Classes  ?

• H04B 5/70 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
• H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set
• H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
• H04B 5/43 - Antennas

Abstract

A switch circuit includes a first and a second input nodes to receive a first and a second input voltages, and an output node to produce an output voltage switchable between the first and second input voltages. A first and a second pass devices are arranged in series between the first input node and the output node. A third and a fourth pass devices are arranged in series between the second input node and the output node. A first, a second, a third, and a fourth elevator circuits control, respectively, the first, second, third, and fourth pass devices. The first elevator circuit is biased between the first input voltage and a shifted ground voltage. The third elevator circuit is biased between the second input voltage and a ground voltage. The second and fourth elevator circuits are biased between the output voltage and an elevated ground voltage.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

IPC Classes  ?

• G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/24 - Bit-line control circuits

Abstract

A startup circuit includes a first circuit leg coupled between an input node and an output node and a second circuit leg coupled between the input node and the output node. The first circuit generates a first current and the second circuit leg sinks current from a first node based upon the first current. A third circuit leg is coupled between the input node and the output node and sources current to a second node based upon a voltage at the first node to thereby generate a feedback voltage at the second node. The first circuit leg increases the first current based upon the feedback voltage, in turn increasing the current sunk from the first node by the second circuit leg and increasing the current sourced to the second node by the third circuit leg to thereby generate a startup current at the output node.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

According to an embodiment, a max-pooling neuron with first and second integrator circuits, a comparator circuit, a Schmitt trigger circuit, and a pair of switches is provided. The first and second integrator circuits, respectively filter a first and a second input train from a first and a second neuron of a previous layer to generate a corresponding first and second filtered input train. The comparator circuit amplifies a difference between the first and second filtered input trains and generates an amplified differential signal. The Schmitt trigger circuit generates a binary output signal based on the amplified differential signal. The pair of switches have a common first terminal coupled to an output node of the max-pooling neuron and a common control terminal coupled to the output terminal of the Schmitt trigger circuit. The other terminals of the pair of switches are coupled to respective input trains.

IPC Classes  ?

• G06N 3/049 - Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• H03H 11/04 - Frequency selective two-port networks
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

The present disclosure is directed to a device for detecting the passage of an infrared, IR, radiation emitting body in a monitoring zone. The device has a first surface and a second surface mutually tilted and configured to face the monitoring zone. The device includes a first IR radiation sensor extending on the first surface and a second IR radiation sensor extending on the second surface. The first IR radiation sensor is configured to detect the IR radiation of the emitting body when the emitting body is in a first field of view of the first IR radiation sensor and the second IR radiation sensor is configured to detect the IR radiation of the emitting body when the emitting body is in a second field of view of the second IR radiation sensor. The first and the second fields of views are configured to be partially superimposed on each other at the monitoring zone.

IPC Classes  ?

• G01J 5/00 - Radiation pyrometry, e.g. infrared or optical thermometry
• G01J 5/07 - Arrangements for adjusting the solid angle of collected radiation, e.g. adjusting or orienting field of view, tracking position or encoding angular position
• G01J 5/20 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices

Abstract

A device includes first and second terminals configured to be respectively connected to first and second conductors of a differential two-wire bus. First and second identical resistive dividing bridges are connected between a reference node and respectively first and second nodes. Third and fourth identical resistive dividing bridges are connected between a supply node and respectively the first and second nodes. A reading circuit is configured to determine a binary state of the bus from the currents flowing through transistors of the reading circuit.

IPC Classes  ?

• H04L 12/40 - Bus networks
• H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

Abstract

An LDO regulator has a pass device arranged between an input node and an output node. The pass device is controlled at a control node by an error amplifier. A first current generator sources compensation current to the control node, a cascode device is arranged between the control node and a compensation node, and a second current generator sinks compensation current from the compensation node. A compensation capacitor is arranged between the output and compensation nodes. Load current through the pass device is sensed to generate a feedback current at a first feedback node. An input branch of a current mirror receives the feedback current. A filtering circuit is coupled between a control terminal of the input branch and a second feedback node. Output branches of the current mirror sink and source additional compensation current from the compensation node and the control node, respectively, proportional to the feedback current.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Abstract

A method of securization of programs in a memory embedded within a microcontroller includes writing a boot program into a first area of the memory and writing at least one additional program into at least one second area of the memory. One or more values of a first register are modified to provide a write protection of the first and second areas. A prohibition against modification of the one or more values of the first register is then implemented when those values are associated with a write protection state of the first area.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

The present description concerns a method comprising: transmitting, by at least one peripheral circuit of a storage system for a motor vehicle, one or more data values to be stored, to at least two circuits of the vehicle; searching for a proof of work; transmitting, when a first one of the at least two circuits has found a potential proof of work, the potential proof of work to each of the other circuits; verifying the potential proof of work; and, if the verification confirms that the potential proof of work matches the proof of work searched for, the storage, in each of the circuits, of one or more data values in a current block of a blockchain, the one or more data values being stored in association with an identification value identifying the previous block, the proof of work, and an identification value identifying the current block.

IPC Classes  ?

• H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

According to an embodiment, a sensor including a machine learning core (MLC) and a finite state machine (FSM) circuit for detecting a shock event is provided. The MLC continuously calculates a value based on the change in velocity. The FSM circuit compares the value to a first threshold and generates a first interrupt if it is greater than the first threshold. The FSM circuit then compares the value to a second threshold less than the first threshold and generates a second interrupt if it is less than or equal to the second threshold after the first interrupt. The MLC calculates a maximum value between the first and second interrupts and stores it in a register, which is read by an application processor of a host device after receiving the second interrupt. The maximum acceleration norm value is reset after a delay after the second interrupt is generated.

IPC Classes  ?

• G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values

Abstract

An interleaved coupled inductors transformer is described in accordance with various embodiments of the present disclosure. In various embodiments, the interleaved coupled inductors transformer includes a first terminal including a first port, a first branch of the first terminal, and a second branch of the first terminal approximately parallel to with the first branch of the first terminal. The interleaved coupled inductors transformer includes a second terminal spatially separate from the first terminal, the second terminal including a second port, a first branch of the second terminal, a second branch of the second terminal approximately parallel to with the first branch of the second terminal, wherein the first and second branches of the first terminal do not overlap with the first and second branches of the second terminal.

IPC Classes  ?

• H01F 27/28 - CoilsWindingsConductive connections
• H01F 27/29 - TerminalsTapping arrangements
• H01F 37/00 - Fixed inductances not covered by group

Abstract

An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/317 - Testing of digital circuits

Abstract

Micromachined ultrasonic transducer wherein a die including semiconductor material accommodates at least one ultrasonic cell. Each ultrasonic cell includes a piezoelectric structure, a cavity, and a membrane region, vertically aligned with each other. The cavity extends inside the die and downwardly delimits the membrane region. The piezoelectric structure is arranged on the membrane region and has at least one annular-shaped piezoelectric region. The micromachined ultrasonic transducer is configured to operate around the second axisymmetric vibration mode.

IPC Classes  ?

• B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
• H10N 30/02 - Forming enclosures or casings
• H10N 30/06 - Forming electrodes or interconnections, e.g. leads or terminals
• H10N 30/50 - Piezoelectric or electrostrictive devices having a stacked or multilayer structure
• H10N 30/87 - Electrodes or interconnections, e.g. leads or terminals
• H10N 30/88 - MountsSupportsEnclosuresCasings

Abstract

A pixel includes, on a first face, first trenches extending parallel to a first direction and regularly spaced in a second direction (orthogonal to the first direction) and second trenches extending parallel to the second direction and regularly spaced in the first direction. The first trenches include first notches, each first notch extending from a first trench and being aligned with a corresponding second trench. The second trenches include second notches, each second notch extending from a second trench and being aligned with a corresponding first trench.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A power conversion circuit includes a first node configured to receive a first voltage referenced to a second node configured to be coupled to a reference potential. A first power converter couples the first node to a third node. A second power converter couples a fourth node to an output node. A first capacitor couples the third node to the fourth node. A first switch connects the output node to the first node. An output switch connects the output node to a load.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H05B 47/10 - Controlling the light source

Abstract

A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.

IPC Classes  ?

• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

Methods, systems, and devices for semiconductor manufacturing are described. One such method includes forming a first layer comprising a first material. A top surface of the first layer extends along a first direction and a second direction. In some cases, the method includes forming, on at least the top surface of the first layer, a second layer comprising a second material, and forming a void in the second layer. Forming the void may expose a portion of the top surface of the first layer. In some cases, the method may include forming one or more layers on a top surface of the second layer and on the exposed portion of the top surface of the first layer. The method may also include performing a material removal operation that lifts portions of the one or more layers formed on the top surface of the second layer off of the top surface.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An authentication method can be performed in view of a pairing of a peripheral device to a companion device via a host device. The method includes initiating a pairing session and, in response to the initiating, receiving a first command by the host device. The first command comprises a first command code and a first encrypted payload to be exchanged between the peripheral device and the companion device via the host device. The first command code indicates to the host device to transfer the first command without decoding it.

IPC Classes  ?

• H04W 12/50 - Secure pairing of devices
• H04W 12/0431 - Key distribution or pre-distributionKey agreement
• H04W 12/06 - Authentication

Abstract

A circuit includes a current source, a differential pair of transistors coupled to the current source, an active load, and a current injection circuit. The differential pair of transistors has a first offset voltage and an input transconductance. The current injection circuit is configured to supply a first current and a second current to produce a second offset voltage across the differential pair of transistors opposite the first offset voltage. The first current and the second current has a same thermal dependence as the input transconductance of the differential pair of transistors.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage

Abstract

An authentication method can be performed in view of a pairing of a peripheral device to a companion device via a host device. The method includes initiating a pairing session and, in response to the initiating, receiving a first command by the host device. The first command comprises a first command code and a first encrypted payload to be exchanged between the peripheral device and the companion device via the host device. The first command code indicates to the host device to transfer the first command without decoding it.

IPC Classes  ?

• G06F 21/44 - Program or device authentication
• H04W 12/50 - Secure pairing of devices
• H04W 12/55 - Secure pairing of devices involving three or more devices, e.g. group pairing
• G06F 21/60 - Protecting data

Abstract

Provided is an integrated circuit that includes: a terminal designed to receive a signal at a rated voltage level which can rise to a maximum voltage level; an output circuit including a first transistor and a second transistor coupled in series between the terminal and an output stage; and a protection circuit designed to generate a first voltage controlling the first transistor, and a second voltage controlling the second transistor. In an activated state, the first voltage and the second voltage are obtained by dividing the voltage level of said terminal. In a deactivated state, the first voltage is obtained by the voltage level of said terminal, and the second voltage is obtained by the level of a control voltage minus a threshold voltage of a protection transistor.

IPC Classes  ?

• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
• H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
• H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Abstract

A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A method for monitoring voltage drift includes measuring a voltage across a diode of a power device, providing the measured voltage as an input to a controller, the controller being configured to run a transformer-based model, and forecasting a range of expected future values of the voltage across the diode of the power device with the transformer-based model. The transformer-based model may include a temporal fusion transformer with a temporal convolutional neural network and an adversarial compensation model with a backpropagation algorithm.

IPC Classes  ?

• G01R 31/26 - Testing of individual semiconductor devices

Abstract

An electronic device that includes: a substrate including a first contact pad; a cap including a front surface, the cap being attached to a surface of the substrate, the front surface including a first recess and a second recess within the first recess, the cap including a first leadframe embedded within the cap; a first device mounted over the cap and within the second recess; and an optical lens mounted over the cap and the first device, where a first end of the first leadframe is extended out of the cap and electrically connected to the first contact pad, and where a second end of the first leadframe is extended out of the cap at the front surface and electrically connected to the first device.

IPC Classes  ?

• G01S 7/481 - Constructional features, e.g. arrangements of optical elements
• G01S 17/08 - Systems determining position data of a target for measuring distance only

Abstract

A method for forming a graphene layer on a semiconductor substrate, a semiconductor diode utilizing the method for graphene layer formation, and an optoelectronic semiconductor device also utilizing the method for graphene layer formation are provided. An example method for disposing a graphene layer on a semiconductor substrate may include depositing a metal catalyst layer on a top surface of the semiconductor substrate and patterning the metal catalyst layer, such that one or more portions of the top surface of the semiconductor substrate are covered by one or more metal catalyst layer structures. The method may further include facilitating a graphene growth process on an exposed surface of the one or more metal catalyst layer structures, wherein the graphene growth process forms the graphene layer on the exposed surfaces of the one or more metal catalyst layer structures.

IPC Classes  ?

• H01L 29/872 - Schottky diodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/66 - Types of semiconductor device

Abstract

An authentication method is used in pairing a peripheral device to a companion device. The peripheral device sends a first identifier and a first value of a first counter to the companion device. The companion device verifies whether a pairing table stored in the companion device contains the first identifier. When the pairing table does not include the first identifier the companion device initiates a pairing session. When the pairing table includes the first identifier, the companion device compares the first value to a second value associated with the first identifier in the pairing table. In response to the first value being greater than the second value, the companion devices initiates a nominal session and in response to the first value being lower than or equal to the second value, execution of the method is stopped.

IPC Classes  ?

• G06F 21/44 - Program or device authentication
• H04W 12/50 - Secure pairing of devices
• G06F 21/60 - Protecting data
• G06F 21/84 - Protecting input, output or interconnection devices output devices, e.g. displays or monitors

Abstract

Described is a method for performing the execution of an application in a Secure Element (SE), comprising a host sending an APDU command to the SE comprising the application, processing at the SE the APDU command for execution by the application, performing a determined plurality of operations of the application commanded by the APDU command, the application determining among the plurality of application operations commanded by the APDU command a first set of operations to be executed by the application upon receiving the APDU command and at least a second set of operations. The SE performs the first set of operations to be executed by the application upon receiving the APDU command, performing a deferred execution of a second set of operations upon communication of completion of the execution of the first set of operations from the SE to the host.

IPC Classes  ?

• G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
• G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
• G06F 21/60 - Protecting data

Abstract

An integrated circuit comprises a current source, a plurality of parallel transistors, a plurality of switches, switch control circuitry, and measurement circuitry. Each switch selectively couples the current source to a corresponding transistor. The switch control circuitry is configured to, at different times, cause all the switches to close and, separately for each transistor, cause the switch associated with each transistor to close while causing all other switches to open. The measurement circuitry is configured to measure, separately for each of the transistors, a base-emitter voltage (VBE) when all the switches are closed and a VBE when only the switch associated with each transistor is closed, determine a ΔVBE for each of the plurality of transistors by calculating a difference between the VBE when only the switch associated with each transistor is closed and the VBE when all the switches are closed, and calculate an average of all the ΔVBEs.

IPC Classes  ?

• H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
• H03K 17/30 - Modifications for providing a predetermined threshold before switching
• H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors

Abstract

Electrically insulating material is molded onto a sculptured, electrically conductive leadframe structure that includes a pattern of electrically conductive formations such as a die mounting location configured to have at least one semiconductor die arranged thereon, a dummy pad and a tie bar extending between the die mounting location and the dummy pad. A pre-molded leadframe structure results from the electrically insulating material penetrating into spaces between electrically conductive formations in the pattern of electrically conductive formations. At least one portion of the tie bar extending between the die mounting location and the dummy pad is removed to electrically decouple the dummy pad from the die mounting location.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/495 - Lead-frames

Abstract

A semiconductor die is mounted on a substrate having electrically conductive substrate portions. The electrically conductive substrate portions include a die mounting location and electrically conductive leads around the die mounting location. The semiconductor die is mounted on a first surface of the die mounting location. The substrate and the semiconductor die are encapsulated in an electrically insulating encapsulation having a surface opposite the first surface. An electrically conductive path is provided to electrically couple the semiconductor die to one of the electrically conductive substrate portions. The electrically conductive path includes: a first path section extending through and/or over the electrically insulating encapsulation between the electrically conductive substrate portion and an intermediate point at the surface of the electrically insulating encapsulation, and a second path section provided via wire bonding and extending between the semiconductor die and the intermediate point at the surface of the electrically insulating encapsulation.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

A method configures a memory for use in executing an application. The configurating the memory includes defining a set of virtual memory resources associated with one or more contiguous memory areas of the memory. Contiguous virtual memory resources of the set of virtual memory resources are selectively merged based on respective security attributes of the virtual memory resources of the set of virtual memory resources, generating a merged set of virtual memory resources. A security attribute assigned to a virtual memory resource indicates the virtual memory resource is a secure memory resource, a non-secure memory resource, or a non-secure callable memory resource. Configuration information indicative of the merged set of virtual memory resources is stored for use in executing the application.

IPC Classes  ?

• G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

Abstract

The present disclosure relates to a half-bridge circuit comprising first and second PMOS transistors in series between the first node and an intermediate node, a third PMOS transistor and a fourth NMOS transistor in series between the intermediate node and the second node, and a control circuit. The control circuit comprises a bootstrap charge pump. The charge pump comprises a capacitive element having a first electrode coupled with the gate of the third transistor. The charge pump is configured to charge the capacitive element from the intermediate node and without a clock signal. The present application also relates to a device comprising two identical half-bridge circuits connected to two respective conductors of a bus.

IPC Classes  ?

• H03K 17/06 - Modifications for ensuring a fully conducting state
• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage

Abstract

An integrated circuit comprises a current source, a plurality of transistors arranged in parallel, a plurality of resistors, a plurality of switches, switch control circuitry, and measurement circuitry. Each resistor is coupled with the emitter of a respective transistor. Each switch selectively couples the current source to a respective resistor such that a bias current flows from the current source to the emitter of a respective transistor when a respective switch is closed. The measurement circuitry is coupled to the first transistor between its emitter and a respective resistor. The measurement circuitry is configured to separately measure a base-emitter voltage (VBE1) of the first transistor when all of the switches are closed and a base-emitter voltage (VBE2) of the first transistor when only the switch associated with the first transistor is closed and to determine a ΔVBE by calculating a difference between VBE2 and VBE 1.

IPC Classes  ?

• G05F 3/30 - Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
• G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
• G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements

Abstract

A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

IPC Classes  ?

• H01L 29/40 - Electrodes
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/872 - Schottky diodes

Abstract

A method of operating a time-of-flight (ToF) ranging system includes: receiving a histogram that includes a cross-talk signal generated by reflected light pulses from a cover glass of the ToF ranging system; finding, in a first region of the histogram, a first rising edge having a gradient that is larger than a threshold or is a maximum gradient in the first region, where the first rising edge is in a first histogram bin having a first value; determining a second value of a second histogram bin in the first region, where the first histogram bin precedes the second histogram bin by a pre-determined distance; estimating a ratio between the first region of the histogram and a pre-stored light pulse shape based on the first value and the second value; scaling the pre-stored light pulse shape with the estimated ratio; and subtracting the scaled pre-stored light pulse shape from the histogram.

IPC Classes  ?

• G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak

Abstract

The present disclosure relates to a device for measuring a power current supplied by a main power FET. The device includes a current measurement power FET coupled with the main FET; first and second FETs, the gates of which are coupled with each other, the first FET is coupled with the current measurement FET, in which a source/drain terminal of the second FET is coupled with a source/drain terminal of the first FET, or a source/drain terminal of the second FET is coupled with a source/drain terminal of the main FET or to a voltage source or load external to the device, and source/drain terminals of the first and second FETs are coupled with each other.

IPC Classes  ?

• G01R 31/40 - Testing power supplies

Abstract

Described herein is a microelectromechanical sensor device, comprising: a stack of a first die that integrates a pressure-detection structure and a second die that integrates an inertial detection structure, the first die constituting a cap for the inertial detection structure and being bonded to the second die so as to define a hermetic cavity. The first die has a first substrate, having a front surface and a rear surface that is bonded to said second die, a buried cavity being buried and entirely contained in the first substrate and being arranged in a position corresponding to the front surface, from which it is separated by a membrane. In particular, the aforesaid buried cavity is distinct and separate from the hermetic cavity.

IPC Classes  ?

• B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
• B81C 3/00 - Assembling of devices or systems from individually processed components
• G01C 19/5783 - Mountings or housings not specific to any of the devices covered by groups
• G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means

Abstract

Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.

IPC Classes  ?

• H03D 3/00 - Demodulation of angle-modulated oscillations
• H03D 7/16 - Multiple frequency-changing

Abstract

Methods, apparatuses, systems, and/or computer program products for using a neural network splitter to split a neural network into slices are provided. A splitter device may receive a neural network. The splitter devices may be connected to one or more other devices. The neural network may be split the neural network into slices to be deployed to the one or more other devices for execution. The neural network splitter may generate and intermediate representation of the neural network. A profiler of the neural network splitter may extract one or more features from the intermediate representation. A classifier may select one or more heuristics of the neural network features. The neural network may then determine one or more slices based on the features, heuristics, and device characteristics of the connected devices. The slices may be generated and deployed to the connected devices for execution.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/10 - Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
• B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]

Abstract

A two terminal semiconductor controlled rectifier (SCR) device has an anode terminal coupled to a first node and a cathode terminal coupled to a second node. Neither of the cathode gate or anode gate of the SCR device are connected to a triggering circuit for controlling turn on of the SCR device. The SCR device has an avalanche breakdown voltage for turn on, where that avalanche breakdown voltage is set by a breakdown avalanche of a PN junction of the SCR device. A circuit path includes a series connected chain of M Zener diodes with a blocking diode that are coupled between the first node and the second node. The circuit path has an activation voltage for turn on, where that activation voltage is dependent on N times a Zener diode reverse breakdown voltage. The activation voltage is less than the avalanche breakdown voltage.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

In accordance with an embodiment, a method for controlling a constant on-time switched mode power converter includes: generating a pulse signal having an on-time; during a soft-start phase of the power converter, successively increasing the on-time from an initial duration to a final duration, wherein the final duration is larger than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting a frequency of the pulse signal based on the feedback signal and a reference signal; and driving a power switch with the pulse signal to control the power switch and regulate the output voltage.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/36 - Means for starting or stopping converters

Abstract

A system for testing a circuit includes a phase-locked loop, a test logic circuit, and a test controller. The test logic circuit is coupled to the phase-locked loop. The test logic circuit is configured to count a number of clock cycles of the phase-locked loop using a reference clock as a reference. The reference clock is coupled to the test logic circuit. The test controller is coupled to the phase-locked loop and to the test logic circuit. The test controller is configured to measure a clock frequency of the phase-locked loop with the counted number of clock cycles received from the test logic circuit.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H03L 7/095 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

The present disclosure relates to an EIS measuring device comprising: an electrical energy storage circuit; an electronic circuit coupled to the electrical energy storage circuit and configured to be coupled to a battery whose impedance is to be measured by the EIS measuring device, a characterization circuit configured to measure an alternative current intended to circulate between the battery and the electronic circuit, and a voltage at terminals of the battery; wherein the electronic circuit is alternately configured in a first mode to pull out electrical energy of the battery and storing the electrical energy pulled-out from the battery in the electrical energy storage circuit, and in a second mode to pull out the stored electrical energy from the electrical energy storage circuit and to re-inject the electrical energy pulled-out from the electrical energy storage circuit in the battery.

IPC Classes  ?

• G01R 31/389 - Measuring internal impedance, internal conductance or related variables
• G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
• G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries