Fraunhofer Gesellschaft zur Förderung der Angewandten Forschung (Germany)
Inventor
Edelstein, Ruth Shima
Ivanov, Dmitry
Veinger, Dmitry
Roizin, Yakov
Hoffmann, Sonja
Henfling, Michael
Trupp, Sabine
Abstract
A sensing device that includes (a) an image sensor matrix that comprises a first pixel and a second pixel; wherein the first pixel is configured to generate a first detection signal indicative of a presence of a first analyte; wherein the second pixel is configured to generate a second detection signal that is indifferent to the presence of the first analyte; and (b) a processing circuit that is configured to determine the presence of the first analyte based on at least a relationship between the first detection signal and the second detection signal.
G01N 31/22 - Investigating or analysing non-biological materials by the use of the chemical methods specified in the subgroupsApparatus specially adapted for such methods using chemical indicators
2.
SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME
A solid-state imaging device includes a plurality of pixels arrayed in a two-dimensional matrix on a substrate. Each of the pixels includes a light receiving potion that performs photoelectric conversion, a microlens that condenses light to the light receiving potion, and at least one light scattering structure provided between the light receiving potion and the microlens.
For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.
A location detection system for detecting a location of a wafer within a transfer robot vacuum chamber (TRVC), the detection system may include (i) an illumination unit that is configured to direct a transmitted radiation pattern through a transparent window of the TRVC and towards one or more TRVS reflecting elements located below an upper side of a wafer holding element of the transfer robot; wherein the illumination unit is located outside the TRVC; (ii) a sensing unit that is configured to generate one or more detection signals indicative of a received radiation pattern that is reflected from the one or more TRVS reflecting elements; and (iii) a location processing circuit that is configured to detect a location of the wafer based on the one or more detection signals.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01B 11/27 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes for testing the alignment of axes
A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source/drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source/drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and/or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program/erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 27/11558 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate the control gate being a doped region, e.g. single-poly memory cells
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.
A UVC disinfection system that may include a UVC radiation illumination unit, a control unit, and a node. The node may include (i) a power supply, (ii) a UVC dose sensing unit that comprises a UVC sensing element, wherein the UVC dose sensing unit is configured to sense that the UVC radiation dose received by the node reached a predefined UVC radiation dose; and (iii) a node transmitter that is configured transmit a node unique signal following a sensing, by the UVC dose sensing unit, that the UVC radiation dose received by the node reached a predefined UVC radiation dose. The control unit is configured to control an emission of UVC radiation from the UVC radiation illumination unit based on a reception or a lack of reception of the node unique signal.
A method for manufacturing optical unit, the method includes (a) obtaining an intermediate optical unit that comprises a semiconductor portion, a transparent organic layer, the array of organic microlenses and a protective layer; (b) depositing a protective mask above a first protective layer region; (c) removing, by applying a first etch process, the second protective layer region to expose a second region of the transparent organic layer; and (d) removing, by applying a second etch process, the second region of the transparent organic layer to expose the contact pads and removing the protective mask while maintaining the first protective layer portion.
A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.
G11C 17/00 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
12.
Solid-state imaging device comprising element isolation layer with light-shielding properties and charge trapping layer
A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.
A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.
There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.
B.G. Negev Technologies and Applications Ltd., at Ben-Gurion University (Israel)
Inventor
Shalev, Gil
Roizin, Yakov
Evgeny, Pikhay
Bhattacharyya, Ie Mei
Ron, Izhar
Greental, Doron
Abstract
A biosensor that includes a semiconductor active region; a sensing region configured to contact a fluid; and multiple electrodes that comprise decoupling electrodes and additional electrodes. The decoupling electrodes may be configured, wherein operating in a first mode, to prevent a formation of a top conductive channel within the semiconductor active region; and wherein the additional electrodes are configured, wherein operating in the first mode, to independently control (i) one or more properties of one or more other conductive channels formed within the semiconductor active region, and (ii) a Debye length at an interface between the sensing region and the fluid.
A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.
H01L 31/119 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
This semiconductor device is provided with a memory element writing unit (10) having: a memory element (1) which can be electrically written one time only and stores a binary value; a writing control section (2) which is connected to the memory element (1) via a first node signal (N1) and performs writing into the memory element (1) on the basis of a write control signal (CT1) instructing writing into the memory element (1); and a write-state detection circuit (5) which is capable of detecting the state that the memory element (1) is already written from a measurement signal obtained by measuring the first node signal (N1). If a detection signal indicating the already-written state of the memory element (1) is received from the write-state detection circuit (5) after the writing into the memory element (1) is started, the writing control section (2) stops the writing operation when a given period of time has elapsed after the detection of the already-written state of the memory element (1).
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
A solid-state imaging device includes a first semiconductor substrate, photoelectric conversion portions arrayed on the first semiconductor substrate and configured to convert incident light to charges, a charge storage portion configured to hold charges transferred from a corresponding one of the photoelectric conversion portions via a transfer transistor, and an interconnect layer stacked on the first semiconductor substrate and including a plurality of metal interconnects. The incident light enters the first semiconductor substrate from a back surface side that is an opposite side to the interconnect layer. The solid-state imaging device further includes a light absorbing film between the photoelectric conversion portions and the metal interconnects.
A solid-state imaging apparatus includes photoelectric conversion regions arranged close to a surface of a semiconductor substrate and a recessed portion provided above each photoelectric conversion region in the semiconductor substrate. Further, the solid-state imaging apparatus includes a light transmissive film embedded in the recessed portion. With this configuration, the performance of the solid-state imaging apparatus is improved, such as improvement of sensitivity and reduction in color mixture.
A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A UV radiation sensor that includes an area that is filled with a dielectric material, the area comprises a first portion of a first thickness and a second trench portion with dielectric of a second thickness, wherein the first thickness is smaller than the second thickness; a floating gate that comprises a first floating gate portion that is positioned above the first area portion and a second floating gate portion that is positioned above the trench portion, wherein the second floating gate portion comprises multiple segments, wherein there are one or more gaps between two or more of the multiple segments; a charging element for charging the floating gate; and a readout element for reading the floating gate.
An ultraviolet sensor that may include a group of serially connected photovoltaic diodes of alternating polarities; a selective blocking portion that is configured to prevent ultraviolet radiation from reaching photovoltaic diodes that belong to the group and are of a first polarity, while allowing the ultraviolet radiation to reach photovoltaic diodes that belong to the group and are of a second polarity; and an interface for providing an output signal of the group, the output signal is indicative of ultraviolet radiation sensed by the photovoltaic diodes that belong to the group and are of the second polarity.
H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
A radiation sensor that may include a first transistor, a first isolated conductive structure that comprises a floating gate of the first transistor, a first group of radiation sensing diodes that are coupled to each other, wherein the first group is configured to convert sensed radiation that is sensed by the first group to a first output signal, and to change a state of the first isolated conductive structure using the first output signal, a second transistor, a second isolated conductive structure that comprises a floating gate of the second transistor, and a second group of radiation sensing diodes that are coupled to each other, wherein the second group is configured to convert sensed radiation that is sensed by the second group to a second output signal, and to change a state, under a control of the first transistor, of the second isolated conductive structure using the second output signal.
Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03K 17/04 - Modifications for accelerating switching
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
This solid-state imaging device comprises a pixel array in which pixels (10) are arranged in a matrix form. The pixels (10) have a photoelectric conversion unit (24) that generates a signal charge on the basis of incident light, and light-shielding element separation layers (22, 23) that surround the periphery of the photoelectric conversion unit (24). In the row direction and the column direction, the element separation layers (22, 23) of adjacent pixels (10) are mutually separated. In the row direction and the column direction, in a region sandwiched by the element separation layers (22, 23) of adjacent pixels (10), a charge storage layer (13) and a charge capture layer (11) are provided. The charge storage layer (13) stores the signal charge, and the charge capture layer (11) suppresses the incidence of light on the charge storage layer (13).
A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.
H01L 31/119 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
This solid-state imaging device 100 is provided with: an N-type semiconductor layer 101; an element layer 102 which comprises a photoelectric conversion element and an active element; a wiring layer 103 which performs wiring to the active element; and an element isolation trench 135 which penetrates through the semiconductor layer 101. The element layer 102 comprises a P-type region 112 and an N-type region 113. A first hole accumulation layer 103a is formed on a surface of the semiconductor layer 101, said surface being on the reverse side from the element layer 102. A second hole accumulation layer 130b is formed on portions of the semiconductor layer 101 and the element layer 102, said portions being in contact with the element isolation trench 135. The P-type region 112 of the element layer 102 and the first hole accumulation layer 103a are connected to each other by means of the second hole accumulation layer 130b.
A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An operational transconductance amplifier, that may include a first differential pair that comprises a first transistor and a second transistor that are coupled to each other at a certain node; wherein the first differential pair is configured to convert a differential input voltage to first and second output currents; a current source that is coupled to the certain node and may include an adjustable current sources; and a feedback unit that is coupled to the certain node and is configured to (a) receive the differential input voltage, and maintain a voltage of the certain node substantially fixed regardless of changes in the differential input voltage.
An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/024 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
G01R 33/02 - Measuring direction or magnitude of magnetic fields or magnetic flux
G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
31.
Gallium nitride based ultra-violet sensor with intrinsic amplification and method of operating same
A UV sensor includes a GaN stack including a low-resistance GaN layer formed over a nucleation layer, and a high-resistance GaN layer formed over the low-resistance GaN layer, wherein a 2DEG conductive channel exists at the upper surface of the high-resistance GaN layer. An AlGaN layer is formed over the upper surface of the high-resistance GaN layer. A source contact and a drain contact extend through the AlGaN layer and contact the upper surface of the high-resistance GaN layer (and are thereby electrically coupled to the 2DEG channel). A drain depletion region extends entirely from the upper surface of the high-resistance GaN layer to the low-resistance GaN layer under the drain contact. An electrical current between the source and drain contacts is a function of UV light received by the GaN stack. An electrode is connected to the low-resistance GaN layer to allow for electrical refresh of the UV sensor.
H01L 31/112 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor
G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/024 - Arrangements for cooling, heating, ventilating or temperature compensation
32.
Lateral diffused metal oxide semiconductor field effect (LDMOS) transistor and device having LDMOS transistors
A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate. Each one of the first region and the second region has a substantially uniform thickness
Light detecting structures comprising germanium (Ge) photodiodes formed in a device layer of a germanium on-insulator (GeOI) wafer, focal planes arrays based on such Ge photodiodes (PDs) and methods for fabricating such Ge photodiodes and focal plane arrays (FPAs). An FPA includes a Ge-on-GeOI PD array bonded to a ROIC where the handle layer of the GeOI layer is removed. The GeOI insulator properties and thickness can be designed to improve light coupling into the PDs.
37 - Construction and mining; installation and repair services
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Technical support services concerning the modification of integrated circuits designs, namely, relating to the transfer, optimization, and porting of integrated circuits to assist customers with the modification of integrated circuit designs to enable the manufacture of such designs Manufacture of integrated circuits to order per the specification of others; Technical support services, namely, providing technical advice related to the manufacture of integrated circuits Design services from specified blocks of an integrated circuit to a complete integrated circuit to enable the manufacture of integrated circuits for others
For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A method for manufacturing a semiconductor device, the method may include forming a first part of a hollow in first part of a first layer of the semiconductor device and coating a sidewall of the first part of the hollow with an etch stop material, wherein the forming of the first part of the hollow comprises performing at least one iteration of (i) anisotropic etching and (ii) deposition of the etch stop material; wherein when completed, the semiconductor device comprises a radio frequency (RF) circuit; forming a second part of the hollow in a second part of the first layer by performing isotropic etching that involves directing plasma through the first part of the hollow; wherein the second part of the hollow reaches either (a) a bottom of a second layer of the semiconductor device or (b) the RF circuit; and wherein at least a majority of the second part of the hollow is wider than at least a majority of the first part of the hollow.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
39.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
This semiconductor device is provided with: a gate electrode (5) which is formed on a semiconductor substrate (1), with a gate insulating film (4) being interposed therebetween; an offset drain layer (2) which is provided in the semiconductor substrate (1) on one side of the gate electrode (5); a drain layer (7) which is positioned above the offset drain layer (2); and a source layer (8) which is provided in the semiconductor substrate (1) on the other side of the gate electrode (5). This semiconductor device is also provided with: a protective film (9) which covers the upper surface of the semiconductor substrate (1); a field plate (13) which is provided on the protective film (9) and has a portion that is positioned above the offset drain layer (2); and a field plug (12) which is provided within the protective film (9) so as to be positioned above the offset drain layer (2) without reaching the offset drain layer (2), while being connected to the field plate (13).
For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Some demonstrative embodiments include an apparatus including a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A system that may include (a) a radiation source that is constructed and arranged to illuminate an object with radiation during consecutive time frames of microsecond-scale duration, wherein radiation emitted during one time frame differs by energy from radiation transmitted during an adjacent time frame; and (b) a CMOS sensor that may include a readout circuit and CMOS pixels. Each CMOS pixel may include a radiation sensing element and in-pixel memory elements. Different in-pixel memory elements are constructed and arranged to sample a state of the radiation sensing element during different time frames of the consecutive time frames.
An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A sensor circuit having a Single Photon Avalanche Diode (SPAD) and an active quenching circuit including a quenching transistor controlled by a one-shot (or similar) circuit is disclosed. The quenching transistor applies a reverse-bias voltage level on the cathode of the SPAD. During photon detection events, pulses generated by the SPAD's avalanche breakdown trigger the one-shot circuit to de-actuate the quenching transistor, allowing the cathode potential to drop below the SPAD's breakdown voltage. After a delay period, which is defined by the one-shot's configuration, allows reliable completion of the avalanche breakdown process, the one-shot circuit re-actuates the quenching transistor such that the SPAD's cathode is refreshed to the reverse-bias voltage level. The one-shot circuit is optionally coupled by way of capacitors to the SPAD and the quenching transistor to facilitate implementation using standard CMOS elements. The sensor is suitable for use in a LIDAR system.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.
Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/00 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat
G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively.
A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.
A hybrid Micro-Electro-Mechanical-System-Floating-Gate (MEMS-FG) device includes an electrically isolated non-volatile memory (floating) structure including a polysilicon gate structure connected by a metal via to a fixed electrode, where the polysilicon gate structure also forms the gate of an NVM cell, and the fixed electrode forms part of a lever-type or membrane-type ohmic MEMS switch. An initial charge is written before each sensing operation onto the floating structure by way of the NVM cell. During each sensing operation, sensor data is effectively written directly onto the NVM cell by way of either maintaining or discharging the initial charge, where discharge of the initial charge occurs when a predetermined event (e.g., contact by a fingerprint ridge) produces an actuating force that biases a movable electrode of the MEMS switch against the fixed electrode. The sensor data is read out from the NVM cell after each sensing operation.
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A solid-state fingerprint sensor including an array of pixels, each pixel including an electrically isolated NVM structure, a security NVM cell and a normally-open MEMS switch. The electrically isolated NVM structure includes a polycrystalline silicon gate structure connected by a metal via structure to a fixed electrode that forms part of the MEMS switch. Initial charges stored on the electrically isolated NVM structures before each sensing operation are discharged to ground by the MEMS switch when a fingerprint ridge is aligned with the pixel and produces an applied actuating force on the MEMs switch. Final pixel charge values (i.e., either the initial charge or no charge) stored on each electrically isolated NVM structure after each sensing operation are encrypted using security bits stored on the security NVM cells such that only encrypted image data is transmitted from the pixels to external circuitry.
Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a multi-split gate. For example, an Integrated Circuit (IC) may include at least one MOS transistor, the MOS transistor may include a source; a drain; a body; and a multi-split gate including a control gate component configured to control conductivity of the MOS transistor, and at least first and second field plate gate components, the first field plate gate component is electrically isolated from the second field plate gate component, the first and second field plate gate components are electrically isolated from the control gate.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
09 - Scientific and electric apparatus and instruments
37 - Construction and mining; installation and repair services
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Integrated circuits Technical support services concerning the modification of integrated circuits designs, namely, relating to the transfer, optimization, and porting of integrated circuits to assist customers with the modification of integrated circuit designs to enable the manufacture of such designs Manufacture of integrated circuits to order per the specification of others; Technical support services, namely, providing technical advice related to the manufacture of integrated circuits Design services from specified blocks of an integrated circuit to a complete integrated circuit to enable the manufacture of integrated circuits for others
53.
Schmitt trigger circuit with hysteresis determined by modified polysilicon gate dopants
A Schmitt trigger's hysteresis is established by standard and non-standard MOSFETs having different (lower/higher) threshold voltages. For example, a standard n-channel transistor having a relatively low threshold voltage (e.g., 1V) sets the lower trigger switching voltage, and a non-standard n-channel transistor (e.g., an n-channel source/drain and a polysilicon gate doped with a p-type dopant) exhibits a relatively high threshold voltage (e.g., 2V) that sets the higher trigger switching voltage. An output control circuit generates the Schmitt trigger's digital output signal based on the on/off states of the two (non-standard and standard) MOSFETs, whereby the changes digital output signal between two values when the analog input signal falls below the lower threshold voltage (i.e., when both MOSFETs are turned on/off) and rises above the higher threshold voltage (i.e., when both MOSFETs are turned off/on). Self-resetting and other circuits utilize the Schmitt trigger to facilitate, e.g., high dynamic range image sensor pixels.
H03K 3/35 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
ON, whereby the hybrid CMOS SOI switch achieves improved FOM. The MOS transistors may also function as drivers during programming (switching) of direct-heating-type PCM cells.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
55.
Device and system of a silicon controlled rectifier (SCR)
Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
56.
Composition and method for forming a dielectric layer
A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.
B32B 3/10 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C08J 9/26 - Working-up of macromolecular substances to porous or cellular articles or materialsAfter-treatment thereof by elimination of a solid phase from a macromolecular composition or article, e.g. leaching out
B82Y 30/00 - Nanotechnology for materials or surface science, e.g. nanocomposites
B82Y 40/00 - Manufacture or treatment of nanostructures
57.
Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate
A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A laterally diffused metal oxide semiconductor (LDMOS) device that may include an oxide region that comprises a bottom surface; a drain that is positioned between a left drift region and a right drift region and below the bottom surface; wherein the oxide region further comprises a first sloped surface and a second sloped surface; wherein a first angle between the first sloped surface and the bottom surface does not exceed twenty degrees; and wherein a second angle between the second sloped surface and the bottom surface of the oxide region does not exceed twenty degrees.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
59.
Backside illuminated (BSI) CMOS image sensor (CIS) with a resonant cavity and a method for manufacturing the BSI CIS
A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot resonator comprises a front reflector, a back reflector and an active Silicon layer between the front reflector and the back reflector.
A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial layer and to the first metal layer; removing the sacrificial layer by a second removal process that is less aggressive than the first removal process; fabricating an insulator layer on the first metal layer; and depositing a second metal layer on the insulator layer.
Gas sensing using MTJ elements to capture/store gas concentration level data for readout at room temperature. In one embodiment, during reset the MTJ elements are heated above blocking temperatures of their storage layers while applying a first magnetic biasing force to set initial magnetic orientations. During gas sensing, reaction heat from a gas sensing element combines with control heat to raise each MTJ element's temperature from a work point temperature above its blocking temperature only when the target gas exceeds an associated concentration level, whereby a second magnetic biasing force causes the magnetic orientation to switch directions. During readout, read currents are measured to determine the MTJ elements' final resistance states, which indicate their switched/non-switched states, and the resistance states are correlated with stored data to determine the measured gas concentration level. The MTJ elements are cooled after reset and gas sensing to facilitate accurate CDS readout data.
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
62.
Semiconductor gas sensor using magnetic tunnel junction elements
A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layer's blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ element's temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layer's magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout. In one embodiment, multiple MTJ elements connected in a NAND-type string switch at different concentration levels to provide highly accurate quantitative measurement data.
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
64.
Radioisotope power source embedded in electronic devices
An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
65.
Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate structure, and a diode connected to drain terminals of the asymmetrical transistors. The injection transistor is configured with relatively high source/drain-to-gate capacitances to facilitate EEPROM-type (floating gate) program/erase operations (e.g., hot carrier injection and band-to-band tunneling of holes), and the readout transistor is configured (e.g., using a threshold voltage implant) to facilitate low-voltage readout operations. The diode is configured to function both as a limiting resistor that prevents over-erase during high-voltage erase operations, and also to prevent sneak (leakage) currents during low-voltage readout operations. The diode is implemented using either p-n junction or Schottky diode configurations formed on bulk silicon, or a lateral diode configurations disclosed for SOI substrates. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
67.
Image sensor module and a method for evaluating an image sensor
An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal layer dielectric material is positioned between the first and second capacitor conductive plates; wherein at least the certain portion of the intermediate metal layer dielectric material, the first capacitor conductive plate and the second capacitor conductive plate form a high voltage capacitor; and wherein the intermediate metal layer conductor is configured to supply power to a group of transistors of the die while the first conductor is configured to supply power only to a sub-group of the transistors of the die.
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
According to an embodiment of the invention there may be provided a die that may include (a) a first region of a first type; (b) a first conductor that contacts the first region; (c) a substrate having a substrate portion of the first type; wherein the substrate portion contacts the first region; an intermediate region of a second type; wherein the first type and the second type are selected from an n-type semiconductor and a p-type semiconductor; wherein the first type differs from the second type; (d) a second region of the second type; (e) a second conductor that contacts the second region; (f) a third region of the second type; (g) a third conductor that contacts the third region; (h) a fourth region of the first type; wherein the third region contacts the fourth region and does not contact the intermediate region; (i) a fourth conductor that contacts the intermediate region to form a first Schottky diode. A doping concentration of the intermediate region may be lower that a doping concentration of each one of the second region and the third region. A doping concentration of the substrate portion may be lower than a doping concentration of the first region. The third and fourth conductors may be electrically coupled to each other.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
71.
Floating gate NVM with low-moisture-content oxide cap layer
2 generated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
73.
High-speed compare operation using magnetic tunnel junction elements including two different anti-ferromagnetic layers
A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
74.
Logic unit including magnetic tunnel junction elements having two different anti-ferromagnetic layers
A logic unit for security engines or content addressable memory including Magnetic Tunnel Junction (MTJ) elements connected in series to form a NAND-type string, where each MTJ element includes a storage layer and a sense layer having different anti-ferromagnetic materials respectively having higher and lower blocking temperatures. During write/program, the string is heated above the higher blocking temperature, and magnetic fields are used to store bit values of a confidential logical pattern in the storage layers. The string is then cooled to an intermediate temperature between the higher and lower blocking temperatures and the field lines turned off to store bit-bar (opposite) values in the sense layers. During a pre-compare operation, the MTJ elements are heated to the intermediate temperature, and an input logical pattern is stored in the sense layers. During a compare operation, with the field lines off, a read current is passed through the string and measured.
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H03K 19/003 - Modifications for increasing the reliability
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
A soft-start circuit for a switching regulator (e.g., a buck converter) in which the soft-start circuit supplies a DC ramp voltage to the switch regulator's pre-driver such that the pulsed gate voltage supplied to power switch during the initial soft-start operating phase includes a series of pulses having amplitudes that respectively gradually change (e.g., sequentially increase from 0V to the system operating voltage), whereby the regulated output voltage passed from the power switch to the load is gradually increased at a rate that prevents voltage overshoot and inrush current. The DC ramp voltage is generated, for example, by a current source that begins charging a capacitor at the beginning of the initial soft-start operating phase. This arrangement allows a constant-frequency ramp signal generated by a single oscillator to be shared by multiple switch regulators that are fabricated on an IC chip.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02M 1/36 - Means for starting or stopping converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
76.
Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask
A double-RESURF LDMOS fabrication method utilizes a shared mask to form separately patterned N+ buried layer (NBL) and P+ buried layer (PBL) regions. The mask includes two opening types (e.g., large and small), and the P-type and N-type implant materials are separately directed onto the mask at different implant angles, such that the N-type implant passes through both opening types to form a first pattered implant region in both a first region and a surrounding second region, and such that the P-type implant material passes only through the larger openings and forms a second pattered implant region only in the first substrate portion. An optional epitaxial layer is deposited over the substrate and annealed to form the separately patterned PBL and NBL in the epitaxial layer, where a portion of the PBL diffuses above the NBL and forms a P-surf region below the LDMOS's N-drift region.
H01L 21/33 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising three or more electrodes
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.
A self-adjustable current source control circuit utilizes a replica output stage, a sink current source that generates a reference current, and a negative feedback circuit to generate a sink current between a linear regulator output terminal and ground only when a load circuit connected to the linear regulator is in a low power consuming state. The replica output stage includes an 1:N scaled replica of the linear regulator's NMOS (or NPN) output stage transistor, and the negative feedback circuit utilizes two PMOS (or PNP) negative feedback transistors having the same N:1 size ratio and connected as a common gate amplifier, whereby one of the two negative feedback transistors turns on to draw the desired sink current from the regulator output terminal only when the load current falls below N times the reference current (i.e., only the load current is drawn through the output stage transistor during high load current conditions).
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
79.
Deep silicon via as a drain sinker in integrated vertical DMOS transistor
ON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A method of fabricating a nanoshell is disclosed. The method comprises coating a nanometric core made of a first material by a second material, to form a core-shell nanostructure and applying non-chemical treatment to the core-shell nanostructure so as to at least partially remove the nanometric core, thereby fabricating a nanoshell. The disclosed nanoshell can be used in the fabrication of transistors, optical devices (such as CCD and CMOS sensors), memory devices and energy storage devices.
H01L 51/42 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals
B82Y 25/00 - Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
B82Y 30/00 - Nanotechnology for materials or surface science, e.g. nanocomposites
B82Y 40/00 - Manufacture or treatment of nanostructures
H01G 11/36 - Nanostructures, e.g. nanofibres, nanotubes or fullerenes
B32B 3/20 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of hollow pieces, e.g. tubesLayered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of pieces with channels or cavities
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H01G 11/24 - Electrodes characterised by structural features of the materials making up or comprised in the electrodes, e.g. form, surface area or porosityElectrodes characterised by the structural features of powders or particles used therefor
H01G 11/30 - Electrodes characterised by their material
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
H01M 4/02 - Electrodes composed of, or comprising, active material
B01J 13/04 - Making microcapsules or microballoons by physical processes, e.g. drying, spraying
B01J 13/20 - After-treatment of capsule walls, e.g. hardening
B32B 15/02 - Layered products essentially comprising metal in a form other than a sheet, e.g. wire, particles
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 27/28 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
H01L 27/30 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for either the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
H01L 27/32 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 51/56 - Processes or apparatus specially adapted for the manufacture or treatment of such devices or of parts thereof
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
81.
Single-exposure high dynamic range CMOS image sensor pixel with internal charge amplifier
A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
82.
Method for producing photovoltaic device isolated by porous silicon
Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. (Israel)
Inventor
Roizin, Yakov
Pikhay, Evgeny
Chen-Zamero, Irit
Eli, Ora
Asscher, Micha
Saar, Amir
Abstract
Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P− epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. (Israel)
Inventor
Roizin, Yakov
Pikhay, Evgeny
Chen-Zamero, Irit
Eli, Ora
Asscher, Micha
Saar, Amir
Abstract
A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P− epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P− epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.
H01L 31/042 - PV modules or arrays of single PV cells
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
84.
Shared readout low noise global shutter image sensor
A global shutter image sensor includes an array of pixel groups arranged in rows and columns, each pixel group including four pixels and a shared readout circuit having a floating diffusion. Each pixel includes a photodiode, a transfer gate and a charge coupled gate (CCG) device. The CCG devices are coupled in series with the floating diffusion of the shared readout circuit. Control circuitry controls the image sensor such that all of the pixels simultaneously capture image information (charges) and then transfer the captured charges to the CCG devices during a global shutter operation. The control circuit then controls the CCG devices to act as a shift register that transfers the captured charges to the floating diffusion during sequential correlated double sampling readout phases. The readout circuit includes a shared reset transistor, a source-follower and row select transistor, and each pixel group is controlled by eight or fewer control signals.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A method for operating a global shutter image sensor includes performing both a global shutter (image capture) operation and a rolling shutter (readout) operation. During the global shutter operation, image information (charges) are captured by photodiodes in every pixel, and then simultaneously transferred to charge coupled gate (CCG) devices provided in each pixel. The rolling shutter operation includes performing multiple correlated double sampling (CDS) readout phases utilizing readout circuits that are shared by groups of pixels (e.g., four pixels share each readout circuit) having CCG devices connected in a chain. After resetting a floating diffusion in the readout circuit, a first captured charge is transferred to floating diffusion for readout, and the remaining charges are shifted along the CCG chain. The remaining CCG devices are then sequentially read out by repeating the read-and-shift operation. The readout operation is then repeated for each row of pixel groups.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
ON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.
A method of fabricating a nanoshell is disclosed. The method comprises coating a nanometric core made of a first material by a second material, to form a core-shell nanostructure and applying non-chemical treatment to the core-shell nanostructure so as to at least partially remove the nanometric core, thereby fabricating a nanoshell. The disclosed nanoshell can be used in the fabrication of transistors, optical devices (such as CCD and CMOS sensors), memory devices and energy storage devices.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
B32B 3/20 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of hollow pieces, e.g. tubesLayered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of pieces with channels or cavities
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01M 4/02 - Electrodes composed of, or comprising, active material
B82Y 30/00 - Nanotechnology for materials or surface science, e.g. nanocomposites
B82Y 40/00 - Manufacture or treatment of nanostructures
C07K 2/00 - Peptides of undefined number of amino acidsDerivatives thereof
91.
COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER
A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.
A power supply for converting AC to a regulated DC output current, utilizing two serial switched mode power supplies, the first providing an intermediate DC output voltage with only moderate ripple properties, this output being input to the second, which operates as a DC/DC converter to provide the desired output with low ripple and good regulation. The diode rectifier assembly has no reservoir/smoothing capacitor, or one of much smaller capacitance than in prior art power supplies. The large resulting rectifier output ripple is overcome by use of the two power supply units, at least the first having a smoothing capacitor at its output. A majority of the energy stored in this capacitor is utilized during each AC half cycle. Such power supplies also provide improved hold-up times. The power supply is also constructed to have low standby power consumption, by use of a double burst configuration.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/14 - Arrangements for reducing ripples from DC input or output
An endoscope system includes a host device and an endoscope including a very small area CMOS image sensor having only four pads (power, ground, digital in, analog out), and including an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad to the host device of the endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. The endoscope housing thus requires only four wires and is made very small.
A method and system for processing fluoride-containing wastewater includes treating the wastewater with brine (waste) created by the regeneration process implemented by in ion exchanging water softener. The brine, which is typically disposed of, contains both calcium and magnesium salts, in varying concentrations and ratios. The regeneration process brine is added to the fluoride-containing wastewater within a reaction tank, and the fluoride ion concentration is monitored. When the fluoride ion concentration falls below a predetermined level (e.g., 15 ppm), the flow of regeneration process brine is stopped. A pH controller monitors the pH within the reaction tank, and adds a basic agent to ensure that the pH remains above a predetermined level (e.g., pH>9). The pH control results in a clear effluent, and a sludge having a high settling rate and a high dewater ability.
A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
96.
Device having an avalanche photo diode and a method for sensing photons
A semiconductor device that may include an avalanche photodiode (APD), the APD may include: a first doped region of a first polarity; a buried guard ring of a second polarity, the second polarity is opposite to the first polarity, the buried guard ring is spaced apart from the first doped region and is positioned below the first doped region; a well of the second polarity, wherein the well interfaces the first doped region to form a p-n junction; and a second doped region of the second polarity, the second doped region is spaced apart from the first doped region.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
A charger for recharging the batteries of a portable electronic device even when no external power source is available. A battery or cell is installed within the charger, and when no access is available to a fixed power source into which the charger can be plugged, the internal battery or cell can be used to recharge the electronic device. The internal battery can be a primary battery or a secondary battery. In the latter case, the internal battery can be maintained in a charged state by means of circuitry which, when the charger is plugged into the external power source, charges the internal battery as well as the battery of the electronic device. The external power source can be either an AC power wall socket, in which case the charger includes AC/DC voltage conversion circuits, or a car lighter socket, or the DC output of a conventional wall charger.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02J 3/32 - Arrangements for balancing the load in a network by storage of energy using batteries with converting means
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.
A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams. The 3D NVM array effectively includes multiple NVM NAND string structures, where each NAND string structure is formed by multiple series-connected NVM memory cells disposed along an associated bitline structure.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
100.
Method for generating a three-dimensional NAND memory with mono-crystalline channels using sacrificial material
A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
