Ultrata LLC

United States of America

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G06F 3/06 - Digital input from, or digital output to, record carriers 33
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units 13
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures 10
G06F 12/0817 - Cache consistency protocols using directory methods 10
G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data 10
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Found results for  patents

1.

Memory fabric software implementation

      
Application Number 17687148
Grant Number 11899931
Status In Force
Filing Date 2022-03-04
First Publication Date 2022-11-03
Grant Date 2024-02-13
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems
  • G06F 16/18 - File system types
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

2.

Infinite memory fabric hardware implementation with router

      
Application Number 17582416
Grant Number 11733904
Status In Force
Filing Date 2022-01-24
First Publication Date 2022-08-18
Grant Date 2023-08-22
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects; wherein a set of data is stored within the first memory of the memory module; wherein the memory module dynamically determines that at least a portion of the set of data will be transferred from the first memory to the second memory; and wherein, in response to the determination that at least a portion of the set of data will be transferred from the first memory to the second memory, the router is configured to identify the portion to be transferred and to facilitate execution of the transfer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures
  • G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation

3.

Utilization of a distributed index to provide object memory fabric coherency

      
Application Number 17403468
Grant Number 11775171
Status In Force
Filing Date 2021-08-16
First Publication Date 2022-05-05
Grant Date 2023-10-03
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

4.

Object memory data flow instruction execution

      
Application Number 17395781
Grant Number 11768602
Status In Force
Filing Date 2021-08-06
First Publication Date 2022-03-31
Grant Date 2023-09-26
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

5.

Object memory interfaces across shared links

      
Application Number 16996690
Grant Number 11281382
Status In Force
Filing Date 2020-08-18
First Publication Date 2020-12-03
Grant Date 2022-03-22
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can utilize a memory fabric protocol between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes to distribute and track the memory objects across the object memory fabric. The memory fabric protocol can be utilized across a dedicated link or across a shared link between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/00 - Error detection; Error correction; Monitoring
  • G06F 12/0815 - Cache consistency protocols
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 12/04 - Addressing variable-length words or parts of words
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

6.

Distributed index for fault tolerant object memory fabric

      
Application Number 16986978
Grant Number 11573699
Status In Force
Filing Date 2020-08-06
First Publication Date 2020-11-19
Grant Date 2023-02-07
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

7.

Infinite memory fabric hardware implementation with memory

      
Application Number 16883701
Grant Number 11256438
Status In Force
Filing Date 2020-05-26
First Publication Date 2020-11-12
Grant Date 2022-02-22
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein the first memory has a lower latency than the second memory, and wherein each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions, wherein a set of data is stored within the first memory of the memory module; wherein the memory module is configured to receive an indication of a subset of the set of data that is eligible to be transferred between the first memory and the second memory; and wherein the memory module dynamically determines which of the subset of data will be transferred to the second memory based on access patterns associated with the object memory fabric.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

8.

Infinite memory fabric streams and APIs

      
Application Number 16814583
Grant Number 10922005
Status In Force
Filing Date 2020-03-10
First Publication Date 2020-07-02
Grant Date 2021-02-16
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/54 - Interprogram communication

9.

Infinite memory fabric hardware implementation with router

      
Application Number 16545640
Grant Number 11231865
Status In Force
Filing Date 2019-08-20
First Publication Date 2020-02-06
Grant Date 2022-01-25
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects; wherein a set of data is stored within the first memory of the memory module; wherein the memory module dynamically determines that at least a portion of the set of data will be transferred from the first memory to the second memory; and wherein, in response to the determination that at least a portion of the set of data will be transferred from the first memory to the second memory, the router is configured to identify the portion to be transferred and to facilitate execution of the transfer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures
  • G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation

10.

Utilization of a distributed index to provide object memory fabric coherency

      
Application Number 16567474
Grant Number 11126350
Status In Force
Filing Date 2019-09-11
First Publication Date 2020-01-02
Grant Date 2021-09-21
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

11.

Object memory interfaces across shared links

      
Application Number 16266460
Grant Number 10809923
Status In Force
Filing Date 2019-02-04
First Publication Date 2019-06-06
Grant Date 2020-10-20
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can utilize a memory fabric protocol between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes to distribute and track the memory objects across the object memory fabric. The memory fabric protocol can be utilized across a dedicated link or across a shared link between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/00 - Error detection; Error correction; Monitoring
  • G06F 12/0815 - Cache consistency protocols
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 12/04 - Addressing variable-length words or parts of words
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

12.

Memory fabric software implementation

      
Application Number 16269833
Grant Number 11269514
Status In Force
Filing Date 2019-02-07
First Publication Date 2019-06-06
Grant Date 2022-03-08
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

IPC Classes  ?

  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems
  • G06F 16/18 - File system types
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 12/02 - Addressing or allocation; Relocation

13.

Memory fabric operations and coherency using fault tolerant objects

      
Application Number 16254043
Grant Number 10895992
Status In Force
Filing Date 2019-01-22
First Publication Date 2019-05-23
Grant Date 2021-01-19
Owner Ultrata LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can distribute and track the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes on a per-object basis. Distributing the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes can comprise storing, on a per-object basis, each memory object on two or more nodes of the plurality of hardware-based processing nodes of the object memory fabric.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/00 - Error detection; Error correction; Monitoring
  • G06F 12/0815 - Cache consistency protocols
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 12/04 - Addressing variable-length words or parts of words
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

14.

Infinite memory fabric streams and APIs

      
Application Number 16254079
Grant Number 10606504
Status In Force
Filing Date 2019-01-22
First Publication Date 2019-05-23
Grant Date 2020-03-31
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/54 - Interprogram communication

15.

Infinite memory fabric streams and APIS

      
Application Number 15946860
Grant Number 10235084
Status In Force
Filing Date 2018-04-06
First Publication Date 2018-08-09
Grant Date 2019-03-19
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/54 - Interprogram communication

16.

Distributed index for fault tolerant object memory fabric

      
Application Number 15946918
Grant Number 10768814
Status In Force
Filing Date 2018-04-06
First Publication Date 2018-08-09
Grant Date 2020-09-08
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/08 - Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

17.

Utilization of a distributed index to provide object memory fabric coherency

      
Application Number 15938061
Grant Number 10452268
Status In Force
Filing Date 2018-03-28
First Publication Date 2018-08-02
Grant Date 2019-10-22
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/08 - Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 12/0877 - Cache access modes
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data

18.

Infinite memory fabric hardware implementation with router

      
Application Number 15852228
Grant Number 10430109
Status In Force
Filing Date 2017-12-22
First Publication Date 2018-07-05
Grant Date 2019-10-01
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects; wherein a set of data is stored within the first memory of the memory module; wherein the memory module dynamically determines that at least a portion of the set of data will be transferred from the first memory to the second memory; and wherein, in response to the determination that at least a portion of the set of data will be transferred from the first memory to the second memory, the router is configured to identify the portion to be transferred and to facilitate execution of the transfer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures

19.

Memory fabric software implementation

      
Application Number 15371393
Grant Number 10241676
Status In Force
Filing Date 2016-12-07
First Publication Date 2017-07-13
Grant Date 2019-03-26
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

IPC Classes  ?

  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocation; Relocation

20.

MEMORY FABRIC SOFTWARE IMPLEMENTATION

      
Document Number 03006773
Status Pending
Filing Date 2016-12-07
Open to Public Date 2017-06-15
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

21.

MEMORY FABRIC OPERATIONS AND COHERENCY USING FAULT TOLERANT OBJECTS

      
Application Number US2016065330
Publication Number 2017/100288
Status In Force
Filing Date 2016-12-07
Publication Date 2017-06-15
Owner ULTRATA, LLC. (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can distribute and track the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes on a per-object basis. Distributing the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes can comprise storing, on a per-object basis, each memory object on two or more nodes of the plurality of hardware-based processing nodes of the object memory fabric.

IPC Classes  ?

  • G06F 15/167 - Interprocessor communication using a common memory, e.g. mailbox

22.

OBJECT MEMORY INTERFACES ACROSS SHARED LINKS

      
Application Number US2016065334
Publication Number 2017/100292
Status In Force
Filing Date 2016-12-07
Publication Date 2017-06-15
Owner ULTRATA, LLC. (USA)
Inventor
  • Frank, Stephen
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can utilize a memory fabric protocol between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes to distribute and track the memory objects across the object memory fabric. The memory fabric protocol can be utilized across a dedicated link or across a shared link between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes.

IPC Classes  ?

  • H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

23.

MEMORY FABRIC SOFTWARE IMPLEMENTATION

      
Application Number US2016065320
Publication Number 2017/100281
Status In Force
Filing Date 2016-12-07
Publication Date 2017-06-15
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

24.

Object memory interfaces across shared links

      
Application Number 15371448
Grant Number 10248337
Status In Force
Filing Date 2016-12-07
First Publication Date 2017-06-08
Grant Date 2019-04-02
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can utilize a memory fabric protocol between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes to distribute and track the memory objects across the object memory fabric. The memory fabric protocol can be utilized across a dedicated link or across a shared link between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 3/06 - Digital input from, or digital output to, record carriers

25.

Memory fabric operations and coherency using fault tolerant objects

      
Application Number 15371440
Grant Number 10235063
Status In Force
Filing Date 2016-12-07
First Publication Date 2017-06-08
Grant Date 2019-03-19
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can distribute and track the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes on a per-object basis. Distributing the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes can comprise storing, on a per-object basis, each memory object on two or more nodes of the plurality of hardware-based processing nodes of the object memory fabric.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 3/06 - Digital input from, or digital output to, record carriers

26.

INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH ROUTER

      
Document Number 02988957
Status In Force
Filing Date 2016-06-01
Open to Public Date 2016-12-15
Grant Date 2023-10-10
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

27.

Infinite memory fabric streams and APIs

      
Application Number 15168965
Grant Number 09971542
Status In Force
Filing Date 2016-05-31
First Publication Date 2016-12-15
Grant Date 2018-05-15
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to object memory fabric streams and application programming interfaces (APIs) that correspond to a method to implement a distributed object memory and to support hardware, software, and mixed implementations. The stream API may be defined from any point as two one-way streams in opposite directions. Advantageously, the stream API can be implemented with a variety topologies. The stream API may handle object coherency so that any device can then move or remotely execute arbitrary functions, since functions are within object meta-data, which is part of a coherent object address space.

IPC Classes  ?

  • G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/54 - Interprogram communication

28.

Infinite memory fabric hardware implementation with router

      
Application Number 15169585
Grant Number 09886210
Status In Force
Filing Date 2016-05-31
First Publication Date 2016-12-15
Grant Date 2018-02-06
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects; wherein a set of data is stored within the first memory of the memory module; wherein the memory module dynamically determines that at least a portion of the set of data will be transferred from the first memory to the second memory; and wherein, in response to the determination that at least a portion of the set of data will be transferred from the first memory to the second memory, the router is configured to identify the portion to be transferred and to facilitate execution of the transfer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

29.

INFINITE MEMORY FABRIC STREAMS AND APIS

      
Application Number US2016035203
Publication Number 2016/200649
Status In Force
Filing Date 2016-06-01
Publication Date 2016-12-15
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to object memory fabric streams and application programming interfaces (APIs) that correspond to a method to implement a distributed object memory and to support hardware, software, and mixed implementations. The stream API may be defined from any point as two one-way streams in opposite directions. Advantageously, the stream API can be implemented with a variety topologies. The stream API may handle object coherency so that any device can then move or remotely execute arbitrary functions, since functions are within object meta-data, which is part of a coherent object address space.

IPC Classes  ?

  • G06F 9/45 - Compilation or interpretation of high level programme languages
  • G06F 17/30 - Information retrieval; Database structures therefor
  • H04L 12/721 - Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
  • H04L 12/771 - Router architecture
  • H04L 12/851 - Traffic type related actions, e.g. QoS or priority
  • H04L 12/933 - Switch core, e.g. crossbar, shared memory or shared medium

30.

INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH MEMORY

      
Application Number US2016035264
Publication Number 2016/200655
Status In Force
Filing Date 2016-06-01
Publication Date 2016-12-15
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein the first memory has a lower latency than the second memory, and wherein each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions.

IPC Classes  ?

  • G06F 9/45 - Compilation or interpretation of high level programme languages
  • G06F 17/30 - Information retrieval; Database structures therefor
  • H04L 12/721 - Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
  • H04L 12/771 - Router architecture
  • H04L 12/851 - Traffic type related actions, e.g. QoS or priority
  • H04L 12/933 - Switch core, e.g. crossbar, shared memory or shared medium

31.

INFINITE MEMORY FABRIC STREAMS AND APIS

      
Document Number 02988963
Status Pending
Filing Date 2016-06-01
Open to Public Date 2016-12-15
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to object memory fabric streams and application programming interfaces (APIs) that correspond to a method to implement a distributed object memory and to support hardware, software, and mixed implementations. The stream API may be defined from any point as two one-way streams in opposite directions. Advantageously, the stream API can be implemented with a variety topologies. The stream API may handle object coherency so that any device can then move or remotely execute arbitrary functions, since functions are within object meta-data, which is part of a coherent object address space.

IPC Classes  ?

  • G06F 9/54 - Interprogram communication
  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

32.

Infinite memory fabric hardware implementation with memory

      
Application Number 15169580
Grant Number 10698628
Status In Force
Filing Date 2016-05-31
First Publication Date 2016-12-15
Grant Date 2020-06-30
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein the first memory has a lower latency than the second memory, and wherein each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions, wherein a set of data is stored within the first memory of the memory module; wherein the memory module is configured to receive an indication of a subset of the set of data that is eligible to be transferred between the first memory and the second memory; and wherein the memory module dynamically determines which of the subset of data will be transferred to the second memory based on access patterns associated with the object memory fabric.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

33.

INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH ROUTER

      
Application Number US2016035268
Publication Number 2016/200657
Status In Force
Filing Date 2016-06-01
Publication Date 2016-12-15
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

34.

OBJECT MEMORY DATA FLOW INSTRUCTION EXECUTION

      
Document Number 02974360
Status In Force
Filing Date 2016-01-20
Open to Public Date 2016-07-28
Grant Date 2023-10-03
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

35.

DISTRIBUTED INDEX FOR FAULT TOLERANT OBJECT MEMORY FABRIC

      
Document Number 02974394
Status In Force
Filing Date 2016-01-20
Open to Public Date 2016-07-28
Grant Date 2023-09-05
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocation; Relocation

36.

OBJECT MEMORY FABRIC PERFORMANCE ACCELERATION

      
Application Number US2016014018
Publication Number 2016/118561
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can provide transparent and dynamic performance acceleration, especially with big data or other memory intensive applications, by reducing or eliminating overhead typically associated with memory management, storage management, networking, and data directories. Rather, embodiments manage memory objects at the memory level which can significantly shorten the pathways between storage and memory and between memory and processing, thereby eliminating the associated overhead between each.

IPC Classes  ?

  • G06F 9/26 - Address formation of the next microinstruction

37.

UNIVERSAL SINGLE LEVEL OBJECT MEMORY ADDRESS SPACE

      
Application Number US2016014024
Publication Number 2016/118564
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can eliminate typical size constraints on memory space of commodity servers and other commodity hardware imposed by address sizes. Rather, physical addressing can be managed within the memory objects themselves and the objects can be in turn accessed and managed through the object name space.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

38.

IMPLEMENTATION OF AN OBJECT MEMORY CENTRIC CLOUD

      
Application Number US2016014074
Publication Number 2016/118591
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric including hardware-based processing nodes having memory modules storing and managing memory objects created natively within the memory modules and managed by the memory modules at a memory layer, where physical address of memory and storage is managed with the memory objects based on an object address space that is allocated on a per-object basis with an object addressing scheme. Each node may utilize the object addressing scheme to couple to additional nodes to operate as a set of nodes so that all memory objects of the set are accessible based on the object addressing scheme defining invariant object addresses for the memory objects that are invariant with respect to physical memory storage locations and storage location changes of the memory objects within the memory module and across all modules interfacing the object memory fabric.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

39.

MANAGING META-DATA IN AN OBJECT MEMORY FABRIC

      
Application Number US2016014130
Publication Number 2016/118627
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement a hardware-based multi-node processing system of an object memory fabric. Hardware-based processing nodes operatively coupled may each include object memory modules storing and managing memory objects, each memory object being created natively within the memory module and managed by the memory module at a memory layer, and each memory object including memory object data and memory object metadata. The memory object metadata may include triggers that specify additional operations to be executed by any object memory module of the hardware-based processing nodes when the respective memory object is located at the respective object memory module and accessed as part of the respective object memory module processing requests.

IPC Classes  ?

  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

40.

UTILIZATION OF A DISTRIBUTED INDEX TO PROVIDE OBJECT MEMORY FABRIC COHERENCY

      
Application Number US2016014135
Publication Number 2016/118630
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

IPC Classes  ?

  • G06F 17/30 - Information retrieval; Database structures therefor

41.

OBJECT BASED MEMORY FABRIC

      
Document Number 02974382
Status In Force
Filing Date 2016-01-20
Open to Public Date 2016-07-28
Grant Date 2023-09-26
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can implement an object-based memory which manages the objects within the memory at the memory layer rather than in the application layer. That is, the objects and associated properties can be implemented and managed natively in memory enabling the object memory system to provide increased functionality without any software and increasing performance by dynamically managing object characteristics including, but not limited to persistence, location and processing. Object properties can also propagate up to higher application levels.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 13/38 - Information transfer, e.g. on bus

42.

OBJECT BASED MEMORY FABRIC

      
Application Number US2016014013
Publication Number 2016/118559
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can implement an object-based memory which manages the objects within the memory at the memory layer rather than in the application layer. That is, the objects and associated properties can be implemented and managed natively in memory enabling the object memory system to provide increased functionality without any software and increasing performance by dynamically managing object characteristics including, but not limited to persistence, location and processing. Object properties can also propagate up to higher application levels.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

43.

TRANS-CLOUD OBJECT BASED MEMORY

      
Application Number US2016014021
Publication Number 2016/118563
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can eliminate the distinction between memory (temporary) and storage (persistent) by implementing and managing both within the objects. These embodiments can eliminate the distinction between local and remote memory by transparently managing the location of objects (or portions of objects) so all objects appear simultaneously local to all nodes. These embodiments can also eliminate the distinction between processing and memory through methods of the objects to place the processing within the memory itself.

IPC Classes  ?

  • G06F 9/26 - Address formation of the next microinstruction

44.

DISTRIBUTED INDEX FOR FAULT TOLERANT OBJECT MEMORY FABRIC

      
Application Number US2016014099
Publication Number 2016/118607
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

45.

OBJECT MEMORY DATA FLOW INSTRUCTION EXECUTION

      
Application Number US2016014113
Publication Number 2016/118615
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

IPC Classes  ?

  • G06F 9/26 - Address formation of the next microinstruction

46.

OBJECT MEMORY DATA FLOW TRIGGERS

      
Application Number US2016014119
Publication Number 2016/118620
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

IPC Classes  ?

  • G06F 9/26 - Address formation of the next microinstruction

47.

OBJECT MEMORY INSTRUCTION SET

      
Application Number US2016014124
Publication Number 2016/118624
Status In Force
Filing Date 2016-01-20
Publication Date 2016-07-28
Owner ULTRATA LLC (USA)
Inventor
  • Frank, Steven
  • Reback, Larry

Abstract

Embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to define arbitrary, parallel functionality such as: direct object address manipulation and generation without the overhead of complex address translation and software layers to manage differing address space; direct object authentication with no runtime overhead that can be set based on secure 3rd party authentication software; object related memory computing in which, as objects move between nodes, the computing can move with them; and parallelism that is dynamically and transparent based on scale and activity. These instructions are divided into three conceptual classes: memory reference including load, store, and special memory fabric instructions; control flow including fork, join, and branches; and execute including arithmetic and comparison instructions.

IPC Classes  ?

  • G06F 9/26 - Address formation of the next microinstruction

48.

Distributed index for fault tolerant object memory fabric

      
Application Number 15001451
Grant Number 09971506
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2018-05-15
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0877 - Cache access modes

49.

Managing meta-data in an object memory fabric

      
Application Number 15001524
Grant Number 11755202
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2023-09-12
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement a hardware-based multi-node processing system of an object memory fabric. Hardware-based processing nodes operatively coupled may each include object memory modules storing and managing memory objects, each memory object being created natively within the memory module and managed by the memory module at a memory layer, and each memory object including memory object data and memory object metadata. The memory object metadata may include triggers that specify additional operations to be executed by any object memory module of the hardware-based processing nodes when the respective memory object is located at the respective object memory module and accessed as part of the respective object memory module processing requests.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

50.

Object memory data flow triggers

      
Application Number 15001490
Grant Number 11579774
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2023-02-14
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

51.

Implementation of an object memory centric cloud

      
Application Number 15001494
Grant Number 11755201
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2023-09-12
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric including hardware-based processing nodes having memory modules storing and managing memory objects created natively within the memory modules and managed by the memory modules at a memory layer, where physical address of memory and storage is managed with the memory objects based on an object address space that is allocated on a per-object basis with an object addressing scheme. Each node may utilize the object addressing scheme to couple to additional nodes to operate as a set of nodes so that all memory objects of the set are accessible based on the object addressing scheme, which defines invariant object addresses for the memory objects that are invariant with respect to physical memory storage locations and storage location changes of the memory objects within the memory module and across all modules interfacing the object memory fabric.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0877 - Cache access modes

52.

Object memory instruction set

      
Application Number 15001526
Grant Number 11782601
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2023-10-10
Owner Ultrata, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to define arbitrary, parallel functionality such as: direct object address manipulation and generation without the overhead of complex address translation and software layers to manage differing address space; direct object authentication with no runtime overhead that can be set based on secure 3rd party authentication software; object related memory computing in which, as objects move between nodes, the computing can move with them; and parallelism that is dynamically and transparent based on scale and activity. These instructions are divided into three conceptual classes: memory reference including load, store, and special memory fabric instructions; control flow including fork, join, and branches; and execute including arithmetic and comparison instructions.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
  • G06F 12/0837 - Cache consistency protocols with software control, e.g. non-cacheable data
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

53.

Utilization of a distributed index to provide object memory fabric coherency

      
Application Number 15001652
Grant Number 09965185
Status In Force
Filing Date 2016-01-20
First Publication Date 2016-07-21
Grant Date 2018-05-08
Owner ULTRATA, LLC (USA)
Inventor
  • Frank, Steven J.
  • Reback, Larry

Abstract

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0877 - Cache access modes