A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
G06F 13/362 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
3.
SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR SERVER SOC
Example implementations described herein are directed to systems and methods for a server hub device that is configured to execute artificial intelligence/neural network models through processing input data and generating metadata or instructions to edge devices. In example implementations, the AI/NN operations are conducted through executing logical shifts (e.g., by shifter circuits) on log-quantized parameters corresponding to such operations.
H04N 21/431 - Generation of visual interfacesContent or additional data rendering
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
4.
SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR EDGE AND SERVER SOC
Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.
H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
H04N 21/232 - Content retrieval operation within server, e.g. reading video streams from disk arrays
H04N 21/435 - Processing of additional data, e.g. decrypting of additional data or reconstructing software from modules extracted from the transport stream
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies
Systems and methods for automatically gating a data strobe during a read operation by the DRAM are disclosed. The method includes detecting, and automatically opening the gate when the DQS signal is driven. A system for automatically gating a Data Strobe (DQS) is disclosed which, on detection at an Input-Output (IO) receiver of a host chip, gates, at the host chip, the DQS signal based on the detection such that the gate is opened when the DQS signal is driven. A host chip and an input output receiver of the host chip are also disclosed.
Systems and methods described herein involve executing, using an artificial intelligence System on Chip (AI SoC), a machine learning model on received televised content, the machine learning model configured to identify objects displayed on the received televised content; displaying, through a mobile application interface, the identified objects for selection; and for a selection of one or more objects from the identified objects and an overlay through the mobile application interface, modifying a display of the received televised content to display the overlay.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
Aspects of the present disclosure involve systems, methods, computer instructions, and artificial intelligence processing elements (AIPEs) involving a shifter circuit or equivalent circuitry/hardware/computer instructions thereof configured to intake shiftable input derived from input data for a neural network operation; intake a shift instruction derived from a corresponding log quantized parameter of a neural network or a constant value; and shift the shiftable input in a left direction or a right direction according to the shift instruction to form shifted output representative of a multiplication of the input data with the corresponding log quantized parameter of the neural network.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
Example implementations described herein are directed to systems and methods for a server hub device that is configured to execute artificial intelligence/neural network models through processing input data and generating metadata or instructions to edge devices. In example implementations, the AI/NN operations are conducted through executing logical shifts (e.g., by shifter circuits) on log-quantized parameters corresponding to such operations.
Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
patents
