Various embodiments described herein support or provide for electrical disturbance testing, including establishing a communication session between an onboard unit and a roadside unit; generating a radio frequency signal to interfere with the communication session; detecting an interrupt of the communication session at a frequency point associated with the RF signal; determining that the interrupt is caused by a failure of uplink data transmission in the communication session; and adjusting a position of the roadside unit or adjusting a filter communicatively coupled between the roadside unit and the associated antenna to cause the communication session to be reestablished at the frequency point associated with the radio frequency signal.
An audio device calibration system includes an acoustic sensor, one or more processors, and a memory storing instructions that, when executed by the one or more processors, configure the processors to obtain a response curve of a device under test, identify an error curve, and calibrate the audio device based on a compensation curve that corresponds to the error curve to perform automatic quality control and calibration for audio devices.
Methods, systems, and computer programs are presented for parking management and navigation. One method includes operations for determining an availability of a parking space having a parking space ID, obtaining a radio-frequency ID associated with a vehicle occupying the parking space, and communicating the parking space ID and the radio-frequency ID to a storage device via a self-organized network formed by multiple parking space terminals. Further, the method includes operations for providing navigation to a vacant parking space and providing navigation to a parked vehicle.
A method for resisting fault injection attacks during secure boot is provided. The method may include: performing a secure check on a System-on-Chip (SoC), wherein one or more pre-determined values are written on one or more bits of a first register of the SoC during the secure check; reading one or more corresponding bits of a second register of the SoC; and comparing the values of the one or more bits of the second register with the values of the one or more corresponding bits of the first register. In response to a comparison result that the values of the one or more bits of the second register are the same as the values of the one or more corresponding bits of the first register, the SoC is booted.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A method of patching a secure boot of an internet of things (IoT) device is provided. The method may include: loading a patch on a flash memory of a system-on-chip (SoC); generating a patch key corresponding to the loaded patch using a cryptographic algorithm; reading a pre-determined authentication key from a one-time programmable (OTP) memory of the SoC; comparing the patch key with the authentication key. In response to a comparison result that the patch key is the same as the authentication key, the method may include authenticating the patch; executing the authenticated patch on the SoC; and booting the SoC with the authenticated patch executed on the SoC.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
An Active Noise Cancellation (ANC) headphone of multiple modes may include a preliminary scene-change detection circuit using ultra-low power to detect a scene change near the headphone and to send a trigger signal upon detecting the scene change, a scene identification circuit to determine a current scene upon receiving a trigger signal, and a filter switch circuit to switch the headphone mode from a previous headphone mode to a current headphone mode according to the determined current scene. In this way, the ANC headphone can automatically obtain an improved balance of comfortability, safety, and communicability under a reduced power consumption.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effects; Masking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
A new trans-impedance amplifier (TIA) with low noise is provided. The TIA may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, and a pair of capacitors electrically connected in series, which are electrically connected in parallel. The structure can lead to a reduced noise level of the TIA.
A headphone, having a sleep mode and a full-power operation mode, includes a sensor set to detect a state of a wearer in a sleep state or an awake state, Active Noise Cancellation (ANC) earphones, and a controller coupled to the sensor set and the earphones, which can control the headphone to switch between the sleep and the full-power operation modes based on the detected state of the wearer. Once the controller determines the wearer falling into the sleep state, the controller will switch the headphone from the full-power operation mode to the sleep mode, turn off the earphones, and increase the wearer state detection interval used while the headphone being in the sleep mode. This may reduce power consumption of the headphone and help improve the sleep quality of the wearer.
A Bluetooth receiver includes a memory; and one or more processors in communication with the memory, the one or more processors configured to perform operations including: dividing Bluetooth frequencies of the Bluetooth receiver into Bluetooth frequency classes based on a frequency relationship among Bluetooth channels of the Bluetooth receiver and non-overlapping Wi-Fi channels of an interfering Wi-Fi device operating in a Wi-Fi frequency range within the Bluetooth frequency range, each Bluetooth frequency class including one or more Bluetooth frequency groups; determining one or more working Bluetooth frequency groups of the Bluetooth frequency classes based on pre-determined requirements, and saving entire working Bluetooth frequencies within the one or more working Bluetooth frequency groups into a channel map table, which can be used for Adaptive Frequency Hopping (AFH) to reduce Wi-Fi interferences caused by the Wi-Fi device. The Bluetooth receiver may efficiently and quickly choose working Bluetooth frequency points.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A trans-impedance amplifier (TIA) may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, a pair of capacitors electrically connected in series, a differential output node, a third PMOS transistor, and a fourth pair of NMOS transistors cross-coupled between the pair of output circuits of the output driving stage. The structure can lead to a reduced noise level and a reduced peak transient current level of the TIA.
A Bluetooth receiver includes a primary circuit path, which can create a first digital IF modulated signal to obtain a Bluetooth load signal at a current Bluetooth frequency point, and an auxiliary circuit path, in parallel with the primary circuit path, which can create a second digital IF modulated signal in a Bluetooth frequency range across multiple Bluetooth frequency points. A signal analysis module of the auxiliary circuit path may evaluate interference levels of the second digital IF modulated signal at the Bluetooth frequency points, by analyzing a Fourier Transformation (FT) spectrum of the second digital IF modulated signal, and to choose a number of working Bluetooth frequency points corresponding to relative low signal strengths in the FT spectrum. This way may efficiently and quickly choose qualified working Bluetooth frequency points for Adaptive Frequency Hopping (AFH) in a single current time slot, without consuming any additional time slots for detection.
H04B 1/7143 - Arrangements for generation of hop patterns
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
A WiFi data transmission system is provided. The transmission system is in a mesh-tree topology and includes a router and nodes connected to the router via a root node. A node of the nodes includes a station (STA) interface, a soft access point (AP) interface, a bridge interface, and a forwarding database (FDB), for example. Upon receiving a data frame by the node, the bridge interface of the node may search the FDB using information of the data frame for a latest data record to determine an outgoing interface address of the outgoing node so as to guide an outgoing path for the data frame. The structure of transmission system can lead to an improved adaptability and communications efficiency, and a reduced resource consumption.
A method includes responsive to a device sensing a phone being adjacent to the device, triggering the device and the phone in a preliminary communication mode; periodically broadcasting by the device in the preliminary communication mode a broadcast message (P2) with a unique identification; detecting a strength of the broadcast message (P2) by the phone; responsive to detecting the strength of the broadcast message (P2) greater than a first threshold (T1), establishing a restricted wireless connection between the phone and the device; transmitting packages between the device and the phone via the restricted wireless connection; detecting strengths of the packages; and responsive to detecting strengths of the packages respectively greater than the first threshold (T1) and a second threshold (T2), establishing a complete wireless communication between the device and the phone so as to connect the device to the network via the phone.
H04W 4/00 - Services specially adapted for wireless communication networks; Facilities therefor
H04W 48/10 - Access restriction or access information delivery, e.g. discovery data delivery using broadcasted information
H04W 48/04 - Access restriction performed under specific conditions based on user or terminal location or mobility data, e.g. moving direction or speed
H04W 12/47 - Security arrangements using identity modules using near field communication [NFC] or radio frequency identification [RFID] modules
A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.
A Weil code generator and a method of generating Weil codes with a Weil code length (N) are provided. The Weil code generator includes a plurality of parallel channels (10), a multi-channel read arbiter (20), and two parallel Legendre ROMs (30), which are connected in series. A channel of the plurality of channels stores a current Weil code to demodulate signals from a satellite. The multi-channel read arbiter (20) may determine a win channel from the plurality of channels. The two Legendre ROMs (30) respectively store a first and a second Legendre sequences (LS1, LS2) each having a Legendre sequence length (2N) being double the Weil code length (N). The Weil code generator may generate Weil codes efficiently.
G01S 19/30 - Acquisition or tracking of signals transmitted by the system code related
G01S 19/37 - Hardware or software details of the signal processing chain
G01S 19/29 - Acquisition or tracking of signals transmitted by the system carrier related
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
An ADC circuit is provided. The ADC circuit may include an array of bit capacitors; a comparator electrically connected to the bit capacitors; a NOR gate electrically connected to the comparator; an AND gate to create an asynchronous clock (ACLK) based on a digital output from the NOR and a synchronous clock (CLKin); a delay control circuit to receive the asynchronous clock and to create a delayed asynchronous clock (ACLKd); and a SAR control circuit to receive a digital output from an output end of the comparator, to receive the delayed asynchronous clock, to transmit a bit control signal (B<9:1>) to the bit capacitors, and to transmit a delay control word (DL<7:1>) to the delay control circuit. The ADC circuit can create an asynchronous comparator clock (CKcmp) with a maximum delay value (Td_max), thus leading to an improved conversion linearity and a reduced power consumption.
H03M 1/80 - Simultaneous conversion using weighted impedances
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
17.
Power amplifier and overcurrent protection circuit
A power amplifier includes a digital-to-analog converter, a loop filter, a driver circuit, a first adjustable reference resistor and a second adjustable reference resistor. A circuit includes an overcurrent protection circuit and a power amplifier, wherein the overcurrent protection circuit is communicatively coupled to the power amplifier. The digital-to-analog converter is configured to receive a digital signal and to output an analog signal, the driver circuit communicatively coupled to the loop filter and at least one of a first output port and a second output port of the power amplifier.
A radio-frequency (RF) power rectifier circuit is provided. The RF power rectifier circuit includes a pair of differential voltage input nodes, a pair of input transistors respectively connected to the pair of differential voltage input nodes, a current mirror including a first, a second, and a third transistors, a pair of cascode transistors electrically connected between the pair of input transistors and the first transistor, a control resistor and a control transistor, and an output node. The control resistor is electrically connected to a source of the control transistor and the ground to provide a DC bias to the control transistor, and the control transistor is electrically connected to the second transistor to provide a dynamic bias to the pair of cascode transistors. This structure can lead to an increased input voltage range and reduced power consumption.
H02M 7/25 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage
H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.
A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
H03M 1/76 - Simultaneous conversion using switching tree
A wireless speaker system includes a first transceiver and a second transceiver. The first transceiver is configured to establish a first wireless link with a data source for receiving a plurality of data packets, and to establish a second wireless link with a second transceiver for transmitting a set of parameters to the second transceiver to enable the second transceiver to sniff the plurality of data packets from the data source. The first transceiver is further configured to send a second acknowledgment to the data source via the first wireless link upon failure to receive the plurality of data packets from the data source via the first wireless link and upon receiving a first acknowledgment from the second wireless transceiver via the second wireless link.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks
22.
Power amplifier and method of operating the power amplifier
A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.
H03F 3/217 - Class D power amplifiers; Switching amplifiers
H03F 3/42 - Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
23.
System and method of recovering pairing information of wireless devices
A system for recovering pairing information of wireless devices is provided. The system may include a first device (such as a mouse) and a second device (such as a dongle) that are wirelessly paired. The system can determine a pairing information damage in one of the first device and the second device, and can automatically recover the pairing information without even noticed by the user. In this way, the system can be less affected by the pairing information damage, and can have extended product life and improved customer experience.
A new demodulator with consistent sensibility to signals received from different directions, low power consumption, and low manufacturing cost is provided. The demodulator may include a first demodulator branch and a second demodulator branch electrically connected in parallel, and a DC circuit to provide DC power to the demodulator. The DC circuit has a first diode and a second diode electrically connected in series between a DC power supply Vcc and the ground. The second demodulator branch can share a low pass filter and a DC blocking capacitor of the first demodulator branch for example, and can multiplex or reuse a bias current from the first demodulator branch.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
H04L 5/00 - Arrangements affording multiple use of the transmission path
An RF front-end circuit in a receiver, comprising a low noise amplifier (LNA) configured to receive an RF signal from an antenna; a frequency synthesizer and divider (FS_DIV), configured to generate a first local oscillation (LO) signal, a second LO signal, a third LO signal and a fourth LO signal; a first front-end circuit communicatively coupled to the LNA and the FS_DIV, and configured to output a first digital intermediate-frequency signal by processing the amplified RF signal and the first LO signal and a second digital intermediate-frequency signal by processing the amplified RF signal, the first and second LO signals; a second front-end circuit communicatively coupled to the LNA and the FS_DIV, and configured to output a third digital intermediate-frequency signal by processing the amplified RF signal and the third LO signal and a fourth digital intermediate-frequency signal by processing the amplified RF signal, the third and fourth LO signals.
A new demodulator with consistent sensibility to signals received from different directions and low power consumption is provided. The demodulator may include a first demodulator branch and a second demodulator branch electrically connected in parallel, and a DC circuit to provide DC power to the demodulator. The DC circuit has a first diode and a second diode electrically connected in series between a DC power supply Vcc and the ground. The second demodulator branch can multiplex or reuse a bias current from the first demodulator branch.
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
A circuit for error correction comprises a first RS syndrome generator to generate a first RS syndrome for a RS(n, k) code according to a received symbol stream to be decoded, wherein k and n are respective the number of data symbols and the total number of code symbols in the received symbol stream to be decoded; a first decision unit communicatively coupled to the first RS syndrome generator and configured to determine whether there are at least N symbols in the first RS syndrome that equal 0, wherein N is related to a code distance of the RS(n, k) code; and a first adder communicatively coupled to the first decision unit and configured to output a corrected decoded codeword by adding the first RS syndrome to the received symbol stream to be decoded if there are at least N symbols in the first RS syndrome that equal 0.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
28.
Receiver and method for calibrating frequency offset
A receiver comprises an I/Q demodulator generates an angular signal by demodulating an in-phase branch and a quadrature branch of a received signal; a filter communicatively coupled to the I/Q demodulator and configured to generate a filtered angular signal by filtering out a noise signal having a frequency higher than a predetermined frequency value from the angular signal; an angle subtractor communicatively coupled to the filter and configured to generate a phase signal based on the filtered angular signal; a phase calibrator communicatively coupled to the angle subtractor and configured to generate a calibrated phase signal based on at least one received preamble signal corresponding to the phase signal and a known value of the at least one received preamble signal corresponding to the phase signal; and a symbol decider communicatively coupled to the phase calibrator and configured to generate an output symbol based on the calibrated phase signal.
A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.
H03H 19/00 - Networks using time-varying elements, e.g. N-path filters
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A CMOS IR transceiver includes an IR transmitter circuit, an IR receiver circuit, and an IR diode configured to either emit or receive an IR signal. CMOS elements, such as a PMOS current mirror, a PMOS switch, a NMOS switch, a NMOS current mirror, and a receiver enabling PMOSFET switch are used in the CMOS IR transceiver. The CMOS IR transceiver may have advantages of increased integration, occupying less space, and lower cost.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
A method for establishing a BLE mesh network, comprising: receiving, by a first node, from a second node, a first network packet; determining, by the first node, whether the received first network packet has been received before, (a) determining whether the first node is a destination node if the received first network packet is different from the network packet stored in the buffer, performing an action defined by the first network packet if the first node is the destination node, and broadcasting the received first network packet through an advertising channel in the BLE mesh network if the first node is not the destination node; (b) dropping the received first network packet if the received first network packet is the same as at least one network packet stored in the buffer.
H04L 12/741 - Header address processing for routing, e.g. table lookup
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A method in an on-board unit comprising: receiving and decoding, with a transceiver, a broadcast packet (BCP) from a road side unit (RSU); processing BCP with a micro controller unit (MCU), wherein processing comprises determining whether there is a first interrupt from the transceiver, wherein the first interrupt is used to interrupt idle state of MCU; searching for low level state from a falling edge after the first interrupt; determining whether duration time of low level is within a time range; inputting one byte into the transceiver if duration time is within the range and clearing the first interrupt; determining whether there is a second interrupt from the transceiver, wherein the second interrupt is used to interrupt data reception; processing data in BCP if there is second interrupt; and converting, with the transceiver, processed data to a wireless signal and transmitting the signal to RSU.
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
G07B 15/06 - Arrangements for road pricing or congestion charging of vehicles or vehicle users, e.g. automatic toll systems
33.
Radio frequency transceiver circuit with distributed inductor and method thereof
A radio-frequency transceiver circuit, comprising: a first port and a second port, configured to receive, together, a pair of differential signals; a radio-frequency matching circuit communicatively coupled to the first port and the second port, and configured to process the pair of differential signals to obtain a radio-frequency signal and configured to increase transmission power for the radio-frequency signal, wherein the radio-frequency matching circuit includes at least one capacitor, at least one distributed inductor; a band pass filter circuit, communicatively coupled to the radio-frequency matching circuit and configured to filter the radio-frequency signal, wherein the band pass filter circuit includes at least one capacitor and at least one distributed inductor; and a third port, communicatively coupled to the band pass filter circuit and configured to output the filtered radio-frequency signal, wherein both of the at least one distributed inductors have a length of microstrip line.
A switch for controlling a gain of an amplifier comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a first resistor, and an inverter. A source of the first NMOS transistor is connected to a first terminal of the first resistor, a drain of the first NMOS transistor is connected to a drain of the third PMOS transistor, a source of the fourth NMOS transistor and a source of the second NMOS transistor, a gate of the first NMOS transistor is connected to a source of the third PMOS transistor, a drain of the fifth PMOS transistor, a drain of the fourth NMOS transistor, and a gate of the second NMOS transistor; a gate of the third PMOS transistor receives a switch voltage (Vs); a gate of the fourth PMOS transistor receives a negative switch voltage (Vsn).
An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.
A method and a circuit for exciting a crystal oscillation circuit are disclosed herein. The crystal oscillation circuit comprising: charging, with a charging circuit, a voltage-controlled oscillator; providing, with the voltage-controlled oscillator, an exciting signal; blocking, with a direct current blocking capacitor, direct current from the voltage-controlled oscillator to the crystal oscillation circuit; and exciting, with the exciting signal, the crystal oscillation circuit. The circuit for exciting a crystal oscillation circuit, comprising: a charging circuit; a voltage-controlled oscillator coupled to the charging circuit and configured to provide an exciting signal to the crystal oscillation circuit; and a direct current blocking capacitor connected between the voltage-controlled oscillator and the crystal oscillation circuit and configured to block direct current from the voltage-controlled oscillator.
H03B 5/30 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
A card detector configured to be communicatively coupled to a card reader comprises: a first comparator configured to output periodically a first comparison result by comparing a voltage for a device under test with a first reference; a second comparator outputs periodically a second comparison result by comparing a second reference voltage with the first reference voltage, wherein the second reference voltage is adjustable; a decision circuit communicatively coupled to both the first comparator and the second comparator, and decides whether a card is in proximity to the card detector by comparing the time delay relationship between the first comparison result and the second comparison result respectively at a first time point and a second time point different from the first time point, and further wakes up the card reader if the decision circuit decides that the card is in proximity to the card detector.
G06K 7/08 - Methods or arrangements for sensing record carriers by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
G06K 7/00 - Methods or arrangements for sensing record carriers
38.
Fractional-N frequency synthesizer and method thereof
A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
H03B 21/02 - Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies by plural beating, i.e. for frequency synthesis
H03K 23/68 - Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
H03L 7/085 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/087 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03M 7/32 - Conversion to or from delta modulation, i.e. one-bit differential modulation
39.
Receiver for determining sample phase and method of determining sample phase
A receiver for determining sample phase comprises a sync detector to output a sample phase; an interpolator communicatively coupled to the sync detector and to generate a plurality of interpolated phases, wherein each of the interpolated phase and phases within the phase set corresponds to a respective syncword; a calculator communicatively coupled to the interpolator to calculate an error vector magnitude (EVM) of syncword corresponding respectively to each of the interpolated phase and to each of the phase within a phase set, and determine the minimum EVM among EVMs for the syncword corresponding to each of the interpolated phase and the EVM of syncword corresponding to each of the phase within the phase set; and an output unit communicatively coupled to the calculator and configured to sample and output payload signals at the phase corresponding to the minimum EVM.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
40.
Radio frequency voltage-to-current converting circuit and method
A voltage-to-current converting circuit, comprising: a direct current (DC) bias circuit, a first DC-blocking circuit, a second DC-blocking circuit, a first differential input pair and a second differential input pair; wherein the DC bias circuit is connected to the first and second DC-blocking circuits and configured to provide a bias voltage to the first and the second differential input pairs; wherein the first DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair and the second DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair; and wherein the first differential circuit is connected to the second differential circuit via two resistors.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
41.
Wireless microphone receiver and method in the wireless microphone receiver
A wireless microphone receiver comprises a phase locker to lock a phase of an audio data successfully received from a microphone transmitter; a calculator to calculate a frequency offset between the locked phase of the microphone receiver and the phase of the microphone transmitter; a calibrator to calibrate the frequency offset using a first step if the absolute value of the frequency offset is larger than a first predetermined threshold, and to calibrate the frequency offset with a second step if the absolute value of the frequency offset is smaller than or equal to the first predetermined threshold, and complete the calibration if a calibrated frequency offset is smaller than a second threshold; a buffer to buffer the audio data received from the microphone transmitter, and the calibrator further adjusts the amount of data stored in the buffer; and the microphone receiver further outputs buffered audio data.
A switching unit comprises a COordinate Rotation DIgital Computer (CORDIC) unit configured to estimate a maximum phase difference between a phase of the GFSK modulated signal to be switched and a phase of the QPSK modulated signal after switch; a timing unit communicatively coupled to the CORDIC unit and configured to generate adaptive steps according to a switch time and the estimated maximum phase difference, wherein the CORDIC is further configured to generated an adjusted GFSK modulated signal by adjusting a phase of the GFSK modulated signal to be switched according to the estimated maximum phase difference and the adaptive steps.
A circuit to compensate for a lost audio frame, comprising: an identifier configured to identify a reference audio segment with a first length followed by the lost audio frame with a second length; a searcher coupled to the identifier and configured to search for a first audio segment similar to the reference audio segment in a cached audio segment followed by the reference audio segment by utilizing a cross-correlation search; the identifier further configured to identify a second audio segment subsequent to the first audio segment as a pre-compensated audio frame; an adjustor coupled to the identifier and configured to adjust an amplitude of the second audio segment based on a scale factor; and an output coupled to the adjustor to output the adjusted second audio segment as a compensated audio frame.
G10L 19/005 - Correction of errors induced by the transmission channel, if related to the coding algorithm
G10L 25/06 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being correlation coefficients
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A first speaker, comprising: a receiver configured to receive, from a second speaker, a second runtime and a second number of audio samples when the first speaker plays an audio file synchronized with the second speaker; a calculator configured to calculate a time interval value based on the second runtime; a generator configured to generate a revised second number of audio samples based on the time interval value; a comparator configured to compare a difference between the revised second number of audio samples and a first number of audio samples of the first speaker so as to determine the amount of latency of the first speaker; an adjustor configured to adjust a playing speed of the first speaker; and an output configured to output the audio file according to the adjusted playing speed.
A power management system comprises an input power detector configured to generate a first enablement signal by detecting whether a first voltage is supplied; a first output stage connected to the input power detector and configured to receive and regulate the first voltage upon receiving the first enablement signal; an error operational amplifier is connected to the first output stage, a first input port of the error operational amplifier is configured to receive a first reference voltage, a second input port of the error operational amplifier is connected to a connection point of a first resistor and a second resistor, the first resistor is connected to the first output stage, the second resistor is connected to ground, and a system output port is located at the connection of the output port of the first output stage and the first resistor, to drive a load.
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
46.
Wireless transmitter, wireless remote receiver and methods thereof
A wireless transmitter, comprises a frame generator configured to generate a frame by including an auxiliary preamble, an auxiliary syncword, a guard, a preamble, an address, a packet control, a payload and a CRC; a modulator communicatively coupled to the frame generator and configured to modulate the frame according to a variable transmission rate and include the transmission rate in the auxiliary syncword; and a RF front end communicatively coupled to the modulator and configured to transmit the modulated signal to a receiver.
Embodiments discloses a transmitter for transmitting a Bluetooth packet in an enhanced data rate format. The Bluetooth packet includes a GFSK modulated segment, a Guard segment and a DPSK modulated segment. The transmitter comprises a first multiplexer configured to select a phase signal from a Guard phase signal, a received GFSK phase signal and a received DPSK phase signal based on time; a second multiplexer configured to select a amplitude signal from a Guard amplitude signal, a received GFSK amplitude signal and a received DPSK amplitude signal based on time, a phase to frequency converter communicatively coupled to the first multiplexer and configured to convert the selected phase signal into converted frequency signal. The transmitter further comprises a phase lock loop, a digital to analog converter and a power amplifier.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A method for suppressing POP noise in an audio operation amplifier, comprising: connecting a first resistor and a second resistor in series at an output stage of the audio operation amplifier by turning on a first switch and a second switch; generating, with a ramp generator, a ramp voltage after an audio signal is input into the audio operation amplifier, wherein the ramp voltage varies from zero to a first value; generating, with an voltage generator, a second voltage, wherein a third switch is turned on and a fourth switch is turned off when the ramp voltage reaches the second value; short-circuiting the first and second resistors by turning off the first and second switches; and outputting, with the audio operation amplifier, an amplified audio signal.
A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
H03C 3/09 - Modifications of modulator for regulating the mean frequency
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
H03K 21/00 - PULSE TECHNIQUE - Details of pulse counters or frequency dividers
G11B 7/09 - Disposition or mounting of heads or light sources relatively to record carriers with provision for moving the light beam or focus plane for the purpose of maintaining alignment of the light beam relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track f
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
50.
Low-noise amplifier, receiver and method in a low-noise amplifier
A low-noise amplifier comprises first and second input ports respectively configured to receive a positive and negative input voltages; first and second resonance circuit, first and second transistor; wherein a first voltage output port of the first resonance circuit is connected to the second transistor, and a second voltage output port of the second resonance circuit is connected to the first transistor, the first and second voltage output ports are crossed coupled to a second node of both the first transistor and the second transistor via a first and second capacitor respectively; the second node of the second transistor is connected to both the second input port via a third capacitor and a third node of the first transistor, and the second node of the first transistor is connected to both the first input port via a fourth capacitor and a third node of the second transistor.
An electronic toll collection receiver, comprising: an enveloping module configured to envelope an amplitude modulation (AM) signal; an averaging module connected to the enveloping module, configured to obtain an average value of the enveloped AM signal; a direct current blocking module connected to the enveloping module and the averaging module, configured to eliminate the average value from the enveloped AM signal; a comparing module connected to the direct current blocking module, configured to compare the average value and each of amplitude values of the enveloped AM signal; a correcting module connected to the comparing module and the directing current blocking module, configured to correct output values from the comparing module; and a decoder module connected to the correcting module, configured to decode the corrected output values from the correcting module.
A method of error decision, comprising: for each of a plurality of demodulated decision information in a codeword, identifying by a controller, a decoded bit for the demodulated decision as an erasable error bit if the demodulated decision information is larger than a first threshold and smaller than a second threshold; for all the identified erasable error bits, enumerating by a calculator, all possible combinations of the identified erasable error bits; for each combination of all enumerated possible combinations feeding by the calculator, each combination with all other decided decoded bits of the code word into a header correction checker; performing, by the header correction checker, header correction checking for each combination; and outputting, by a decision circuit connected to the header correction checker, a combination with a correct header correction check (HEC) result as an output sequence.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04W 4/00 - Services specially adapted for wireless communication networks; Facilities therefor
53.
Method and device for improving acoustics of an AM demodulation output signal
A method for improving acoustics of amplitude modulation (AM) audio signal, comprising: amplifying and mixing, with an amplitude modulation (AM) front-end module, an analog AM signal and an automatic gain control (AGC) signal from an AGC module; converting and sampling, with an analog-digital converter and down-sampling module, the amplified and mixed signal to generate a digital AM signal; digitally mixing, with a digital mixer module, the digital AM signal to generate a first digital AM envelope signal; compensating, with an AM compensator module, the first digital AM envelope signal by an AM compensating AGC signal from the AM compensator module to generate a second digital AM envelope signal; demodulating, with a demodulation module, the second digital AM envelope signal; and outputting, with an output module, a demodulated AM audio signal.
H04H 20/49 - Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups specially adapted for stereophonic broadcast systems for AM stereophonic broadcast systems
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
The invention discloses an antenna comprising a plurality of laminated layers of radiating elements, wherein each layer of radiating elements is arranged in a zigzag pattern; a feed point connected to one of the plurality laminated layers of the radiating elements and is configured to receive a radio frequency signal; and a plated via configured to couple the plurality of laminated layers of radiating elements; wherein the radiating elements are configured to radiate the radio frequency signal.
A wireless communication method without pairing IDs in advance, comprises: transmitting, at a first power, a first ID within a first pipe; searching for a second ID on at least one frequency point, wherein the second ID matches the first ID; if the second ID is not found within the first pipe, respectively transmitting, at least at a second power and a third power, at least two matching-code requests within a public pipe on public frequency points; receiving ACKs responding to each of the matching-code requests from different devices; summing numbers of the received ACKs from each device; comparing the summed numbers of the received ACKs from the different devices to get a maximum number; switching from a public pipe to a third pipe of a device that sent the maximum number of ACKs; transmitting a matching-code package to the device that sent the maximum number of ACKs.
H04W 4/00 - Services specially adapted for wireless communication networks; Facilities therefor
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
A transmitter comprises an analog-to-digital converter, an audio signal compressor, a framer, a scrambler, a modulator, and a transmitting unit. The analog-to-digital converter translates an analog audio signal into a digital Pulse-Code Modulation (PCM) format audio signal. The audio signal compressor compresses the PCM format audio signal into a coded bit stream with a modified Adaptive differential Pulse-code Modulation (ADPCM) algorithm. The framer packetizes the coded bit stream into a 1.125 ms frame data by adding a preamble, a signaling field, a data field, and a cyclic redundancy check field to the coded bit stream. The scrambler scrambles the frame data with an ID number. The modulator generates a modulated signal by modulating the scrambled frame data with a predetermined modulation scheme. The transmitting unit transmits the modulated signal.
A circuit comprises a decision unit configured to obtain a plurality of decision errors based on a demodulated signal and an original symbol; a calculator configured to calculate an instant direct current error based on the plurality of the decision errors, and first and second variance error signals based on the instant direct current error; an error detector configured to obtain a first result by determining whether an absolute value of both the first variance error signal and an the second variance error signal are larger than a first threshold; obtain a second result by determining whether an absolute value of a first decision error of the plurality of the decision error is larger than a second threshold; and output a second closest constellation point as a corrected symbol corresponding to the first decision error at least based on the first result and the second result.
A method of compensating phase imbalance comprises, detecting power outputs of a first output signal related to a first phase compensation value and of a second output signal related to a second phase compensation value; calculating a first absolute difference between an in-phase value and a quadrature value of the power output of the first output signal; calculating a second absolute difference between an in-phase value and a quadrature value of the power output of the second output signal; determining a minimum difference by comparing the first absolute difference with the second absolute difference; determining an optimal phase compensation value and a suboptimal phase compensation value from the first and the second phase compensation values according to the minimum difference; and obtaining an updated optimal phase compensation value with a binary search algorithm.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/027 - Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
59.
Operational amplifier and method of operating the operational amplifier
An operational amplifier comprises a first input pair, a second input pair, a switch and a first current mirror. The first input pair comprises a different type of MOS transistor from the second input pair. The switch determines which one of the first or the second input pair is functioning and the operating input pair is configured to output voltage. The switch is further connected to the first input pair and the first current mirror. The first current mirror is further connected to the second input pair, and is configured to copy a current passing through the switch to the second input pair. Therefore an increase of transconductance of the first input pair is compensated by a decrease of transconductance of the second input pair, and the operational amplifier has a substantially constant transconductance no matter which of the first input pair and the second input pair is functioning.
A device for selecting a channel comprises a speed detector configured to detect a speed of a channel selecting mechanism; a controller connected to the speed detector; and a frequency deviation detector connected to the controller and is configured to receive an input signal. The controller selects a wideband channel searching mode for the frequency deviation detector if the speed is higher than a speed threshold, or a narrowband channel searching mode if the speed is lower than the speed threshold. The frequency deviation detector detects an existence of a channel when either an actual frequency deviation of the input signal is lower than a first wideband frequency deviation threshold when the wideband channel searching mode is selected, or the actual frequency deviation is lower than a narrowband frequency deviation threshold when the narrowband channel searching mode is selected.
H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line
H04H 40/36 - Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups specially adapted for stereophonic broadcast receiving
An operational amplifier comprises an input pair, an aiding unit, an even number of amplification stages, a feeding unit, a first current source, a second current source. Both the input pair and the aiding unit are connected to the first current source. The input pair receives differential input voltage. Both the input pair and the aiding unit are further connected to a first stage of the even number of amplification stages. The even number of amplification stages are connected in series, and the last stage of the amplification stages outputs differential output voltages. The feeding unit is configured to receive a common mode voltage of the differential output voltages, and feeds a voltage on a first node of the feeding unit back to the aiding unit so as to provide bias voltage to the aiding unit. The aiding unit avoids dead lock of the input pair.
An amplifier comprises a biasing unit, an amplifying unit and a Schmitt trigger. The biasing unit is configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio. The amplifying unit is connected to the biasing unit and configured to receive an input voltage and generate an amplified voltage based on the biasing current. The Schmitt trigger is connected to the amplifier and configured to generate and output a modified voltage.
A circuit comprises an oscillator, a frequency divider and a comparator. The oscillator generates an oscillating signal (Fvco). The frequency divider is communicatively coupled to the oscillator, divides a frequency of the oscillating signal by a denominator and generates a divided signal. The comparator is communicatively coupled to the oscillator and the frequency divider, and is configured to obtain a first count of the divided signal (Fvco/N) within a predetermined time and a second count of a reference signal within the predetermined time; compare the first count with the second count, and generate a comparison result according to the first count and the second count. The oscillator is further configured to adjust the frequency of the oscillating signal according to the comparison result.
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details
A circuit comprises a transmitter port; a receiver port; an antenna port configured to transmit a signal from the transmitter port to antenna port and receive a signal at antenna port and pass to the receiver port; and a switch configured to switch whether the transmitter port or the receiver port is communicatively coupled to the antenna port. The switch comprises a plurality of NMOS FETs configured to switch between the transmitter port and the receiver port.
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
A circuit comprises a phase combiner and four output ports. The phase combiner adds an in-phase positive input and a quadrature positive input to obtain an in-phase positive output, adds an in-phase negative input and a quadrature negative input to obtain an in-phase negative output, adds the in-phase negative input and the quadrature positive input to obtain a quadrature positive output, and adds the in-phase positive input and the quadrature negative input to obtain a quadrature negative output. The four output ports, are respectively configured to output the in-phase positive output, the in-phase negative output, the quadrature positive output, and the quadrature negative output.
A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
G01R 23/15 - Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit.
A first circuit is configured to communicatively couple to a second circuit including an analog circuit and a digital circuit. The first circuit comprises a lock unit and a sleep unit. The lock unit is configured to receive a lock enable signal and to lock a configuration signal of the digital circuit in response to the lock enable signal. The sleep unit is configured to receive a sleep triggering signal indicating to switch into sleep mode and to generate an off signal to switch off the digital circuit in response to the sleep triggering signal, while the analog circuit remains on.
A Bluetooth receiver comprises a RF front end configured to receive a Bluetooth signal including a preamble and 34-bit pseudo-number (PN); a DC estimator communicatively coupled to the RF front end; and a frame synchronizer communicatively coupled to the DC estimator. The DC estimator is configured to perform DC offset estimation by determining an average value of samples of the preamble and the frame synchronizer is configured to use the 34-bit PN for frame synchronization.
A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
71.
Amplitude shift keying demodulator and method for demodulating an ask signal
An ASK demodulator comprises a rectification circuit which receives and rectifies an ASK signal to generate a rectified current; an active load circuit is coupled to the rectification circuit and receives the rectified current and present an impedance which is inversely proportional to at least a part of the rectified current when a frequency of a base band signal meets a preset condition; a comparator is coupled to the rectification circuit and the active load circuit and receives a reference voltage and a voltage generated based on, at least in part, the rectified current and the impedance, and compares the reference voltage and the generated voltage to generate a demodulated signal.
An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal.
A method comprises: disposing an on-board unit at a preset relative position with respect to a road-side unit; transmitting a signal by the road-side unit; receiving the signal by the on-board unit and detecting a strength of the received signal; calculating, by the on-board unit, a calculated strength of the received signal according to the detected strength of the received signal; storing the calculated strength of the received signal in a memory accessible by the on-board unit; using the stored calculated strength of the received signal to determine if payment of a toll should be made.
G08G 1/00 - Traffic control systems for road vehicles
G08G 1/01 - Detecting movement of traffic to be counted or controlled
G07B 15/02 - Arrangements or apparatus for collecting fares, tolls or entrance fees at one or more control points taking into account a variable factor such as distance or time, e.g. for passenger transport, parking systems or car rental systems
A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.
H03B 19/00 - Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
75.
GFSK modulator and a method for reducing residual frequency modulation and a digital enhanced cordless telecommunication transmitter including the GFSK modulator
A GFSK modulator comprises: a first compensation module, configured to receive a GFSK pulse signal, apply a first amplitude compensation and a first delay compensation to the GFSK pulse signal, so as to generate a first compensated control signal; a second compensation module, configured to receive the GFSK pulse signal, apply a second amplitude compensation and a second delay compensation to the GFSK pulse signal, so as to generate a second compensated control signal; a closed-loop PLL module including a closed-loop PLL, configured to receive and use the first and the second compensated control signals to generate a modulated signal.
A new demodulator with low power consumption and high gain which is suitable for CMOS integration is provided. The demodulator makes use of a MOS configured in a “common-source” status so as to achieve a desirable gain.
A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.
A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.
A method and system to reduce the noise floor of a communications system is disclosed. The system may be incorporated into any device that provides binary samples from a datastream, such as a cordless telephone system. The system is configured to determine a number of bits of the binary samples that are affected by noise. The system is then able to remove the noise by setting those bits to a fixed value. The fixed value may depend on whether the sample is positive or negative. The value to set may be chosen so that the least significant bits of each sample come as close as possible to 0 for that particular numerical representation system. The system can be integrated with other known signal processing methods.
A method and apparatus for demodulating an input signal in a selectable intermediate frequency system is disclosed. The apparatus includes a front end module, a filter, and a phase lock loop (PLL). The front end module mixes the input signal with an oscillating signal. The filter includes at least one characteristic that is selectable to configure an intermediate frequency. The PLL demodulates an output frequency based on the output of the filter.
A method and apparatus for demodulating an input signal, for example, in a communications system, is disclosed. The apparatus includes a signal preconditioner and a demodulator. The signal preconditioner may include a low-pass filter and a hysteretic comparator that are configured to precondition a preconditioner input signal to provide a preconditioner output signal. The modulator may be configured to demodulate the preconditioner output signal.
A method, system, and apparatus for squelching a signal in telecommunications systems. The apparatus includes a filter, two power detectors, a divider, two comparators, a logic gate, and a gain control block. The apparatus receives an input signal, and the power of the signal is detected. The input signal is also filtered to pass only the noise portion of the signal, and the power of the filtered signal is detected. A ratio between the filtered signal power and the input signal power is determined. A first comparator receives the filtered signal power and a second comparator receives the ratio of the filtered signal power and the input signal power. The logic gate receives the outputs from the first and second comparators. The gain control block receives as inputs the logic gate's output and the input signal to the apparatus. The gain control block may attenuate the input signal based on the logic gate's output. The gain control block generates the output signal of the apparatus.
An apparatus to enable half-duplexing capabilities in a two-way communication device is disclosed. The apparatus estimates the signal power and background noise of a first input signal and a second input signal during approximately the same period. The apparatus further provides at least one control signal based on the result of one or more determinations. These determinations may include whether the estimated signal power of at least one of the first and second input signals exceeds a threshold value; whether the estimated signal power of the first input signal exceeds the sum of a first threshold value and the estimated background noise of the first input signal; and whether the estimated signal power of the second input signal exceeds the sum of a second threshold value and the estimated background noise of the second input signal. Other embodiments for use with two-way communication devices and related methods are also disclosed.
A method and apparatus for automatic frequency correction in a demodulation circuit. The apparatus includes a demodulator, a frequency offset estimator, a frequency controller, and an oscillator. The oscillator provides a receiver clock signal which the demodulator employs to demodulate a modulated signal. The frequency offset estimator estimates an offset between a carrier wave frequency of the modulated signal and a frequency of the receiver clock signal. The frequency controller provides a frequency control signal to the oscillator for adjusting the frequency of the receiver clock. While the estimated offset is outside of an adjustment range, the frequency controller maintains the frequency control signal at its previous value. The frequency controller also adjusts the adjustment range based on past error signal values.
H04L 27/152 - Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between an input clock signal and an output clock signal. The loop filter multiplies the phase error signal and filters the multiplied phase error signal. The compressor divides the loop filter output. Based on the compressor output, the clock generator generates an output clock signal is provided as a feedback signal to the phase error detector. The apparatus may also include a glitch cleaner for deglitching the input clock signal.
When there are unused data slots available, a system allocates redundant slots in a data frame to a single mobile unit. A receiving device calculates a quality of slot (QoS) score for each slot that it receives data for. After the QoS score is calculated, the system calculates a Quality of Audio Segment (QoAS) score for each individual segment. It does so by comparing the individual audio segments that were received. Segments that are identical are assigned a positive score, while segments that differ get no score. The QoAS for each segment is added to the QoS for the slot the segment was transmitted in to generate the total score. The system then chooses the segment with the highest total score. If the total score is above a specified threshold, the system outputs the segment to the next component. Otherwise, it outputs a mute segment.
A method and system to reduce the noise floor of a communications system is disclosed. The system may be incorporated into any device that provides binary samples from a datastream, such as a cordless telephone system. The system is configured to determine a number of bits of the binary samples that are affected by noise. The system is then able to remove the noise by setting those bits to a fixed value. The fixed value may depend on whether the sample is positive or negative. The value to set may be chosen so that the least significant bits of each sample come as close as possible to 0 for that particular numerical representation system. The system can be integrated with other known signal processing methods.
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