ViXS Systems, Inc.

Canada

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H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal 18
H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream 16
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding 14
H04N 11/02 - Colour television systems with bandwidth reduction 11
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder 11
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1.

Color gamut mapper for dynamic range conversion and methods for use therewith

      
Application Number 15858096
Grant Number 10257483
Status In Force
Filing Date 2017-12-29
First Publication Date 2018-05-03
Grant Date 2019-04-09
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Liu, Ying
  • Li, Xinghai
  • Feng, Jie

Abstract

In various embodiments, a color gamut mapper includes a gamut map selection generator configured to analyze color space signals and generate a gamut map selection signal in response thereto. A color gamut transformer is configured to process the color space signals via a selected one of a plurality of gamut maps to generate gamut mapped color space signals, wherein the selected one of the plurality of gamut maps is selected in response to the gamut map selection signal. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
  • H04N 5/20 - Circuitry for controlling amplitude response
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • G06T 5/00 - Image enhancement or restoration

2.

Adaptive partition subset selection module and method for use therewith

      
Application Number 14047197
Grant Number 09729869
Status In Force
Filing Date 2013-10-07
First Publication Date 2017-06-29
Grant Date 2017-08-08
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Wang, Jiao
  • Ramachandran, Avinash
  • Zhao, Wilf

Abstract

A partition subset selection module selects a subset of available partitions for a macroblock pair of the plurality of macroblock pairs, based on motion search motion vectors generated by a motion search section, and further based on a macroblock adaptive frame and field indicator. A motion refinement module generates refined motion vectors for the macroblock pair, based on the subset of available partitions for a macroblock pair.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/56 - Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
  • H04N 19/513 - Processing of motion vectors
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/109 - Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
  • H04N 19/16 - Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter for a given display mode, e.g. for interlaced or progressive display mode
  • H04N 19/57 - Motion estimation characterised by a search window with variable size or shape

3.

Memory subsystem consumer trigger

      
Application Number 14853106
Grant Number 10319348
Status In Force
Filing Date 2015-09-14
First Publication Date 2016-11-17
Grant Date 2019-06-11
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Lee, Brian

Abstract

A technique includes writing first processed data to a buffer. The first processed data is generated in response to execution of a first subtask of a pipelined task on first data. The technique includes writing command information to the buffer. The command information is appended to the first processed data and is associated with execution of a second subtask of the pipelined task on second processed data. The technique includes executing the second subtask on the second processed data according to the command information received from the buffer at a conclusion of execution of the second subtask on the first processed data. The technique may include executing the first subtask based on the first data to generate the first processed data. Executing the second subtask may include triggering execution of an execution unit in response to the command information.

IPC Classes  ?

  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory
  • G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • H04N 21/435 - Processing of additional data, e.g. decrypting of additional data or reconstructing software from modules extracted from the transport stream
  • G06F 3/14 - Digital output to display device

4.

Video camera system with distributed control and methods for use therewith

      
Application Number 14677024
Grant Number 09641869
Status In Force
Filing Date 2015-04-02
First Publication Date 2016-10-06
Grant Date 2017-05-02
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Laksono, Indra
  • Daub, Sally Jean
  • Pomeroy, John
  • Zhao, Xu Gang

Abstract

Aspects of the subject disclosure may include, for example, a video camera system that includes a first subset of video cameras that are configured to generate at least one broadcast video signal of an event, and a second subset of video cameras that are each individually controllable in response to subscriber control data from a corresponding one of a plurality of video player systems to generate a plurality of processed video signals of the event. A video access server receives the subscriber control data from the video player systems corresponding to a plurality of subscribers for control of the second subset of video cameras, and for routing the processed video signals of the event such that each of the plurality of processed video signals of the event is routed to the corresponding one of the plurality of video player systems. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 21/454 - Content filtering, e.g. blocking advertisements
  • H04N 21/218 - Source of audio or video content, e.g. local disk arrays
  • H04N 21/2187 - Live feed
  • H04N 21/254 - Management at additional data server, e.g. shopping server or rights management server
  • H04N 21/258 - Client or end-user data management, e.g. managing client capabilities, user preferences or demographics or processing of multiple end-users preferences to derive collaborative data
  • H04N 21/472 - End-user interface for requesting content, additional data or servicesEnd-user interface for interacting with content, e.g. for content reservation or setting reminders, for requesting event notification or for manipulating displayed content
  • G05D 1/00 - Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
  • H04N 5/247 - Arrangement of television cameras
  • H04N 5/268 - Signal distribution or switching

5.

Bank address remapping to load balance memory traffic among banks of memory

      
Application Number 14802236
Grant Number 10019358
Status In Force
Filing Date 2015-07-17
First Publication Date 2016-09-22
Grant Date 2018-07-10
Owner VIXS SYSTEMS INC. (Canada)
Inventor Lee, Brian

Abstract

A system includes a processing component and a memory controller. The memory controller is to conduct memory accesses to a banked memory responsive to memory access requests from the processing component, whereby the memory controller is to distribute memory accesses among the plurality of banks by modifying, for each memory access request, a bank of the bank memory referenced by the memory access request. A memory device includes a plurality of banks, an interface to receive memory access requests, bank remapping logic, and access control logic. The bank remapping logic is to, for each received memory access request, remap a bank segment of a memory address associated with the received memory access request with a modified bank segment. The access control logic is to, for each received memory access request, access a bank of the plurality of banks based on the modified bank segment for the memory access request.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

6.

Media source device with digital format conversion and methods for use therewith

      
Application Number 14982684
Grant Number 09706260
Status In Force
Filing Date 2015-12-29
First Publication Date 2016-07-28
Grant Date 2017-07-11
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Dong, Suiwu
  • Daub, Sally Jean

Abstract

A media source device includes media files in either original source format or in alternative digital formats, based on a content descriptor indicated by a client device from a plurality of content descriptors generated to represent possible transcodings of the source format. In the alternative, a media source device can receive a client device report and subsequent request for a media file. The media source device can send the media file to the client device in a particular digital format based on whether the content descriptor corresponding to the media file is compatible or incompatible with the client device. The bit rate used to send the media file to the client device can be adjusted based on the available transmit bit rate.

IPC Classes  ?

  • G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
  • G06F 13/38 - Information transfer, e.g. on bus
  • H04N 21/647 - Control signaling between network components and server or clientsNetwork processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load or bridging between two different networks, e.g. between IP and wireless
  • H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
  • H04N 21/235 - Processing of additional data, e.g. scrambling of additional data or processing content descriptors
  • H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
  • H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
  • H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
  • H04N 21/643 - Communication protocols
  • H04N 21/654 - Transmission by server directed to the client
  • H04N 21/6587 - Control parameters, e.g. trick play commands or viewpoint selection
  • H04N 21/84 - Generation or processing of descriptive data, e.g. content descriptors
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream

7.

Bonded OFDM communication system

      
Application Number 15000912
Grant Number 09634874
Status In Force
Filing Date 2016-01-19
First Publication Date 2016-07-21
Grant Date 2017-04-25
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Mittelsteadt, Cimarron
  • Dubey, Amit Ranjan
  • Cave, Michael

Abstract

An orthogonal frequency division multiplexing (OFDM) communication system includes a first interface having a first cable coupler to couple to a first end of a coaxial cable, and a first plurality of signal pathways coupled to the first cable coupler. Each signal pathway of the first plurality includes a physical (PHY) layer component and a radio frequency (RF) front end coupled to the PHY layer component. The system further includes a second interface having a second cable coupler to couple to a second end of a coaxial cable, and a second plurality of signal pathways coupled to the second cable coupler. Each signal pathway of the second plurality corresponds to a signal pathway of the first plurality and includes a PHY layer component and an RF front end coupled to the PHY layer component.

IPC Classes  ?

  • H04L 27/00 - Modulated-carrier systems
  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 29/08 - Transmission control procedure, e.g. data link level control procedure

8.

Dynamic range converter with generic architecture and methods for use therewith

      
Application Number 14863065
Grant Number 09544560
Status In Force
Filing Date 2015-09-23
First Publication Date 2016-07-14
Grant Date 2017-01-10
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Wallace, Bradley Arthur
  • Wu, Xiaowen
  • Feng, Jie
  • Li, Xinghai

Abstract

In various embodiments, a dynamic range converter includes a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 9/64 - Circuits for processing colour signals
  • G06T 5/00 - Image enhancement or restoration

9.

Dynamic range converter with reconfigurable architecture and methods for use therewith

      
Application Number 14867205
Grant Number 09560330
Status In Force
Filing Date 2015-09-28
First Publication Date 2016-07-14
Grant Date 2017-01-31
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Wallace, Bradley Arthur
  • Wu, Xiaowen
  • Feng, Jie
  • Li, Xinghai

Abstract

In various embodiments, a dynamic range converter includes a plurality of circuits, including at least one configurable circuit that operates based on configuration data. The plurality of circuits include a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 9/64 - Circuits for processing colour signals
  • G06T 5/00 - Image enhancement or restoration

10.

Dynamic range converter with logarithmic conversion and methods for use therewith

      
Application Number 14867234
Grant Number 09654755
Status In Force
Filing Date 2015-09-28
First Publication Date 2016-07-14
Grant Date 2017-05-16
Owner VIXS Systems, Inc. (Canada)
Inventor Wallace, Bradley Arthur

Abstract

In various embodiments, a dynamic range converter includes at least one circuit including a logarithm base 2 (log 2) domain circuit that uses piecewise linear interpolation to perform as at least a portion of one of: a linearizer configured to convert nonlinear color space signals to linearized color space signals; a delinearizer configured to convert linear color space signals to nonlinearized color space signals; a chrominance tone mapper for scaling gamut shaped components in accordance with dynamic color transform metadata to generate chrominance mapped components; or a luminance tone mapper for scaling color remapped components in accordance with the dynamic color transform metadata to generate luminance mapped components. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • H04N 5/20 - Circuitry for controlling amplitude response
  • G06T 5/00 - Image enhancement or restoration

11.

Dynamic range converter with pipelined architecture and methods for use therewith

      
Application Number 14867312
Grant Number 09589313
Status In Force
Filing Date 2015-09-28
First Publication Date 2016-07-14
Grant Date 2017-03-07
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Wallace, Bradley Arthur

Abstract

In various embodiments, a dynamic range converter includes a plurality of circuits configured in a processing pipeline for operation timed by a pixel clock. The plurality of circuits include a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed.

IPC Classes  ?

  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • G06T 5/00 - Image enhancement or restoration
  • H04N 5/20 - Circuitry for controlling amplitude response
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits

12.

Color gamut mapper for dynamic range conversion and methods for use therewith

      
Application Number 14953765
Grant Number 09860504
Status In Force
Filing Date 2015-11-30
First Publication Date 2016-07-14
Grant Date 2018-01-02
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Liu, Ying
  • Li, Xinghai
  • Feng, Jie

Abstract

In various embodiments, a color gamut mapper includes a gamut map selection generator configured to analyze color space signals and generate a gamut map selection signal in response thereto. A color gamut transformer is configured to process the color space signals via a selected one of a plurality of gamut maps to generate gamut mapped color space signals, wherein the selected one of the plurality of gamut maps is selected in response to the gamut map selection signal. Other embodiments are disclosed.

IPC Classes  ?

  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
  • H04N 5/20 - Circuitry for controlling amplitude response
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • G06T 5/00 - Image enhancement or restoration

13.

Dynamic range converter with frame by frame adaptation and methods for use therewith

      
Application Number 14873916
Grant Number 09558538
Status In Force
Filing Date 2015-10-02
First Publication Date 2016-07-14
Grant Date 2017-01-31
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Wallace, Bradley Arthur
  • Wu, Xiaowen

Abstract

In various embodiments, a dynamic range converter includes a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video on a frame by frame basis to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed.

IPC Classes  ?

  • G06T 5/00 - Image enhancement or restoration
  • H04N 5/20 - Circuitry for controlling amplitude response
  • H04N 5/68 - Circuit details for cathode-ray display tubes
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits

14.

Tone mapper with filtering for dynamic range conversion and methods for use therewith

      
Application Number 14942242
Grant Number 09652870
Status In Force
Filing Date 2015-11-16
First Publication Date 2016-07-14
Grant Date 2017-05-16
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Xinghai
  • Liu, Ying
  • Zhao, Xu Gang

Abstract

In various embodiments, a filtering tone mapper includes a two-dimensional filter. A tone mapper configured to apply tone mapping to a video frame in accordance with a tone mapping function to generate a processed video frame, wherein the tone mapper operates in conjunction with the two-dimensional filter to apply the tone mapping to pixels of the video frame based on a plurality of adjacent pixels of the video frame. Other embodiments are disclosed.

IPC Classes  ?

  • G06T 1/00 - General purpose image data processing
  • H04N 1/60 - Colour correction or control
  • H04N 21/00 - Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N 5/20 - Circuitry for controlling amplitude response
  • H04N 9/67 - Circuits for processing colour signals for matrixing
  • H04N 9/68 - Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
  • G06T 11/00 - 2D [Two Dimensional] image generation

15.

Frame buffer compression using separate aggregation of fixed-length and variable-length components of codewords

      
Application Number 14536859
Grant Number 09712848
Status In Force
Filing Date 2014-11-10
First Publication Date 2016-05-12
Grant Date 2017-07-18
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Cheung, Wendy Wai Yin
  • Guo, Xin

Abstract

Each set of pels of an image frame is encoded into a corresponding set of codewords having fixed-length and unary variable-length components. The variable-length components are combined into a variable-length portion and the fixed-length components are separately combined into a fixed-length portion that is attached to the variable-length portion to complete a bit segment. For decompression, a first bit string of a fixed number of bits is identified as a fixed-length portion of the bit segment. A search window placed adjacent to the first bit string is scanned to find a second bit string having a number of termination bits equal to the number of codewords in the set, with the second bit string thus representing the variable-length portion of a corresponding bit segment. Each variable-length component of the identified variable-length portion is combined with a corresponding fixed-length component of the identified fixed-length portion to recreate a corresponding codeword.

IPC Classes  ?

  • H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
  • H04N 19/88 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks
  • H03M 7/40 - Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code

16.

Dongle device with video encoding and methods for use therewith

      
Application Number 14687247
Grant Number 09743126
Status In Force
Filing Date 2015-04-15
First Publication Date 2016-01-14
Grant Date 2017-08-22
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Sahdra, Kuldip
  • Stewart, Norman
  • Huang, Shijun D.
  • Tong, Mang Lun A.
  • Leung, Lewis

Abstract

A universal serial bus (USB) dongle device includes a USB interface for receiving a video signal in a first format and for sending a processed video signal in a second format wherein the first format differs from the second format. An encoding module generates the processed video signal based on the video signal. In a further embodiment, A video card includes a video receiver for receiving a video signal in a first format, based on a selection command. An encoding module generates a processed video signal in a second format based on the video signal, wherein the first format differs from the second format. A USB interface transfers the processed video signal to the host device, receives the selection command from the host device and receives a power signal from the host device to power the video receiver and the encoding module.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • H04N 21/418 - External card to be used in combination with the client device, e.g. for conditional access
  • H04N 21/41 - Structure of clientStructure of client peripherals
  • H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
  • H04N 21/63 - Control signaling between client, server and network componentsNetwork processes for video distribution between server and clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB'sCommunication protocolsAddressing
  • H04N 21/436 - Interfacing a local distribution network, e.g. communicating with another STB or inside the home
  • H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
  • H04N 21/4405 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
  • H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
  • H04N 21/482 - End-user interface for program selection
  • G06F 13/40 - Bus structure
  • G06F 13/38 - Information transfer, e.g. on bus

17.

Configurable transcoder and methods for use therewith

      
Application Number 14723641
Grant Number 09800880
Status In Force
Filing Date 2015-05-28
First Publication Date 2015-11-12
Grant Date 2017-10-24
Owner ViXS Systems, Inc. (Canada)
Inventor Wang, Yimin (jim)

Abstract

A transcoder includes a demultiplexer that demultiplexes a video signal into a moving image stream, an audio stream and a subtitle stream. A stream probe generates stream format identification data based on the video signal. A transcoder configuration module generates hardware/software configuration data based on the stream format identification data. The hardware/software configuration data configures a plurality of hardware transcoders and the processing device to operate to generate a transcoded video stream, a transcoded audio stream and processed subtitle stream via selected hardware and software blocks. A remultiplexer generates the processed video signal by remultiplexing the transcoded video stream, the transcoded audio stream and the processed subtitle stream, based on the hardware/software configuration data.

IPC Classes  ?

  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 21/222 - Secondary servers, e.g. proxy server or cable television Head-end
  • H04N 21/2365 - Multiplexing of several video streams
  • H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
  • H04N 19/136 - Incoming video signal characteristics or properties
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264

18.

Video scaling using multiple video paths

      
Application Number 14250764
Grant Number 09582852
Status In Force
Filing Date 2014-04-11
First Publication Date 2015-10-15
Grant Date 2017-02-28
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Wallace, Bradley A.
  • Astrachan, Paul M.

Abstract

A video scaling technique includes scaling a first dimension and a second dimension of a frame of video data to generate a scaled frame of video data. The scaling includes scaling the second dimension of a first portion of a frame of video data at a first rate to generate first scaled pixels and scaling the second dimension of a second portion of the frame of video data at the first rate to generate second scaled pixels. The scaling includes combining first output pixels based on the first scaled pixels and second output pixels based on the second scaled pixels to provide pixels of the scaled frame of video data at a second rate. The first rate is a fraction of the second rate.

IPC Classes  ?

  • G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
  • G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • H04N 7/01 - Conversion of standards

19.

Video system with customized tiling and methods for use therewith

      
Application Number 14678232
Grant Number 09628870
Status In Force
Filing Date 2015-04-03
First Publication Date 2015-10-01
Grant Date 2017-04-18
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Daub, Sally Jean
  • Pomeroy, John
  • Laksono, Indra

Abstract

A tile processor is configured to analyze sensor data to identify the at least one viewer and to generate tile configuration data in response to the identification of the at least one viewer that indicates a tiled partitioning of a screen display into a plurality of tiled regions. An A/V player generates tiled display data for display of the at least video program on a display device in accordance with the tile configuration data.

IPC Classes  ?

  • H04H 60/33 - Arrangements for monitoring the users' behaviour or opinions
  • H04N 21/81 - Monomedia components thereof
  • H04N 21/4415 - Acquiring end-user identification using biometric characteristics of the user, e.g. by voice recognition or fingerprint scanning
  • H04N 21/482 - End-user interface for program selection
  • H04N 21/485 - End-user interface for client configuration

20.

Video processing with static and dynamic regions and method for use therewith

      
Application Number 14225981
Grant Number 09716888
Status In Force
Filing Date 2014-03-26
First Publication Date 2015-10-01
Grant Date 2017-07-25
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Zhao, Xu Gang
  • Li, Xinghai

Abstract

A system for processing a video signal includes a static region identification and separation module for generating static region image data corresponding to a static region of the video signal, for generating dynamic region video data corresponding to at least one dynamic region in the video signal and for generating dynamic region location data that indicates at least one location corresponding to the at least one dynamic region in the video signal. A static region encoding module image encodes the state region image data to produce encoded static region data. A video encoder section generates at least one encoded video signal by compressing the dynamic region video data.

IPC Classes  ?

  • H04N 19/23 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with coding of regions that are present throughout a whole video segment, e.g. sprites, background or mosaic
  • H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
  • H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks

21.

Video system with viewer analysis and methods for use therewith

      
Application Number 14217819
Grant Number 09282367
Status In Force
Filing Date 2014-03-18
First Publication Date 2015-09-24
Grant Date 2016-03-08
Owner ViXS Systems, Inc. (Canada)
Inventor Daub, Sally Jean

Abstract

A system includes a viewer sensor that generates sensor data for sensing one or more viewers of a video display device. A viewer analysis module analyzes the sensor data to generate viewer data. A selection module selects selected content based on the viewer data and generates selected content data based on the selected content for display to the viewer or viewers via the video display device or via a mobile device associated with the viewer or viewers.

IPC Classes  ?

  • H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
  • H04H 60/33 - Arrangements for monitoring the users' behaviour or opinions
  • H04H 60/45 - Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying users
  • H04H 60/47 - Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for recognising genres
  • H04N 21/41 - Structure of clientStructure of client peripherals
  • H04N 21/4223 - Cameras
  • H04N 21/4415 - Acquiring end-user identification using biometric characteristics of the user, e.g. by voice recognition or fingerprint scanning
  • H04N 21/45 - Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies or resolving scheduling conflicts
  • H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
  • H04N 21/454 - Content filtering, e.g. blocking advertisements
  • H04N 21/458 - Scheduling content for creating a personalised stream, e.g. by combining a locally stored advertisement with an incoming streamUpdating operations, e.g. for OS modules
  • H04N 21/81 - Monomedia components thereof

22.

Processing system with transport stream aggregation and methods for use therewith

      
Application Number 14301805
Grant Number 09743035
Status In Force
Filing Date 2014-06-11
First Publication Date 2015-09-17
Grant Date 2017-08-22
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Stewart, Norman Vernon Douglas

Abstract

A processing system includes a transport stream aggregator that receives a plurality of transport streams in a transport stream format and that generates an aggregated transport stream in response. The transport stream aggregator processes transport stream packets of the plurality of transport streams and replaces a packet synchronization field with a customized synchronization field. A processing device is configured to generate a processed video signal from the aggregated transport stream.

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • H04N 7/01 - Conversion of standards
  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • H04N 5/44 - Receiver circuitry
  • H04N 7/08 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band
  • H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
  • H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
  • H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
  • H04L 29/08 - Transmission control procedure, e.g. data link level control procedure

23.

Video encoder with transform size preprocessing and methods for use therewith

      
Application Number 14196326
Grant Number 09591313
Status In Force
Filing Date 2014-03-04
First Publication Date 2015-09-10
Grant Date 2017-03-07
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A transform size determination module includes a transform size preprocessor configured to process residual data from a picture of the video data to evaluate a plurality of transform block sizes and to generate candidate transform size data that indicates a selected non-null proper subset of the plurality of transform block size. A final transform size determination processor generates final transform block size data that indicates a final transform block size, based on the candidate transform size data.

IPC Classes  ?

  • H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/149 - Data rate or code amount at the encoder output by estimating the code amount by means of a model, e.g. mathematical model or statistical model
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients

24.

Compensated oscillator

      
Application Number 14186661
Grant Number 09276584
Status In Force
Filing Date 2014-02-21
First Publication Date 2015-08-27
Grant Date 2016-03-01
Owner ViXS Systems Inc. (Canada)
Inventor
  • Au Yeung, Chung Fai
  • Cave, Michael

Abstract

An oscillator includes a compensated current source that adjusts an output current based on process, supply voltage, and temperature (“PVT”) variations of an integrated circuit device. The oscillator generates an output signal having a frequency based, in part, on the output current of the compensated current source. Accordingly, the output signal has a relatively low sensitivity to PVT variations.

IPC Classes  ?

  • H03L 1/00 - Stabilisation of generator output against variations of physical values, e.g. power supply
  • H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only

25.

Codec engine with inline image processing

      
Application Number 14154292
Grant Number 09471995
Status In Force
Filing Date 2014-01-14
First Publication Date 2015-07-16
Grant Date 2016-10-18
Owner VIXS Systems Inc. (Canada)
Inventor
  • Laksono, Indra
  • Young, Eric
  • Yeh, Chun-Chin

Abstract

A video device includes a codec engine to process video data to generate a stream of pixel blocks representing a picture of a sequence of pictures represented by the video data, an image processing module to receive the stream of pixel blocks via a local path between the codec engine and the image processing module and to perform at least one image processing function for the picture using pixel blocks of the stream of pixel blocks received via the local path to generate image processing result data representative of the picture. The video device further includes a storage interface coupleable to a storage component, the storage interface to provide the image processing result data for storage at the storage component.

IPC Classes  ?

  • G06T 9/00 - Image coding
  • H04N 7/01 - Conversion of standards
  • G09G 5/39 - Control of the bit-mapped memory
  • G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
  • G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution

26.

Video encoder with intra-prediction candidate screening and methods for use therewith

      
Application Number 14159805
Grant Number 09294764
Status In Force
Filing Date 2014-01-21
First Publication Date 2015-07-09
Grant Date 2016-03-22
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

An intra-prediction module includes a candidate screening preprocessor configured to process blocks of picture data based on intra-prediction candidate data corresponding to a plurality of pixels of the blocks. The intra-prediction candidate data indicates a first subset selected from a plurality of intra-prediction partitions and a second subset selected from a plurality of intra-prediction modes. The processing includes screening the intra-prediction candidate data to generate screened intra-prediction candidate data that indicates a third subset selected from a plurality of intra-prediction partitions and a fourth subset selected from a plurality of intra-prediction modes. A rate distortion optimization processor determines final intra-prediction data, based on the screened intra-prediction candidate data.

IPC Classes  ?

  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/136 - Incoming video signal characteristics or properties
  • H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
  • H04N 19/51 - Motion estimation or motion compensation
  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
  • H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel

27.

Video encoder with intra-prediction pre-processing and methods for use therewith

      
Application Number 14159829
Grant Number 09294765
Status In Force
Filing Date 2014-01-21
First Publication Date 2015-07-09
Grant Date 2016-03-22
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

An intra-prediction module includes an intra-prediction preprocessor configured to process pixel data from blocks of picture data to determine edge strength data and edge angle range data corresponding to a plurality of pixels of the blocks, and further to generate intra-prediction candidate data based on the edge strength data and the edge angle range data. The intra-prediction candidate data indicates a first subset selected from a plurality of intra-prediction partitions and a second subset selected from a plurality of intra-prediction modes. A rate distortion optimization processor determines final intra-prediction data, based on the intra-prediction candidate data.

IPC Classes  ?

  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/136 - Incoming video signal characteristics or properties
  • H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
  • H04N 19/51 - Motion estimation or motion compensation
  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
  • H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel

28.

Video encoder with weighted prediction and methods for use therewith

      
Application Number 14151019
Grant Number 09654775
Status In Force
Filing Date 2014-01-09
First Publication Date 2015-07-09
Grant Date 2017-05-16
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A weighted prediction module includes a weighted prediction parameter generation module configured to generate a plurality of initial weighted prediction parameters, to analyze the plurality of initial weighted prediction parameters, and to generate a refinement flag that indicates one of: enable parameter refinement and disable parameter refinement. A weighted prediction parameter refinement module is configured to generate a plurality of refined weighted prediction parameters by refining the plurality of initial weighted prediction parameters, when the refinement flag indicates that the parameter refinement is enabled. A weighted prediction flag generation module is configured to generate a weighted prediction flag that indicates one of: enable weighted prediction and disable weighted prediction, based on the refinement flag.

IPC Classes  ?

  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/56 - Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/109 - Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
  • H04N 19/46 - Embedding additional information in the video signal during the compression process
  • H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/187 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
  • H04N 19/577 - Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
  • H04N 19/154 - Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion

29.

Video encoder with block merging and methods for use therewith

      
Application Number 14145508
Grant Number 09438925
Status In Force
Filing Date 2013-12-31
First Publication Date 2015-07-02
Grant Date 2016-09-06
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A video encoder includes a motion search module that determines a motion search motion vector for a region of a selected picture of the plurality of pictures. The motion search module determines the region by merging selected ones of a plurality of blocks of the selected picture based on an evaluation of a cost matrix associated with the plurality of blocks of the selected picture.

IPC Classes  ?

  • H04N 19/513 - Processing of motion vectors
  • H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
  • H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/53 - Multi-resolution motion estimationHierarchical motion estimation
  • H04N 19/136 - Incoming video signal characteristics or properties
  • H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
  • H04N 19/543 - Motion estimation other than block-based using regions

30.

Processing system with register arbitration and methods for use therewith

      
Application Number 14266287
Grant Number 09633180
Status In Force
Filing Date 2014-04-30
First Publication Date 2015-06-11
Grant Date 2017-04-25
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Stewart, Norman Vernon Douglas

Abstract

A processing system includes a memory module that includes a register space for storing a plurality of register data in a plurality of registers and secure access data corresponding to the register space. A register arbitration module operates to receive a request to access one of the registers from a client module; retrieve secure access data corresponding to the client to determine if the client is trusted; and to grant the request to access the register if the client is trusted. If the client is not trusted, the register arbitration module retrieves secure access data to determine if the register is non-secured for the client. The register arbitration module grants the request to access the register when the register is non-secured for the client.

IPC Classes  ?

  • H04N 13/00 - Stereoscopic video systemsMulti-view video systemsDetails thereof
  • G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
  • G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/124 - Quantisation

31.

Watermark insertion in frequency domain for audio encoding/decoding/transcoding

      
Application Number 14096959
Grant Number 09620133
Status In Force
Filing Date 2013-12-04
First Publication Date 2015-06-04
Grant Date 2017-04-11
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Yang, Qi
  • Feng, Jie

Abstract

An audio processing device includes an initial processing module to generate a stream of frequency coefficients based on input audio data, a watermarking module to embed a digital watermark into the stream of frequency coefficients to generate a modified stream of frequency coefficients, and a final processing module to process the modified stream of frequency coefficients to generate output audio data. In some implementations, the input audio data comprises unencoded audio data, the initial processing module comprises a frequency domain transform module to perform a time-to-frequency domain transform to generate the unencoded audio data, and the output audio data is encoded audio data. In other instances, the input audio data comprises encoded audio data, the initial processing module comprises an initial decoding module to partially decode the encoded audio data to generate the stream of frequency coefficients, and the output audio data is decoded audio data.

IPC Classes  ?

  • G10L 19/00 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocodersCoding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
  • G10L 19/018 - Audio watermarking, i.e. embedding inaudible data in the audio signal
  • G10L 19/02 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocodersCoding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders

32.

Motion search with scaled and unscaled pictures

      
Application Number 14065605
Grant Number 09706221
Status In Force
Filing Date 2013-10-29
First Publication Date 2015-04-30
Grant Date 2017-07-11
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Li, Xinghai
  • Guo, Xin

Abstract

Reference pictures received via a video signal are downscaled to a specified resolution by a video encoder/decoder. For each current picture being processed by the video encoder/decoder, the current picture is maintained at its original received resolution, but is divided into blocks. Each block is further divided into sub-blocks, and each sub-block is compared, for a set of specified positions, to a corresponding block of the downscaled reference image to generate a set of candidate motion vectors. The candidate motion vectors are scored according to how closely their corresponding sub-block matches the corresponding block of the reference picture at the corresponding position, and a motion vector for each block of the current image is selected based on the scores. The selected motion vectors are used to process (e.g. encode) the video signal.

IPC Classes  ?

  • H04N 19/124 - Quantisation
  • H04N 19/523 - Motion estimation or motion compensation with sub-pixel accuracy
  • H04N 19/567 - Motion estimation based on rate distortion criteria
  • H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution

33.

Neighbor management for use in entropy encoding and methods for use therewith

      
Application Number 14475908
Grant Number 10142625
Status In Force
Filing Date 2014-09-03
First Publication Date 2015-01-29
Grant Date 2018-11-27
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Zhao, Xu Gang (wilf)
  • Li, Xinghai
  • Wang, Jason

Abstract

An entropy coding module is provided for use in a video encoder that encodes a video input signal based on a plurality of macroblocks derived from the video input signal. The entropy coding module includes an entropy coder that generates entropy encoded data from discrete transformed coefficients for the plurality of macroblocks. A neighbor management module stores neighbor data for at least one macroblock of the plurality of macroblocks for retrieval by the entropy encoder, when operating on at least one neighboring macroblock of the plurality of macroblocks.

IPC Classes  ?

  • H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
  • H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/124 - Quantisation
  • H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

34.

Quantization parameter adjustment based on sum of variance and estimated picture encoding cost

      
Application Number 13926179
Grant Number 09565440
Status In Force
Filing Date 2013-06-25
First Publication Date 2014-12-25
Grant Date 2017-02-07
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A video processing device includes a rate control module to determine more accurate initial quantization parameters at each scene switching point and to adjust the QP parameters in response to scene changes using a sum of variances metric and an estimated picture encoding cost metric from a coding complex estimation block. To determine a first quantization parameter set, a sum of variances metric and an estimated picture encoding cost metric for an initial set pictures of a video stream are used. A bit allocation module is to set a target bit allocation for infra-encoded pictures as substantially proportional to the sum of variances metric and substantially inversely proportional to the estimated picture encoding cost metric, and set a target bit allocation for forward predictive and bi-predictive pictures as substantially proportional to the estimated picture encoding cost metric and substantially inversely proportional to the sum of variances metric.

IPC Classes  ?

  • H04N 19/169 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
  • H04N 19/124 - Quantisation
  • H04N 19/149 - Data rate or code amount at the encoder output by estimating the code amount by means of a model, e.g. mathematical model or statistical model
  • H04N 19/142 - Detection of scene cut or scene change
  • H04N 19/154 - Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion
  • H04N 19/179 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scene or a shot

35.

Scene change detection using sum of variance and estimated picture encoding cost

      
Application Number 13926185
Grant Number 09426475
Status In Force
Filing Date 2013-06-25
First Publication Date 2014-12-25
Grant Date 2016-08-23
Owner VIXS Sytems Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A video processing device includes a complexity estimation module to determine a first sum of variances metric and a first estimated picture encoding cost metric for a first picture of a video stream. The video processing device further includes a scene analysis module to determine a first threshold based on a first statistical feature for sum of variance metrics of a set of one or more pictures preceding the first picture in the video stream and a second threshold based on a second statistical feature for estimated picture encoding cost metrics of the set of one or more pictures. The scene analysis module further is to identify a scene change as occurring at the first picture based on the first sum of variances metric, the first estimated picture encoding cost metric, the first threshold, and the second threshold.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 11/04 - Colour television systems using pulse code modulation
  • H04N 19/124 - Quantisation
  • H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
  • H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/142 - Detection of scene cut or scene change
  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
  • H04N 19/177 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters

36.

Multi-format video decoder with vector processing instructions and methods for use therewith

      
Application Number 14249694
Grant Number 09369713
Status In Force
Filing Date 2014-04-10
First Publication Date 2014-11-20
Grant Date 2016-06-14
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Laksono, Indra
  • Yang, Kai
  • Wang, Hongri
  • Liu, Dong
  • Zhao, Xu Gang
  • Young, Eric
  • Hong, Edward

Abstract

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

IPC Classes  ?

  • H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission
  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 11/04 - Colour television systems using pulse code modulation
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
  • H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
  • H04N 19/136 - Incoming video signal characteristics or properties

37.

Video processor with random access to compressed frame buffer and methods for use therewith

      
Application Number 13933302
Grant Number 09503744
Status In Force
Filing Date 2013-07-02
First Publication Date 2014-07-24
Grant Date 2016-11-22
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Yang, Qi
  • Guo, Xin
  • Laksono, Indra
  • Zhao, Xu Gang

Abstract

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A data object compression/decompression module generates compressed video frame data by compressing a plurality of video data objects into a plurality of compressed video data objects, storing the plurality of compressed video data objects in a compressed frame buffer. The data object compression/decompression module retrieves a selected portion of video frame data from the compressed video frame buffer by identifying selected ones of plurality of compressed video data objects that correspond to the selected portion of video frame data, retrieving the selected ones of the plurality of compressed video data objects and generating the uncompressed video frame data by decompressing the selected ones of the plurality of compressed video data objects.

IPC Classes  ?

  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/20 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding

38.

Video processor with lossy and lossless frame buffer compression and methods for use therewith

      
Application Number 13933329
Grant Number 09277218
Status In Force
Filing Date 2013-07-02
First Publication Date 2014-07-24
Grant Date 2016-03-01
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Guo, Xin
  • Yang, Qi
  • Laksono, Indra
  • Zhao, Xu Gang

Abstract

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A data object compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing a plurality of video data objects into a plurality of compressed video data objects, wherein a first subset of the plurality of video data objects are compressed via lossless compression and a second subset of the plurality of video data objects are compressed via lossy compression.

IPC Classes  ?

  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/20 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding

39.

Video processor with reduced memory bandwidth and methods for use therewith

      
Application Number 14133775
Grant Number 09407920
Status In Force
Filing Date 2013-12-19
First Publication Date 2014-07-24
Grant Date 2016-08-02
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Guo, Xin
  • Yang, Qi
  • Hong, Edward
  • Cheung, Wendy Wai Yin
  • Young, Eric
  • Yeh, Chun-Chin

Abstract

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

IPC Classes  ?

  • G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
  • H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
  • H04N 19/433 - Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/426 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
  • H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/167 - Position within a video image, e.g. region of interest [ROI]

40.

Video processing system and device with encoding and decoding modes and method for use therewith

      
Application Number 14151101
Grant Number 08917757
Status In Force
Filing Date 2014-01-09
First Publication Date 2014-06-12
Grant Date 2014-12-23
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Young, Eric
  • Hong, Edward

Abstract

A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

IPC Classes  ?

  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/146 - Data rate or code amount at the encoder output
  • H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation

41.

Adaptive single-field/dual-field video encoding

      
Application Number 13705422
Grant Number 09560361
Status In Force
Filing Date 2012-12-05
First Publication Date 2014-06-05
Grant Date 2017-01-31
Owner VIXS SYSTEMS INC. (Canada)
Inventor
  • Zhao, Xu Gang
  • Li, Ying

Abstract

A video processing device includes an interface to receive an input video stream and an interface to provide an encoded video stream. The input video stream includes a sequence of frames. Each frame comprises two fields. The video processing device further includes an encoder to encode the input video stream to generate the encoded video stream. The encoder is to dynamically switch between a first encoding mode and a second encoding mode responsive to a variable quantization parameter. In the first encoding mode the encoder is to encode both fields or the complete frame of a corresponding frame of the sequence. In the second encoding mode the encoder is to encode only one field of the two fields of a corresponding frame of the sequence. This approach can achieve a specified low bit rate with reduced quantization effects while keeping the horizontal resolution unchanged.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • H04N 19/112 - Selection of coding mode or of prediction mode according to a given display mode, e.g. for interlaced or progressive display mode
  • H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
  • H04N 19/149 - Data rate or code amount at the encoder output by estimating the code amount by means of a model, e.g. mathematical model or statistical model
  • H04N 19/124 - Quantisation

42.

Video encoding system with adaptive hierarchical B-frames and method for use therewith

      
Application Number 13692388
Grant Number 09307235
Status In Force
Filing Date 2012-12-03
First Publication Date 2014-06-05
Grant Date 2016-04-05
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Zhao, Xu Gang
  • Pomeroy, John

Abstract

A device encodes a video signal having a sequence of images into an encoded video signal. The device includes a group of picture (GOP) adaption module that detects a high complexity scene in the sequence of images and that generates GOP adaption data indicating the high complexity scene when the high complexity scene is detected. An encoding module generates the encoded video signal with hierarchical B frames disabled when the GOP adaption data indicates the high complexity scene.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • H04N 19/177 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
  • H04N 19/114 - Adapting the group of pictures [GOP] structure, e.g. number of B-frames between two anchor frames
  • H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
  • H04N 19/577 - Motion compensation with bidirectional frame interpolation, i.e. using B-pictures

43.

Video processing device with ring oscillator for power adjustment and methods for use therewith

      
Application Number 13741632
Grant Number 09239604
Status In Force
Filing Date 2013-01-15
First Publication Date 2014-03-06
Grant Date 2016-01-19
Owner VIXS Systems, Inc. (Canada)
Inventor
  • Weinberg, Yoav
  • Stewart, Norman Vernon Douglas

Abstract

A video processing device includes a substrate. A plurality of ring oscillators generate a corresponding plurality of ring oscillator outputs. A control circuit generates power adjustment signals for adjusting at least one power supply voltage of the video processing device, based on the plurality of oscillator outputs.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • H04N 5/14 - Picture signal circuitry for video frequency region
  • H04N 19/127 - Prioritisation of hardware or computational resources
  • H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

44.

Video processing device with register adjustment generator and methods for use therewith

      
Application Number 13744031
Grant Number 09310873
Status In Force
Filing Date 2013-01-17
First Publication Date 2014-03-06
Grant Date 2016-04-12
Owner ViXS Systems, Inc. (Canada)
Inventor Weinberg, Yoav

Abstract

A video processing device includes a plurality of circuit modules that cooperate to process an input video signal into a processed video signal. A control circuit generates a plurality of adjustment parameters in response to a calibration of the plurality of circuit modules and that includes a register adjustment generator that generates a register file modification based on the plurality of adjustment parameters.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
  • H04N 21/443 - OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
  • H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 5/00 - Details of television systems
  • H04N 5/14 - Picture signal circuitry for video frequency region
  • H04N 5/44 - Receiver circuitry

45.

Adaptable encryption device and methods for use therewith

      
Application Number 13591404
Grant Number 08917868
Status In Force
Filing Date 2012-08-22
First Publication Date 2014-02-27
Grant Date 2014-12-23
Owner ViXS Systems, Inc. (Canada)
Inventor Ducharme, Paul D.

Abstract

A video processing device includes a data segmentation generator that receives a domain selection, n, and that segments input A/V data into n data blocks. An encryption processing device receives an encryption depth selection, k, and a range selection, m, and sequentially encrypts each of the n data blocks m times using k different keys to generate n encrypted data blocks. An output formatter generates encrypted A/V data from the n encrypted data blocks.

IPC Classes  ?

  • H04L 29/06 - Communication control; Communication processing characterised by a protocol

46.

Motion adaptive deinterlacer and methods for use therewith

      
Application Number 13595255
Grant Number 08681270
Status In Force
Filing Date 2012-08-27
First Publication Date 2014-01-30
Grant Date 2014-03-25
Owner ViXS Systems, Inc. (Canada)
Inventor Zhou, Hui

Abstract

A device for use in conjunction with a video processing device includes a deinterlacer that selectively interpolates a plurality of pictures into a plurality of selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the deinterlace motion data for a picture of the plurality of pictures. The deinterlace motion data is generated based on instantaneous deinterlace motion data generated by comparing an amount of motion for individual pixels of the picture of the plurality of pictures to a motion detection threshold, and also based on historic motion data that considers motion for at least three adjacent pictures of the plurality of pictures having the same odd/even polarity.

IPC Classes  ?

  • H04N 7/01 - Conversion of standards
  • H04N 11/20 - Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards

47.

Motion adaptive filter and deinterlacer and methods for use therewith

      
Application Number 13595243
Grant Number 08629937
Status In Force
Filing Date 2012-08-27
First Publication Date 2014-01-14
Grant Date 2014-01-14
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Zhou, Hui

Abstract

A device for use in conjunction with a video processing device includes an adaptive filter for processing input pictures into selectively filtered pictures, based on a filter motion data. A deinterlacer selectively interpolates the selectively filtered pictures into selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the filter motion data and the deinterlace motion data, based on detecting motion in the input pictures.

IPC Classes  ?

  • H04N 11/20 - Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards

48.

Detection of video feature based on variance metric

      
Application Number 13450870
Grant Number 09071842
Status In Force
Filing Date 2012-04-19
First Publication Date 2013-10-24
Grant Date 2015-06-30
Owner VIXS Systems Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang

Abstract

A metric representing the sum of variances for pixel blocks of a region of an image are used to identify the presence a video feature of the image, and a transcoding is performed responsive to identifying the presence of the video feature. The identified video feature can include, but is not limited to, a scene change, the presence of a black border region or a caption region, or the complexity of the image. The transcoding operation can include, but is not limited to, coding the image as an Intra-frame, omitting the content corresponding to the black border region or the caption region from the transcoded image or allocating a relatively lower bit budget for the black border region or a relatively higher bit budget to the caption region during transcoding of the image, or setting the bit budget for rate control during transcoding.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/115 - Selection of the code volume for a coding unit prior to coding
  • H04N 19/114 - Adapting the group of pictures [GOP] structure, e.g. number of B-frames between two anchor frames
  • H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/142 - Detection of scene cut or scene change
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object

49.

Video processing system with text recognition and methods for use therewith

      
Application Number 13467630
Grant Number 09600725
Status In Force
Filing Date 2012-05-09
First Publication Date 2013-10-24
Grant Date 2017-03-21
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang (wilf)

Abstract

A system for processing a video signal into a processed video signal includes a pattern recognition module for detecting a region of text in the image sequence based on coding feedback data and generating pattern recognition data in response thereto. A video codec generates the processed video signal and generates the coding feedback data in conjunction with the processing of the image sequence.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
  • G05B 15/02 - Systems controlled by a computer electric

50.

Video processing system with video to text description generation, search system and methods for use therewith

      
Application Number 13467691
Grant Number 09317751
Status In Force
Filing Date 2012-05-09
First Publication Date 2013-10-24
Grant Date 2016-04-19
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang (wilf)

Abstract

A system for searching at least one video signal based on an input text string includes a video processing system that processes the at least one video signal by decoding the at least one video signal, encoding the at least one video signal or transcoding the at least one video signal. The video processing system generates a plurality of text strings that describe the video signal in conjunction with the processing. A memory stores a searchable index that includes the plurality of text strings. A search module identifies at least one matching video of the at least one video signal by comparing the input text string to the plurality of text strings of the searchable index.

IPC Classes  ?

  • H04N 19/103 - Selection of coding mode or of prediction mode
  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object

51.

Configurable transcoder and methods for use therewith

      
Application Number 13454798
Grant Number 09106921
Status In Force
Filing Date 2012-04-24
First Publication Date 2013-10-24
Grant Date 2015-08-11
Owner VIXS Systems, INC (Canada)
Inventor Wang, Yimin (jim)

Abstract

A transcoder includes a demultiplexer that demultiplexes a video signal into a video stream, an audio stream and a subtitle stream. A stream probe generates stream format identification data based on the video signal. A transcoder configuration module generates hardware/software configuration data based on the stream format identification data. The hardware/software configuration data configures a plurality of hardware transcoders and the processing device to operate to generate a transcoded video stream, a transcoded audio stream and processed subtitle stream via selected hardware and software blocks. A remultiplexer generates the processed video signal by remultiplexing the transcoded video stream, the transcoded audio stream and the processed subtitle stream, based on the hardware/software configuration data.

IPC Classes  ?

  • H04N 7/58 -
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 21/222 - Secondary servers, e.g. proxy server or cable television Head-end
  • H04N 21/2365 - Multiplexing of several video streams
  • H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/136 - Incoming video signal characteristics or properties

52.

Video processing system with face detection and methods for use therewith

      
Application Number 13467600
Grant Number 08655030
Status In Force
Filing Date 2012-05-09
First Publication Date 2013-10-24
Grant Date 2014-02-18
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Li, Ying
  • Zhao, Xu Gang (wilf)

Abstract

A system for processing a video signal into a processed video signal includes a pattern recognition module for detecting a face in the image sequence, based on coding feedback data, and generating pattern recognition data in response thereto, wherein the pattern recognition data indicates the pattern of interest. A video codec generates the processed video signal and generates the coding feedback data in conjunction with the processing of the image sequence.

IPC Classes  ?

  • G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image

53.

Video codec with shared interpolation filter and method for use therewith

      
Application Number 13858518
Grant Number 09407911
Status In Force
Filing Date 2013-04-08
First Publication Date 2013-08-29
Grant Date 2016-08-02
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Hong, Edward
  • Mittal, Neil

Abstract

A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The video processing device utilizes an interpolation filter to perform an encoding function in the encoding mode and to perform a decoding function in a decoding mode.

IPC Classes  ?

  • H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
  • H04N 19/51 - Motion estimation or motion compensation
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream

54.

Transcoder with dynamic audio channel changing

      
Application Number 13291796
Grant Number 09183842
Status In Force
Filing Date 2011-11-08
First Publication Date 2013-05-09
Grant Date 2015-11-10
Owner VIXS Systems Inc. (Canada)
Inventor
  • Ip, Kent
  • Lo, Kenny

Abstract

A transcoder is arranged to transcode a stream having a dynamically changing audio configuration, such as a changing number of audio channels. The transcoder can receive an input stream whereby changes in the content associated with the input stream causes corresponding changes to the configuration of audio data encoded in the input stream. The transcoder is arranged to detect the change in audio configuration and, in response, to dynamically reconfigure its decoder and encoder modules to continue to transcode the audio data after the audio configuration change.

IPC Classes  ?

  • G10L 21/00 - Speech or voice signal processing techniques to produce another audible or non-audible signal, e.g. visual or tactile, in order to modify its quality or its intelligibility
  • G10L 19/16 - Vocoder architecture
  • G10L 19/008 - Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing

55.

Dynamic transmitter calibration

      
Application Number 13228547
Grant Number 09655069
Status In Force
Filing Date 2011-09-09
First Publication Date 2013-03-14
Grant Date 2017-05-16
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Kelton, James Robert
  • Cave, Michael David

Abstract

A method includes generating an indicator of interference introduced by a transmitter into a spectrum of an output transmit signal outside a target channel of the transmitter. The indicator is generated based on the output transmit signal. The method includes adjusting a power level of the output transmit signal based on the indicator and a predetermined interference indicator level. The indicator may indicate a carrier-to-interference (C/I) ratio of the output transmit signal, and the adjusting comprises setting the power level of the output transmit signal to a maximum power level that maintains the C/I ratio of the output transmit signal above the predetermined interference indicator level. The output transmit signal may be based on a radio-frequency output of a power amplifier of the transmitter prior to transmission over a channel and the generating comprises generating a baseband version of the output transmit signal.

IPC Classes  ?

  • H04W 52/52 - Transmission power control [TPC] using AGC [Automatic Gain Control] circuits or amplifiers
  • H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets

56.

Stereoscopic video transcoder and methods for use therewith

      
Application Number 13178372
Grant Number 08872894
Status In Force
Filing Date 2011-07-07
First Publication Date 2013-01-10
Grant Date 2014-10-28
Owner ViXS Systems, Inc. (Canada)
Inventor Pomeroy, John

Abstract

A video transcoder includes a deformatting module that generates a deformatted video signal based on a video signal in a source stereoscopic video format, and further based on device data that corresponds to a particular target device. A scaling module generates a scaled video signal, based on the deformatted video signal and further based on the device data. A formatting module generates a reformatted video signal in accordance with a target video format, based on the scaled video signal and further based on the device data.

IPC Classes  ?

  • H04N 13/00 - Stereoscopic video systemsMulti-view video systemsDetails thereof

57.

Video decoder with multi-format vector processor and methods for use therewith

      
Application Number 13162265
Grant Number 09503741
Status In Force
Filing Date 2011-06-16
First Publication Date 2012-12-13
Grant Date 2016-11-22
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Yang, Kai
  • Liu, Dong
  • Hong, Edward
  • Wang, Hongri (grace)

Abstract

A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability

58.

Adaptive edge enhancement

      
Application Number 13117328
Grant Number 08761537
Status In Force
Filing Date 2011-05-27
First Publication Date 2012-11-29
Grant Date 2014-06-24
Owner ViXS Systems, Inc. (Canada)
Inventor Wallace, Bradley Arthur

Abstract

In at least one embodiment of the invention, an apparatus for adaptive edge enhancement of a video signal includes a transient improvement module. The transient improvement module is configured to generate a first adjusted pixel value based on a window of pixel values for pixels surrounding a pixel-of-interest initially having an input pixel value. The apparatus includes an adaptive peaking module configured to generate a second adjusted pixel value based on the first adjusted pixel value and the input pixel value. In at least one embodiment of the apparatus, the adaptive peaking module comprises a high-pass filter configured to generate a pixel adjustment based on the first adjusted pixel value. In at least one embodiment of the apparatus, the adaptive peaking module further comprises a gain path configured to apply at least one adaptive gain value to the pixel adjustment to generate an adaptive adjustment value.

IPC Classes  ?

59.

Video decoder with vector processor and methods for use therewith

      
Application Number 13101357
Grant Number 08971416
Status In Force
Filing Date 2011-05-05
First Publication Date 2012-11-08
Grant Date 2015-03-03
Owner VIXS Systems, Inc (Canada)
Inventor
  • Yang, Kai
  • Liu, Dong
  • Hong, Edward
  • Wang, Hongri (grace)

Abstract

A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores format configuration data corresponding to a plurality of video coding formats. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a vector function module that generates vector function data based on a vector function of a first input vector and a second input vector. A selection module selects each element of a vector output as one of: a corresponding element of the vector function data, and a corresponding element of a third input vector.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream

60.

Multi-format video decoder with vector processing instructions and methods for use therewith

      
Application Number 13076554
Grant Number 08743967
Status In Force
Filing Date 2011-03-31
First Publication Date 2012-09-13
Grant Date 2014-06-03
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Laksono, Indra
  • Yang, Kai
  • Wang, Hongri
  • Liu, Dong
  • Zhao, Xu Gang (wilf)
  • Young, Eric
  • Hong, Edward

Abstract

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 7/50 - involving transform and predictive coding

61.

Multi-format video decoder with filter vector processing and methods for use therewith

      
Application Number 13076568
Grant Number 09088793
Status In Force
Filing Date 2011-03-31
First Publication Date 2012-09-13
Grant Date 2015-07-21
Owner VIXS Systems, INC. (Canada)
Inventor
  • Hong, Edward
  • Liu, Dong
  • Wang, Hongri
  • Yang, Kai
  • Laksono, Indra
  • Young, Eric
  • Zhao, Xu Gang

Abstract

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units includes at least one filter vector processor that operates in conjunction with a plurality of programmable filter parameters.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 19/103 - Selection of coding mode or of prediction mode
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
  • H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
  • H04N 19/136 - Incoming video signal characteristics or properties

62.

Video decoder with shared memory and methods for use therewith

      
Application Number 13170255
Grant Number 09025666
Status In Force
Filing Date 2011-06-28
First Publication Date 2012-09-06
Grant Date 2015-05-05
Owner Vixs Systems, Inc. (Canada)
Inventor
  • Wang, Limin (bob)
  • Yang, Yinxia (michael)

Abstract

A video decoder includes an entropy decoding device that includes a first processor that generates first entropy decoded (EDC) data from a first portion of an encoded video signal and further that generates second EDC data from a second portion of the encoded video signal. A general video decoding device includes a second processor that generates a first portion of a decoded video signal from the first EDC data and that further generates a second portion of the decoded video signal from the second EDC data. A shared memory includes at least one buffer that is accessed by the general video decoding device via absolute memory addressing.

IPC Classes  ?

  • H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission
  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
  • H04N 19/187 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

63.

Video decoder with pipeline processing and methods for use therewith

      
Application Number 13041680
Grant Number 09247261
Status In Force
Filing Date 2011-03-07
First Publication Date 2012-09-06
Grant Date 2016-01-26
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Wang, Limin (bob)
  • Wang, Zhong Yan (jason)

Abstract

A video decoder includes an entropy decoding device that includes a first processor that generates first entropy decoded (EDC) data from a first portion of an encoded video signal and further that generates second EDC data from a second portion of the encoded video signal. A general video decoding device includes a second processor that generates a first portion of a decoded video signal from the first EDC data and that further generates a second portion of the decoded video signal from the second EDC data. The entropy decoding device and the general video decoding device operate contemporaneously in a pipelined process where the general video decoding device generates the first portion of the decoded video signal during at least a portion of time that the entropy decoding device generates the second EDC data from the first portion of the encoded video signal.

IPC Classes  ?

  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
  • H04N 19/187 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

64.

Video decoder with general video decoding device and methods for use therewith

      
Application Number 13041767
Grant Number 09025660
Status In Force
Filing Date 2011-03-07
First Publication Date 2012-09-06
Grant Date 2015-05-05
Owner Vixs Systems, Inc. (Canada)
Inventor
  • Wang, Limin (bob)
  • Wang, Zhong Yan (jason)
  • Yang, Yinxia (michael)
  • Guo, Xin (cindy)
  • Zhang, Xiangiun (maggie)

Abstract

A video decoder includes an entropy decoding device that includes a first processor that generates entropy decoded (EDC) data from an encoded video signal. A general video decoding device includes a second processor that generates a decoded video signal from the EDC data, wherein the general video decoding device includes: a neighbor management module, a decode motion compensation module, an inverse intra-prediction module, an inverse transform/quantization module, and a deblocking filter module.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
  • G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image
  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 11/04 - Colour television systems using pulse code modulation
  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/117 - Filters, e.g. for pre-processing or post-processing
  • H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
  • H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

65.

Video decoder with slice dependency decoding and methods for use therewith

      
Application Number 13042115
Grant Number 08848804
Status In Force
Filing Date 2011-03-07
First Publication Date 2012-09-06
Grant Date 2014-09-30
Owner VIXS Systems, Inc (Canada)
Inventor
  • Wang, Limin (bob)
  • Yang, Yinxia (michael)

Abstract

A video decoder includes an entropy decoding device that includes a first processor that generates entropy decoded (EDC) data from an encoded video signal, wherein the encoded video signal includes a plurality of video layers, wherein the entropy decoding device includes a slice dependency module that generates slice dependency data and wherein the first processor entropy decodes a selected subset of the plurality of video layers, based on the slice dependency data. A general video decoding device includes a second processor that generates a decoded video signal from the EDC data.

IPC Classes  ?

  • H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission
  • H04N 19/187 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
  • H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
  • H04N 11/02 - Colour television systems with bandwidth reduction

66.

Multi-pass video encoder and methods for use therewith

      
Application Number 13034392
Grant Number 09271005
Status In Force
Filing Date 2011-02-24
First Publication Date 2012-08-30
Grant Date 2016-02-23
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Daub, Sally Jean
  • Li, Xinghai (billy)
  • Li, Ying
  • Zhao, Xu Gang (wilf)

Abstract

A multi-pass video encoder includes a video encoding module that encodes a video signal based on an initial configuration data set to generate an initial processed video signal and an initial output data set. An application coding control module generates the initial configuration data set and generates a first updated configuration data set based on both the initial processed video signal and the initial output data set. The video encoding module further encodes the video signal based on the first updated configuration data set to generate a first updated processed video signal and a first updated output data set.

IPC Classes  ?

  • H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N 19/192 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding the adaptation method, adaptation tool or adaptation type being iterative or recursive
  • H04N 19/115 - Selection of the code volume for a coding unit prior to coding
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/56 - Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
  • H04N 19/523 - Motion estimation or motion compensation with sub-pixel accuracy
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream

67.

Stereoscopic video processing with separable 2D filter

      
Application Number 13034576
Grant Number 09282314
Status In Force
Filing Date 2011-02-24
First Publication Date 2012-08-30
Grant Date 2016-03-08
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Pan, Feng
  • Liu, Yang

Abstract

A two-dimensional filter operates in accordance with a three-dimensional television signal having a basic layer, a reference processing unit layer and an enhancement layer. The two-dimensional filter generates a processed base layer reference picture from a base layer reference picture via a one-dimensional horizontal filter that horizontally filters the base layer reference picture to generate a first filtered base layer reference picture and a one-dimensional vertical filter, coupled to, but separable from, the one-dimensional horizontal filter, that vertically filters the first filtered base layer reference picture to generate a pre-processed base layer reference picture.

IPC Classes  ?

  • H04N 13/00 - Stereoscopic video systemsMulti-view video systemsDetails thereof
  • H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
  • H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
  • H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

68.

Dynamic video data compression

      
Application Number 12981708
Grant Number 08781000
Status In Force
Filing Date 2010-12-30
First Publication Date 2012-07-05
Grant Date 2014-07-15
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Girardeau, Jr., James Ward
  • Gupta, Rajat

Abstract

A method includes decompressing first compressed video data to provide uncompressed video data in a first order. The method includes compressing the uncompressed video data to provide second compressed video data in a second order. The decompressing and compressing are based on first and second compression rates, respectively. The first order may be based on fundamental blocks of a frame of video data and the second order is based on lines of the frame of video data. The compressing may include alternating compression of partial portions of a first line of uncompressed video data with compression of partial portions of at least a second line of uncompressed video data to thereby generate a first line of compressed video data corresponding to the first line of uncompressed video data and at least a second line of compressed video data corresponding to the second line of uncompressed video data.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 7/50 - involving transform and predictive coding
  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)

69.

Video codec with shared interpolation filter and method for use therewith

      
Application Number 13404705
Grant Number 08437400
Status In Force
Filing Date 2012-02-24
First Publication Date 2012-06-21
Grant Date 2013-05-07
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Hong, Edward
  • Mittal, Neil

Abstract

A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The video processing device utilizes an interpolation filter to perform an encoding function in the encoding mode and to perform a decoding function in a decoding mode.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

70.

Multi-function encoder and decoder devices, and methods thereof

      
Application Number 12965109
Grant Number 08854382
Status In Force
Filing Date 2010-12-10
First Publication Date 2012-06-14
Grant Date 2014-10-07
Owner VIXS Systems, Inc. (Canada)
Inventor
  • Hong, Edward
  • Wang, Hongri
  • Liu, Dong
  • Yang, Kai
  • Laksono, Indra
  • Young, Eric
  • Zhao, Xu Gang

Abstract

A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

IPC Classes  ?

  • G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

71.

Method and apparatus for distributing video on demand loading

      
Application Number 09907114
Grant Number 08166510
Status In Force
Filing Date 2001-07-17
First Publication Date 2012-04-24
Grant Date 2012-04-24
Owner ViXS Systems, Inc. (Canada)
Inventor Ducharme, Paul

Abstract

nd RAID such that processing of multiple requests for the same video program is distributed throughout the video on demand system.

IPC Classes  ?

  • H04N 7/173 - Analogue secrecy systemsAnalogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal

72.

Processing system with register arbitration and methods for use therewith

      
Application Number 12907223
Grant Number 08811497
Status In Force
Filing Date 2010-10-19
First Publication Date 2012-04-19
Grant Date 2014-08-19
Owner VIXS Systems, Inc (Canada)
Inventor Stewart, Norman Vernon Douglas

Abstract

A processing system includes a memory module that includes a register space for storing a plurality of register data in a plurality of registers and secure access data corresponding to the register space. A register arbitration module operates to receive a request to access one of the registers from a client module; retrieve secure access data corresponding to the client to determine if the client is trusted; and to grant the request to access the register if the client is trusted. If the client is not trusted, the register arbitration module retrieves secure access data to determine if the register is non-secured for the client. The register arbitration module grants the request to access the register when the register is non-secured for the client.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)

73.

DRAM memory controller with built-in self test and methods for use therewith

      
Application Number 12868648
Grant Number 08438432
Status In Force
Filing Date 2010-08-25
First Publication Date 2012-03-01
Grant Date 2013-05-07
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Gupta, Rajat
  • Yeh, Chun-Chin

Abstract

An integrated circuit is interfaced with at least one dynamic random access memory (DRAM) via a memory interface. A plurality of user test options are received. The testing of the memory interface is controlled in accordance with the plurality of user test options. Test data, generated as a result of the testing of the memory interface, is stored.

IPC Classes  ?

74.

Audio equalizer and methods for use therewith

      
Application Number 12868617
Grant Number 09124233
Status In Force
Filing Date 2010-08-25
First Publication Date 2012-03-01
Grant Date 2015-09-01
Owner VIXS Systems, INC (Canada)
Inventor Zeng, Hong

Abstract

An audio equalizer includes an equalization processor that operates in conjunction with a transformed-based audio decoder that generates a decoded audio signal from an encoded audio signal. The equalization processor receives an equalization input signal, generates a plurality of response coefficients in response to the equalization input and applies the response coefficients to partially decoded data of the transformed-based audio decoder.

IPC Classes  ?

  • H03G 5/00 - Tone control or bandwidth control in amplifiers
  • H03G 9/02 - Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers
  • H03G 9/00 - Combinations of two or more types of control, e.g. gain control and tone control

75.

Video encoding system with region detection and adaptive encoding tools and method for use therewith

      
Application Number 12840144
Grant Number 08917765
Status In Force
Filing Date 2010-07-20
First Publication Date 2012-01-26
Grant Date 2014-12-23
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Liu, Yang
  • Pan, Feng

Abstract

A system for encoding a video stream into a processed video signal that includes at least one image, includes a region identification signal generator for detecting a region of interest in the at least one image and generating a region identification signal when the pattern of interest is detected. An encoder section generates the processed video signal based on the operation of a plurality of encoding tools, each having at least one encoder quality parameter. The encoder section adjusts the at least one encoding quality parameter of at least one of the plurality of encoding tools in response to the region identification signal.

IPC Classes  ?

  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 19/124 - Quantisation
  • H04N 19/127 - Prioritisation of hardware or computational resources
  • H04N 19/154 - Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component

76.

Dongle device with video encoding and methods for use therewith

      
Application Number 13212970
Grant Number 09043523
Status In Force
Filing Date 2011-08-18
First Publication Date 2011-12-15
Grant Date 2015-05-26
Owner VIXS Systems, Inc. (Canada)
Inventor
  • Sahdra, Kuldip
  • Stewart, Norman
  • Huang, Shijun D.
  • Tong, Mang Lun A.
  • Leung, Lewis

Abstract

A universal serial bus (USB) dongle device includes a USB interface that receives selection data from a host device that indicates a selection of a first video format from a plurality of available formats. The USB interface also receives an input video signal from the host device in the first video format and a power signal from the host device. An encoding module generates a processed video signal in a second video format based on the input video signal, wherein the first video format differs from the second video format. The USB interface transfers the processed video signal to the host device.

IPC Classes  ?

  • H04N 21/63 - Control signaling between client, server and network componentsNetwork processes for video distribution between server and clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB'sCommunication protocolsAddressing
  • H04N 21/41 - Structure of clientStructure of client peripherals
  • H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display

77.

Enhanced histogram equalization

      
Application Number 13182801
Grant Number 08698961
Status In Force
Filing Date 2011-07-14
First Publication Date 2011-11-24
Grant Date 2014-04-15
Owner ViXS Systems, Inc. (Canada)
Inventor Astrachan, Paul M.

Abstract

A video processor includes a video stream translation module configured to generate a translated luminance value for a pixel of a current frame of a video data stream. The translated luminance value is based on a first luminance value for the pixel and a first translation matrix for the current frame of the video data stream. The video processor includes a filter configured to generate an output luminance value for the pixel based on the translated luminance value and a target translated luminance value for the pixel. The output luminance value may be based on a weighted average of the translated luminance value and the target translated luminance value using a first weighting factor. The video processor may include a first weighting factor generator configured to generate the first weighting factor based on luminance values of the current frame of the video stream.

IPC Classes  ?

  • H04N 5/42 - Transmitter circuitry for transmitting at will black-and-white or colour signals
  • G06K 9/68 - Methods or arrangements for recognition using electronic means using sequential comparisons of the image signals with a plurality of reference, e.g. addressable memory

78.

Contrast control device and method therefor

      
Application Number 12784793
Grant Number 08599318
Status In Force
Filing Date 2010-05-21
First Publication Date 2011-11-24
Grant Date 2013-12-03
Owner Vixs Systems, Inc. (Canada)
Inventor
  • Astrachan, Paul M.
  • Aardema, Chris A.

Abstract

A first video picture is translated based upon a first translation matrix to adjust a contrast of the first video image. A second translation matrix is determined based upon a first histogram of a second video picture. A third translation matrix is determined based upon the first translation matrix and the second translation matrix, and the video picture is translated based upon the third translation matrix. The translation matrix can be determined using a histogram that has been adjusted using a clipped histogram equalization technique.

IPC Classes  ?

  • H04N 5/14 - Picture signal circuitry for video frequency region
  • H04N 5/57 - Control of contrast or brightness
  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints

79.

Clock synchronization in a modular circuit emulation system

      
Application Number 12764677
Grant Number 08577666
Status In Force
Filing Date 2010-04-21
First Publication Date 2011-10-27
Grant Date 2013-11-05
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Ni, Hualiang
  • Moghaddam, Ahmad R.
  • King, Cecil E.

Abstract

A modular circuit emulation system includes a global clock generator that generates a plurality of clock signals. A plurality of emulation boards each include at least one programmable circuit and a clock buffer. The clock buffer generates at least one synchronized clock signal for clocking the programmable circuit or circuits, based on at least one of the plurality of global clock signals.

IPC Classes  ?

  • G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines

80.

Method and/or apparatus for implementing a color management module

      
Application Number 12706199
Grant Number 08553154
Status In Force
Filing Date 2010-02-16
First Publication Date 2011-08-18
Grant Date 2013-10-08
Owner VIXS Systems, Inc (Canada)
Inventor
  • Zhou, Hui
  • Aardema, Christopher A.

Abstract

An apparatus comprising a first circuit, a processing circuit and a conversion circuit. The first circuit may be configured to generate a first intermediate signal in a second format in response to an input signal in a first format. The processing circuit may be configured to generate a second intermediate signal and a third intermediate signal in response to the first intermediate signal. The conversion circuit may be configured to generate an output signal in the first format in response to the second intermediate signal and the third intermediate signal. The processing circuit may be configured to implement color blending on the second intermediate signal in the second format prior to conversion to the first format and pass the third intermediate signal without color blending.

IPC Classes  ?

  • H04N 9/64 - Circuits for processing colour signals

81.

Scaled motion search section with parallel processing and method for use therewith

      
Application Number 12642482
Grant Number 09420308
Status In Force
Filing Date 2009-12-18
First Publication Date 2011-06-23
Grant Date 2016-08-16
Owner VIXS SYSTEMS, INC. (Canada)
Inventor Young, Eric

Abstract

A scaled motion search section can be used in a video processing device that processes a video input signal that includes a plurality of pictures. The scaled motion search section includes a downscaling module that downscales the plurality of pictures to generate a plurality of downscaled pictures. A reduced-scale motion search module generates a plurality of motion vector candidates at a downscaled resolution, based on the plurality of downscaled pictures. The reduced-scale motion search module includes a column buffer that stores a column of reference data and generates the plurality of motion vector candidates based on a parallel processing of the column of reference data for a group of adjacent macroblock pairs.

IPC Classes  ?

  • H04N 19/53 - Multi-resolution motion estimationHierarchical motion estimation
  • H04N 19/533 - Motion estimation using multistep search, e.g. 2D-log search or one-at-a-time search [OTS]
  • H04N 19/56 - Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
  • H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution

82.

Adaptive edge enhancement using directional components from non-linear filtering

      
Application Number 12639353
Grant Number 08284314
Status In Force
Filing Date 2009-12-16
First Publication Date 2011-06-16
Grant Date 2012-10-09
Owner Vixs Systems, Inc. (Canada)
Inventor
  • Wallace, Bradley Arthur
  • Lynch, James Christopher

Abstract

A video processing device includes an input to receive pixel values for a set of pixels comprising a pixel window substantially centered around a select pixel that initially has a first pixel value. The video processing device further includes a first filter unit to determine a horizontal transient improvement value based on non-linear filtering of the pixel values in a horizontal direction, a second filter unit to determine a vertical transient improvement value based on non-linear filtering of the pixel values in a vertical direction, a third filter unit to determine a first diagonal transient improvement value based on non-linear filtering of the pixel values in a first diagonal direction, and a fourth filter unit to determine a second diagonal transient improvement value based on non-linear filtering of the pixel values in a second diagonal direction that is perpendicular to the first diagonal direction. The video processing device also includes an output to provide a second pixel value for the select pixel, the second pixel value based on the first pixel value, the vertical transient improvement value, the horizontal transient improvement value, the first diagonal transient improvement value, and the second diagonal transient improvement value.

IPC Classes  ?

  • H04N 5/21 - Circuitry for suppressing or minimising disturbance, e.g. moire or halo
  • H04N 5/213 - Circuitry for suppressing or minimising impulsive noise
  • G06K 9/40 - Noise filtering

83.

Pixel interpolation with edge detection based on cross-correlation

      
Application Number 12567128
Grant Number 08643777
Status In Force
Filing Date 2009-09-25
First Publication Date 2011-03-31
Grant Date 2014-02-04
Owner VIXS Systems Inc. (Canada)
Inventor
  • Wallace, Bradley Arthur
  • Girardeau, Jr., James Ward

Abstract

A pixel interpolation process is based on detection of a potential edge in proximity to a pixel being estimated, and the angle thereof. The potential edge and its angle is determined based on filtering of offset or overlapping sets of lines from a pixel window centered around the pixel being estimated and then cross-correlating the filter results. The highest value in the correlation result values represents a potential edge in proximity to the pixel being estimated and the index of the highest value represents the angle of the potential edge. This information is used in conjunction with other information from the cross-correlation and analysis of the differences between pixels in proximity to verify the validity of the potential edge. If determined to be valid, a diagonal interpolation based on the edge and its angle is used to estimate the pixel value of the pixel. Otherwise, an alternate interpolation process, such as vertical interpolation, is used to estimate the pixel value for the pixel.

IPC Classes  ?

  • H04N 7/01 - Conversion of standards
  • H04N 11/20 - Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards

84.

Adaptive partition subset selection module and method for use therewith

      
Application Number 12413055
Grant Number 08599921
Status In Force
Filing Date 2009-03-27
First Publication Date 2010-09-30
Grant Date 2013-12-03
Owner VIXS Systems, Inc (Canada)
Inventor
  • Wang, Jiao
  • Ramachandran, Avinash
  • Zhao, Wilf

Abstract

A partition subset selection module selects a subset of available partitions for a macroblock pair of the plurality of macroblock pairs, based on motion search motion vectors generated by a motion search section, and further based on a macroblock adaptive frame and field indicator. A motion refinement module generates refined motion vectors for the macroblock pair, based on the subset of available partitions for a macroblock pair.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 11/04 - Colour television systems using pulse code modulation
  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)

85.

Media source device with digital format conversion and methods for use therewith

      
Application Number 12394425
Grant Number 09282337
Status In Force
Filing Date 2009-02-27
First Publication Date 2010-09-02
Grant Date 2016-03-08
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Dong, Suiwu
  • Daub, Sally J.

Abstract

A media source device includes media files in either original source format or in alternative digital formats, based on a content descriptor indicated by a client device from a plurality of content descriptors generated to represent possible transcodings of the source format. In the alternative, a media source device can receive a client device report and subsequent request for a media file. The media source device can send the media file to the client device in a particular digital format based on whether the content descriptor corresponding to the media file is compatible or incompatible with the client device. The bit rate used to send the media file to the client device can be adjusted based on the available transmit bit rate.

IPC Classes  ?

  • G06F 13/38 - Information transfer, e.g. on bus
  • G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
  • H04N 21/235 - Processing of additional data, e.g. scrambling of additional data or processing content descriptors
  • H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
  • H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
  • H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
  • H04N 21/643 - Communication protocols
  • H04N 21/647 - Control signaling between network components and server or clientsNetwork processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load or bridging between two different networks, e.g. between IP and wireless
  • H04N 21/654 - Transmission by server directed to the client
  • H04N 21/6587 - Control parameters, e.g. trick play commands or viewpoint selection
  • H04N 21/84 - Generation or processing of descriptive data, e.g. content descriptors

86.

Edge adaptive deblocking filter and methods for use therewith

      
Application Number 12394519
Grant Number 08380001
Status In Force
Filing Date 2009-02-27
First Publication Date 2010-09-02
Grant Date 2013-02-19
Owner ViXS Systems, Inc. (Canada)
Inventor Zhou, Hui

Abstract

A video filter processes a video input signal that includes a plurality of pixels in a plurality of macroblocks. The video filter includes an edge detector that processes a selected group of the plurality of pixels to generate a edge identification signal that identifies edge pixels in the selected group, wherein the edge detector is adapted based on a quantization parameter of at least one macroblock corresponding to the selected group of the plurality of pixels. An adaptive deblocking filter is coupled to receive the video input signal and to produce a processed video signal in response thereto, the adaptive deblocking filter being adaptive based on the edge identification signal.

IPC Classes  ?

87.

Video transcoding system with drastic scene change detection and method for use therewith

      
Application Number 12261218
Grant Number 08787447
Status In Force
Filing Date 2008-10-30
First Publication Date 2010-05-06
Grant Date 2014-07-22
Owner VIXS Systems, Inc (Canada)
Inventor Ramachandran, Avinash

Abstract

A system for transcoding a video signal into a transcoded video signal includes a drastic scene change detection module that detects a drastic scene change in a sequence of images, wherein the drastic scene change indicates a change in scene complexity. A transcoder section generates the transcoded video signal, wherein, when the drastic scene change is detected, a quality parameter is adjusted in at least one of the sequence of images.

IPC Classes  ?

  • H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)

88.

Video transcoding system with quality readjustment based on high scene cost detection and method for use therewith

      
Application Number 12261204
Grant Number 09407925
Status In Force
Filing Date 2008-10-30
First Publication Date 2010-05-06
Grant Date 2016-08-02
Owner VIXS Systems, Inc. (Canada)
Inventor Ramachandran, Avinash

Abstract

A system for transcoding a video signal into a transcoded video signal, includes a high scene cost detection module that detects a high scene cost corresponding to at least one image of the video signal. An encoder section generates the transcoded video signal, wherein, when the high scene cost is detected, an enhanced quality is assigned to at least one central region.

IPC Classes  ?

  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
  • H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
  • H04N 19/124 - Quantisation
  • H04N 19/126 - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
  • H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/115 - Selection of the code volume for a coding unit prior to coding

89.

Entropy decoder with pipelined processing and methods for use therewith

      
Application Number 12172529
Grant Number 07714754
Status In Force
Filing Date 2008-07-14
First Publication Date 2010-01-14
Grant Date 2010-05-11
Owner VIXS Systems, Inc. (Canada)
Inventor Girardeau, Jr., James Ward

Abstract

An entropy decoding module includes a binary arithmetic coding module that generates a bin string by pipeline processing a bit stream, based on a clock signal and based on context model information. A binarization and context modeling module generates a stream of syntax elements and the context model information based on the bin string.

IPC Classes  ?

  • H03M 7/00 - Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits

90.

Processing system with linked-list based prefetch buffer and methods for use therewith

      
Application Number 12128596
Grant Number 08650364
Status In Force
Filing Date 2008-05-28
First Publication Date 2009-12-03
Grant Date 2014-02-11
Owner ViXS Systems, Inc. (Canada)
Inventor Zhang, Jing

Abstract

A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory. A prefetch memory interface prefetches prefetch data to a prefetch buffer, retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

91.

Method and system for transcoding video data

      
Application Number 10375166
Grant Number 07606305
Status In Force
Filing Date 2003-02-24
First Publication Date 2009-10-20
Grant Date 2009-10-20
Owner VIXS Systems, Inc. (Canada)
Inventor Rault, Patrick

Abstract

A first method of transcoding video data is disclosed that generates a motion vector for a macroblock encoded as a dual prime macro block that has a direct motion vector, and differential motion vector for its two fields respectively. Another method of transcoding includes replacing a skipped P-macroblock that has been used to backward predict a B-Frame with a P-macroblock having a motion vector of zero. Another method of transcoding includes replacing a skipped B-Macroblock with a macroblock having a motion vector from a macroblock of the same frame of the skipped B-Macroblock that is not co-located.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

92.

Hierarchical video analysis-based real-time perceptual video coding

      
Application Number 12039391
Grant Number 08780988
Status In Force
Filing Date 2008-02-28
First Publication Date 2009-09-03
Grant Date 2014-07-15
Owner VIXS Systems, Inc. (Canada)
Inventor
  • Pan, Feng
  • Leung, Lewis

Abstract

A system for encoding a video stream into a processed video signal that includes at least one image. The system includes a downscaling module, a partitioning module, a rate control module, and an encoder section. The downscaling module receives the video stream and produces a downscaled video stream. A partitioning module, including a region detection module, receives the downscaled video stream and detects a pattern of interest in the at least one image. The partitioning module is operable to partition the at least one image based on the detected pattern of interest. The rate control module that receives an output from the partitioning module and produces an encoder control signal dependent on the output from the partitioning module. The encoder section, coupled to the rate control module, receives the video stream and generates the processed video signal.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal

93.

Motion refinement engine with flexible direction processing and methods for use therewith

      
Application Number 12026505
Grant Number 09225996
Status In Force
Filing Date 2008-02-05
First Publication Date 2009-06-25
Grant Date 2015-12-29
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Ramachandran, Avinash
  • Hong, Edward
  • Qiu, Gang

Abstract

A motion refinement engine can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion refinement engine includes a motion search module, that generates at least one motion search motion vector for a macroblock of the plurality of macroblocks based on a first plurality of directions. A motion refinement module generates at least one refined motion vector for the macroblock of the plurality of macroblocks, based on a second plurality of directions, wherein the second plurality of directions differ from the first plurality of directions. In a further embodiment, motion search, motion refinement, and motion compensation are selectively performed in a single pass.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 19/577 - Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
  • H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
  • H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/51 - Motion estimation or motion compensation
  • H04N 19/149 - Data rate or code amount at the encoder output by estimating the code amount by means of a model, e.g. mathematical model or statistical model
  • H04N 19/115 - Selection of the code volume for a coding unit prior to coding
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/112 - Selection of coding mode or of prediction mode according to a given display mode, e.g. for interlaced or progressive display mode
  • H04N 19/124 - Quantisation
  • H04N 19/533 - Motion estimation using multistep search, e.g. 2D-log search or one-at-a-time search [OTS]
  • H04N 19/523 - Motion estimation or motion compensation with sub-pixel accuracy

94.

USB video card and dongle device with video encoding and methods for use therewith

      
Application Number 11950410
Grant Number 08028094
Status In Force
Filing Date 2007-12-04
First Publication Date 2009-06-04
Grant Date 2011-09-27
Owner Vixs Systems, Inc. (Canada)
Inventor
  • Sahdra, Kuldip
  • Stewart, Norman
  • Huang, Shijun D.
  • Tong, Mang Lun A.
  • Leung, Lewis

Abstract

A universal serial bus (USB) dongle device includes a USB interface for receiving a video signal in a first format and for sending a processed video signal in a second format wherein the first format differs from the second format. An encoding module generates the processed video signal based on the video signal. In a further embodiment, A video card includes a video receiver for receiving a video signal in a first format, based on a selection command. An encoding module generates a processed video signal in a second format based on the video signal, wherein the first format differs from the second format. A USB interface transfers the processed video signal to the host device, receives the selection command from the host device and receives a power signal from the host device to power the video receiver and the encoding module.

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

95.

Pattern detection module with region detection, video encoding system and method for use therewith

      
Application Number 12254586
Grant Number 09313504
Status In Force
Filing Date 2008-10-20
First Publication Date 2009-04-16
Grant Date 2016-04-12
Owner VIXS Systems, Inc. (Canada)
Inventor
  • Pan, Feng
  • Jiao, Jingyun
  • Liu, Yang

Abstract

A system for encoding a video stream into a processed video signal that includes at least one image, includes a pattern detection module for detecting a pattern of interest in the at least one image and identifying a region that contains the pattern of interest when the pattern of interest is detected, based on an analysis of the image in a plurality of domains. An encoder section, generates the processed video signal and wherein, when the pattern of interest is detected, a higher quality, such as a higher bit allocation or higher computational processing, is assigned to the region than to portions of the at least one image outside the region.

IPC Classes  ?

  • G06F 21/00 - Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • H04N 19/115 - Selection of the code volume for a coding unit prior to coding
  • H04N 19/46 - Embedding additional information in the video signal during the compression process
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
  • H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N 19/40 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream

96.

Security module for securing an encrypted signal with system and method for use therewith

      
Application Number 11864617
Grant Number 08548168
Status In Force
Filing Date 2007-09-28
First Publication Date 2009-01-22
Grant Date 2013-10-01
Owner ViXS Systems, Inc. (Canada)
Inventor Leung, Lewis

Abstract

A security module includes a signal interface for receiving an encrypted signal and a host interface that is coupleable to a host. A processing module is operable to receive encrypted decryption code from the host via the host interface, decrypt the encrypted decryption code to form decrypted decryption code that is operable to decrypt the encrypted signal, send the decrypted decryption code to the host via the host interface, monitor the security of the decrypted decryption code via security signaling sent between the host and the security module via the host interface to detect potential tampering with the decrypted decryption code, transfer the encrypted signal to the host via the host interface, and discontinue transfer of the encrypted signal when the security signaling indicates the potential tampering with the decrypted decryption code.

IPC Classes  ?

97.

Pattern detection module, video encoding system and method for use therewith

      
Application Number 11772763
Grant Number 08548049
Status In Force
Filing Date 2007-07-02
First Publication Date 2009-01-08
Grant Date 2013-10-01
Owner VIXS Systems, Inc (Canada)
Inventor
  • Pan, Feng
  • Jiao, Jingyun

Abstract

A system for encoding a video stream into a processed video signal that includes at least one image, includes a pattern detection module for detecting a pattern of interest in the at least one image and identifying a region that contains the pattern of interest when the pattern of interest is detected. An encoder section, generates the processed video signal and wherein, when the pattern of interest is detected, a higher quantization is assigned to the region than to portions of the at least one image outside the region.

IPC Classes  ?

  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 7/167 - Systems rendering the television signal unintelligible and subsequently intelligible

98.

Video processing system and device with encoding and decoding modes and method for use therewith

      
Application Number 11716773
Grant Number 08711901
Status In Force
Filing Date 2007-03-12
First Publication Date 2008-09-18
Grant Date 2014-04-29
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Young, Eric
  • Hong, Edward

Abstract

A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

IPC Classes  ?

  • H04N 11/02 - Colour television systems with bandwidth reduction

99.

Motion refinement engine with a plurality of cost calculation methods for use in video encoding and methods for use therewith

      
Application Number 11602731
Grant Number 08218636
Status In Force
Filing Date 2006-11-21
First Publication Date 2008-05-22
Grant Date 2012-07-10
Owner ViXS Systems, Inc. (Canada)
Inventor
  • Ramachandran, Avinash
  • Hong, Edward
  • Qiu, Gang

Abstract

A motion compensation module can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion compensation module includes a motion search module, that generates a motion search motion vector for a plurality of subblocks for a plurality of partitionings of a macroblock of a plurality of macroblocks based on a sum of accumulated differences (SAD) cost. A motion refinement module, when enabled, generates a refined motion vector for the plurality of subblocks for the plurality of partitionings of the macroblock of the plurality of macroblocks, based on the motion search motion vector for each of the plurality of subblocks of the macroblock of the plurality of macroblocks and based on a sum of accumulated transform differences (SATD) cost. A mode decision module operates on either SAD costs or SATD costs, based on whether the refinement module is enabled or disabled.

IPC Classes  ?

  • H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission

100.

Motion refinement engine with selectable partitionings for use in video encoding and methods for use therewith

      
Application Number 11602768
Grant Number 09794561
Status In Force
Filing Date 2006-11-21
First Publication Date 2008-05-22
Grant Date 2017-10-17
Owner VIXS SYSTEMS, INC. (Canada)
Inventor
  • Ramachandran, Avinash
  • Hong, Edward
  • Qiu, Gang

Abstract

A motion compensation module can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion compensation module includes a motion search module that generates a motion search motion vector for a plurality of subblocks for a plurality of partitionings of a macroblock of a plurality of macroblocks and generates a selected group of the plurality of partitionings based on a group selection signal. A motion refinement module—generates a refined motion vector for the plurality of subblocks for the selected group of the plurality of partitionings of the macroblock of the plurality of macroblocks, based on the motion search motion vector for each of the plurality of subblocks of the macroblock of the plurality of macroblocks.

IPC Classes  ?

  • H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission
  • H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N 11/02 - Colour television systems with bandwidth reduction
  • H04N 11/04 - Colour television systems using pulse code modulation
  • H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
  • H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/127 - Prioritisation of hardware or computational resources
  • H04N 19/53 - Multi-resolution motion estimationHierarchical motion estimation
  • H04N 19/523 - Motion estimation or motion compensation with sub-pixel accuracy
  • H04N 19/567 - Motion estimation based on rate distortion criteria
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