H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
2.
Integrated protection devices with monitoring of electrical characteristics
Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 3/18 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to reversal of direct current
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
H02H 3/42 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to product of voltage and current
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
3.
Power management application of interconnect substrates
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
6.
Coupled inductors with leakage plates, and associated systems and methods
A coupled inductor includes a ladder magnetic core, a first common leakage plate formed of a magnetic material, and N windings, where N is an integer greater than one. The ladder magnetic core includes first and second rails and N rungs, where each of the N rungs connects the first and second rails. Each of the N windings includes a respective first portion. Each of the N windings is wound around a respective one of the N rungs, and at least two of the N windings are wrapped at least partially around the first common leakage plate such that a first portion of the winding is disposed between an outer surface of the first rail and an outer surface of the first common leakage plate.
A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high- side device, a low side device, and a controller. The high- side device is coupled between the input terminal and an intermediate terminal. The high- side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low- side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.
A multiple-output DC-DC converter has a first and a second DC-DC sub-converter, each DC-DC subconverter may be a buck, boost, or buck-boost converter having a primary energy-storage inductor. Each DC-DC subconverter drives a separate output of the multiple-output converter and typically has a separate feedback control circuit for controlling output voltage and/or current. The converter has a common timing circuit to maintain a phase offset between the first and DC-DC subconverters. The primary energy storage inductors of the first and second DC-DC converter are magnetically coupled to raise an effective ripple frequency of the converter and simplify output filtering.
An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is included in an integrated electronic assembly.
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
A switching power converter includes a first and second switching device, an air core coupled inductor, and a controller. The air core coupled inductor includes a first winding electrically coupled to the first switching device and a second winding electrically coupled to the second switching device. The first and second windings are magnetically coupled. The controller is operable to cause the first and second switching devices to repeatedly switch between their conductive and non-conductive states at a frequency of at least 100 kilohertz to cause current through the first and second windings to repeatedly cycle, thereby providing power to an output port. The switching power converter may have a topology including, but not limited to, a buck converter topology, a boost converter topology, and a buck-boost converter topology.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
13.
Low profile inductors for high density circuit boards
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
15.
MAXIMUM POWER POINT CONTROLLER TRANSISTOR DRIVING CIRCUITRY AND ASSOCIATED METHODS
An electric power system includes a string of N maximum power point tracking (MPPT) controllers having output ports electrically coupled in series, where N is an integer greater than one. At least one of the N MPPT controllers includes respective transistor driver circuitry powered from a power supply rail of an adjacent one of the N MPPT controllers of the string. Another MPPT controller includes an n- channel field effect freewheeling transistor electrically coupled across an output port and a resistive device electrically coupled between an input port and a gate of the freewheeling transistor, such that the freewheeling transistor operates in its conductive state when power is applied to the input port and a control subsystem of the controller is in an inactive state.
A scalable maximum power point tracking (MPPT) controller includes an input and an output port, a switching circuit adapted to transfer power from the input port to the output port, and a controller core. The controller core is adapted to (a) control the switching circuit to maximize an amount of power extracted from a photovoltaic device electrically coupled to the input port, and (b) set one or more parameters of the MPPT controller based at least in part on a configuration code representing a number of photovoltaic cells of the photovoltaic device electrically coupled in series.
A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non- conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a voltage across the input port, based at least in part on a signal representing current flowing out of the output port, to maximize a signal representing power out of the output port.
A method for operating a maximum power point tracking (MPPT) controller including a switching circuit adapted to transfer power between an input port and an output port includes the steps of: (a) in a first operating mode of the MPPT controller, causing a first switching device of the switching circuit to operate at a fixed duty cycle; and (b) in a second operating mode of the MPPT controller, causing a control switching device of the switching circuit to repeatedly switch between its conductive and non-conductive states to maximize an amount of power extracted from a photovoltaic device electrically coupled to the input port.
A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.
A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.
Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, systems, and processes for controlling a voltage regulator in response to information from a load. In some implementations, transient minimizer circuitry is coupled to receive a notification signal indicating a change or an anticipated change in an electrical characteristic of the load. The transient minimizer circuitry is configured to generate a state command signal responsive to the notification signal. The state command signal indicates a state of the voltage regulator. The switching control circuitry is coupled to receive the state command signal from the transient minimizer circuitry. The switching control circuitry is configured to operate switch circuitry to control the state of the voltage regulator in accordance with the state command signal.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.
A control system for regulating an output voltage of a DC-DC converter having N phases, where N is an integer greater than one, includes a pulse generator and a frequency divider. The pulse generator generates a stream of fixed on-time pulses, each pulse triggered in response to current through an alternating one of the N phases falling to a threshold value. The frequency divider divides the stream of fixed on-time pulses into N phase signals for controlling the N phases. A method for regulating an output voltage of a DC-DC converter having N phases, includes the following steps: (1) generating a stream of fixed on-time pulses, each pulse triggered in response to current through an alternating one of the N phases falling to a threshold value, and (2) dividing the stream of fixed on-time pulses into N phase signals for controlling the N phases.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
24.
Virtual output voltage sensing for feed-forward control of a voltage regulator
Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, systems, and methods for virtual output voltage sensing for feed-forward control of a voltage regulator. A buffer has an input coupled to sense a monitored signal indicating a duty cycle of switch circuitry coupled to an output filter of the voltage regulator. The buffer is configured to provide at an output, responsive to the monitored signal, a buffer output signal having a high reference voltage for a high side on time and a low reference voltage for a low side on time of the switch circuitry. A filter is coupled to receive and filter the buffer output signal to provide a feed-forward signal indicating the output voltage of the voltage regulator. Control circuitry is configured to control the switching of the switch circuitry responsive to the feed-forward signal.
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
25.
SYSTEMS AND METHODS FOR INTELLIGENT, ADAPTIVE MANAGEMENT OF ENERGY STORAGE PACKS
Systems and methods for intelligent, adaptive management of energy storage packs are disclosed. A method comprises receiving a first current measurement of a first energy storage cell electrically connected to a first converter circuit. The first converter circuit controls the charge and discharge of the first energy storage cell. A first voltage measurement of the first energy storage cell is received. A first temperature measurement of the first energy storage cell is received. The first current measurement, the first voltage measurement, and the first temperature measurement are translated into a state of charge of the first energy storage cell.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
26.
DC to DC converter designed to mitigate problems associated with low duty cycle operation
DC to DC converters are described that include two converters interconnected and operated to mitigate at least some of the effects of low duty cycle operation.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G05F 1/70 - Regulating power factorRegulating reactive current or power
27.
INTEGRATED PHOTOVOLTAIC PANEL WITH SECTIONAL MAXIMUM POWER POINT TRACKING
An integrated photovoltaic panel has one or more integral DC-DC converter circuits. The DC-DC converter input port couples to a section of at least one photovoltaic (PV) device of the panel separate from PV devices feeding other converters. The converter has an MPPT controller for operating the converter to transfer maximum power from coupled photovoltaic devices to its output port. The PV panel has a transparent substrate to which PV devices are mounted. A laminating material seals PV devices and converters to the substrate. In embodiments, the panel has multiple converters connected with output ports in series. The integrated PV panel provides summed maximum powers of each section of PV devices. In some embodiments the DC-DC converters are complete with inductors, in other embodiments a common inductor is shared by multiple converters of the panel, in a particular embodiment the common inductor is parasitic inductance of the panel.
A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
31.
Asymmetrical coupled inductors and associated methods
An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.
H02M 3/10 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
32.
POWER MANAGEMENT APPLICATIONS OF INTERCONNECT SUBSTRATES
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
A voltage regulator is operated by determining whether a desired output current is below a threshold, and when the desired output current is below the threshold, generating a sequence of current pulses in a discontinuous current mode. A maximum current of the pulses is a function of the desired output current.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.
An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.
The present application features a transistor that includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench has a first side and an opposing second side, and extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth in the n-well region, wherein each of the second depth and the third depth is greater than the first depth. The transistor further includes a source region and a drain region. The source region is on the first side of the trench and includes a p-body region extending from the surface to the first region, an n+ region and a p+ region implanted in the p-body region. The drain region is on the second side of the trench and includes an n+ region.
A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.
An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.
H01F 3/10 - Composite arrangements of magnetic circuits
H01F 30/06 - Fixed transformers not covered by group characterised by the structure
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
H01H 35/00 - Switches operated by change of a physical condition
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
H02H 3/18 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to reversal of direct current
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
H02H 3/42 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to product of voltage and current
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
41.
INTEGRATED PROTECTION DEVICES WITH MONITORING OF ELECTRICAL CHARACTERISTICS
Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
42.
LOW PROFILE INDUCTORS FOR HIGH DENSITY CIRCUIT BOARDS
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding fauns a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An electric power system includes N electric power sources and N switching circuits, where N in an integer greater than one. Each switching circuit includes an input port electrically coupled to a respective one of the N electric power sources, an output port, and a first switching device adapted to switch between its conductive and non-conductive states to transfer power from the input port to the output port. The output ports of the N switching circuits are electrically coupled in series and to a load to establish an output circuit. Each of the N switching circuits uses an interconnection inductance of the output circuit as a primary energy storage inductance of the switching circuit.
H01F 27/42 - Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors or choke coils
48.
SYSTEM, METHOD, MODULE, AND ENERGY EXCHANGER FOR OPTIMIZING OUTPUT OF SERIES-CONNECTED PHOTOVOLTAIC AND ELECTROCHEMICAL DEVICES
An energy transfer device for solar power systems operates to draw power from high-producing photovoltaic devices and apply that power across low-producing photovoltaic devices. An embodiment is a self-regulating energy exchanger using bidirectional DC-DC converters that operates to maintain uniform voltage across each series-connected photovoltaic device. An alternative embodiment is an energy exchanger that is controlled to maintain each of several series-connected photovoltaic devices at a maximum power point by drawing power from high-performing devices and applying that power across low-performing devices to provide uniform current among series-connected photovoltaic devices.
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
H02M 3/28 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
H01L 31/042 - PV modules or arrays of single PV cells
49.
SWITCHING CIRCUITS FOR EXTRACTING POWER FROM AN ELECTRIC POWER SOURCE AND ASSOCIATED METHODS
An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
H02M 3/28 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
H01L 31/042 - PV modules or arrays of single PV cells
50.
SWITCHING CIRCUITS FOR EXTRACTING POWER FROM AN ELECTRIC POWER SOURCE AND ASSOCIATED METHODS
A switching circuit for extracting power from an electric power source includes (1) an input port for electrically coupling to the electric power source, (2) an output port for electrically coupling to a load, (3) a first switching device configured to switch between its conductive state and its non-conductive state to transfer power from the input port to the output port, (4) an intermediate switching node that transitions between at least two different voltage levels at least in part due to the first switching device switching between its conductive state and its non-conductive state, and (5) a controller for controlling the first switching device to maximize an average value of a voltage at the intermediate switching node.
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
H02M 3/28 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
H01L 31/042 - PV modules or arrays of single PV cells
51.
Switching circuits for extracting power from an electric power source and associated methods
A switching circuit for extracting power from an electric power source includes (1) an input port for electrically coupling to the electric power source, (2) an output port for electrically coupling to a load, (3) a first switching device configured to switch between its conductive state and its non-conductive state to transfer power from the input port to the output port, (4) an intermediate switching node that transitions between at least two different voltage levels at least in part due to the first switching device switching between its conductive state and its non-conductive state, and (5) a controller for controlling the first switching device to maximize an average value of a voltage at the intermediate switching node.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
52.
Switching circuits for extracting power from an electric power source and associated methods
An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.
H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
53.
SWITCHING CIRCUITS FOR EXTRACTING POWER FROM AN ELECTRIC POWER SOURCE AND ASSOCIATED METHODS
An electric power system includes N electric power sources and N switching circuits, where N in an integer greater than one. Each switching circuit includes an input port electrically coupled to a respective one of the N electric power sources, an output port, and a first switching device adapted to switch between its conductive and non- conductive states to transfer power from the input port to the output port. The output ports of the N switching circuits are electrically coupled in series and to a load to establish an output circuit. Each of the N switching circuits uses an interconnection inductance of the output circuit as a primary energy storage inductance of the switching circuit.
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
H02M 3/28 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
H01L 31/042 - PV modules or arrays of single PV cells
54.
Current report in current mode switching regulation
A voltage regulator includes a switch configured to alternately couple and decouple a voltage source through a inductor to a load, a feedback circuitry configured to generate a feedback current proportional to a difference between a desired voltage and an output voltage at an output terminal, a current sensor configured to measure the feedback current, a controller configured to receive the feedback current level from the current sensor and, in response thereto, to control a duty cycle of the switch, and a current mirror configured to generate a reporting current proportional to the feedback current.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
55.
Sensing and feedback with enhanced stability in a current mode control voltage regulator
The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. An adjustment device is coupled to sense a current sensing voltage corresponding to a current provided to the output filter. The adjustment device is configured to convert the current sensing voltage to an adjusted current sensing voltage, including replacing a current sensing resistance associated with the current sensing voltage with a reference resistance. Control circuitry includes a current sensing input coupled to the adjustment device to sense the adjusted current sensing voltage, and an output in communication with the power switch input. The control circuitry is configured to cause a transition of the power switch from the second conduction period to the first conduction period responsive to the adjusted current sensing voltage.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.
The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a comparator mechanism triggers a transition in a power switch when the error in the regulated output voltage is equal to a proportionally scaled value of current provided at an output filter. The voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. A comparator mechanism has a reference input coupled to a reference voltage, a feedback input coupled to sense a feedback voltage at the output filter, a current sensing input coupled to sense a current sensing voltage corresponding to a current provided to the output filter, and an output in communication with the power switch input. The comparator mechanism is configured to trigger responsive to a difference between the feedback voltage and the reference voltage equaling the current sensing voltage. The triggering causes a transition of the power switch from the second conduction period to the first conduction period.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
58.
Controlled delivery of a charging current to a boost capacitor of a voltage regulator
Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling a power switch of a voltage regulator. A capacitor is coupled to an output of the power switch. Charge delivery circuitry is coupled to the capacitor and configured to provide a charging current to the capacitor. Charge control circuitry can be coupled to the charge delivery circuitry and configured to selectively allow the providing of the charging current to the capacitor.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling the switching frequency of a voltage regulator. Frequency monitoring and adjustment circuitry is coupled to sense a switching frequency of a power switch coupled to an output filter of the voltage regulator. The frequency monitoring and adjustment circuitry is configured to provide a frequency adjustment signal based on the sensed switching frequency. Power switch control circuitry is coupled to receive the frequency adjustment signal and is configured to control switching of the power switch based on the frequency adjustment signal.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively.
A multi-phase coupled inductor includes a powder core material magnetic core and first, second, third, and fourth terminals. The coupled inductor further includes a first winding at least partially embedded in the core and a second winding at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially physically separated from the first winding within the magnetic core. The multi-phase coupled inductor is, for example, used in a power supply.
Two-phase coupled inductors including a magnetic core, at least a first winding, and at least three solder tabs. Power supplies including a printed circuit board, a two-phase coupled inductor affixed to the printed circuit board, and first and second switching circuits affixed to the printed circuit board. Each of the first and second switching circuits are electrically coupled to a respective solder tab of the two-phase coupled inductor affixed to the printed circuit board.
A multiphase DC-to-DC power converter has two or more sets of input switches, each set of input switches driving primary windings of at least one associated transformer. Each transformer has one or two secondary windings, the secondary windings feeding power through output switches or rectifiers through an associated output inductor into a common filter. At least two of the output inductors are magnetically coupled.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
64.
Powder core material coupled inductors and associated methods
A multi-phase coupled inductor includes a powder core material magnetic core and first, second, third, and fourth terminals. The coupled inductor further includes a first winding at least partially embedded in the core and a second winding at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially physically separated from the first winding within the magnetic core. The multi-phase coupled inductor is, for example, used in a power supply.
A multi-phase coupled inductor includes a magnetic core formed of a powder magnetic material and first, second, third, and fourth terminals. The coupled inductor further includes a first winding forming at least one turn and at least partially embedded in the core and a second winding forming at least one turn and at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially physically separated from the first winding within the magnetic core. The multi-phase coupled inductor is, for example, used in a power supply.
H01F 17/04 - Fixed inductances of the signal type with magnetic core
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.
A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted into the substrate, and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness of less than about 100A, and the second side having a thickness equal to or greater than 125A.
A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.
A method of making a transistor is disclosed. The method starts with applying a first photoresist and performing a first etching of the first side of a gate where the gate includes an oxide layer formed over a substrate and a conductive material formed over the oxide layer. The first etching is followed by implanting an impurity region into the substrate while using the first photoresist and the conductive material as a mask making the implantation of the impurity region self-aligned to the gate. The implantation is followed by applying a second photoresist and performing a second etching of the second side of the gate.
A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut.
A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain region comprising a n+ region, and a gate between the source region and the drain region. The p-body region includes a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity. The second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration. The p+ region and n+ region abut the second implant region.
A voltage regulator has a switch configured to alternately couple and decouple a voltage source through an inductor to a load, feedback circuitry to generate a feedback current, a current sensor configured to measure the feedback current, and a controller configured to receive the feedback current measurement from the current sensor and, in response thereto, to control a duty cycle of the switch. The feedback circuitry includes an amplifier having a first input configured to receive a desired voltage, a second input, and an output, a capacitor connecting the second input to the output of the amplifier, and a resistor connecting the output of the amplifier and the output terminal such that a feedback current proportional to a difference between the desired voltage and an output voltage at an output terminal flows through the resistor.
G05F 1/613 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in parallel with the load as final control devices
73.
Flip chip power switch with under bump metallization stack
A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.
An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.
An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.
[0116] A multi- winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.
A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.
Two-phase coupled inductors including a magnetic core, at least a first winding, and at least three solder tabs. Power supplies including a printed circuit board, a two-phase coupled inductor affixed to the printed circuit board, and first and second switching circuits affixed to the printed circuit board. Each of the first and second switching circuits are electrically coupled to a respective solder tab of the two-phase coupled inductor affixed to the printed circuit board.
A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An M-winding coupled inductor (800) includes a first end magnetic element (802), a second end magnetic element (804), M connecting magnetic elements (902), and M windings (904). M is an integer greater than one. Each connecting magnetic element (902) is disposed between and connects the first (802) and second (804) end magnetic elements. Each winding (904) is wound at least partially around a respective one of the M connecting magnetic elements (902). The coupled inductor further includes at least one top magnetic element (806) adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.
H01F 3/10 - Composite arrangements of magnetic circuits
H01F 30/06 - Fixed transformers not covered by group characterised by the structure
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
82.
Coupled inductor with improved leakage inductance control
An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements, and each winding has a respective leakage inductance. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The top magnetic element forms a gap. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.
An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An inductor includes a core (1514) formed of a magnetic material and a foil winding (1506) wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue (1604) configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab (1504). At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor (1508, 1510) attached to the core. The core does not form a magnetic path loop around the ground return conductor.
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
87.
Method and apparatus for multi-phase DC-DC converters using coupled inductors in discontinuous conduction mode
A multi-phase, coupled-inductor, DC-DC voltage converter operates in discontinuous conduction mode (DCM) when the system is operated at low output power demand. An embodiment of the converter switches to operating in continuous conduction mode (CCM) when the system is operated at high output power demand. Operation in single-drive and rotating phase DCM operation at low power are described. An alternative embodiment operates in a multiple-drive, rotating-phase, discontinuous conduction mode during at least one condition of output power demand.
G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
88.
Systems and methods for scalable configurations of intelligent energy storage packs
A system and method for scalable configuration of intelligent energy storage packs are disclosed. According to one embodiment, a method comprises providing a first current measurement of a first energy storage cell electrically connected to a first converter circuit, and the first converter circuit controls the charge and discharge of the first energy storage cell. A first voltage measurement of the first energy storage cell is provided. First control signals are received and the first control signals are determined according to a load policy. The first converter circuit transforms a first voltage from the first energy storage cell to a desired first bus contribution voltage according to the first control signals.
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit. During each switching period of the switching circuit, the current for the slave is checked; namely, after the beginning of a low-side conduction period, and before the beginning of a high-side conduction period.
A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.
A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method of fabricating a semiconductor device is provided that includes forming an LDMOS transistor having a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source on the substrate. The method also includes forming an n-type CMOS transistor having a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source. In so doing, the LDMOS transistor can be fabricated through a process that can be seamlessly integrated into a sub-micron CMOS process.
An M-phase coupled inductor including a magnetic core and M windings, where M is an integer greater than one. The magnetic core is formed of a core material, and the magnetic core includes a first outer leg forming a first gap. The first gap includes a first gap material having lower magnetic permeability than the core material. Each winding is wound at least partially around at least a portion of the magnetic core, and each winding has a respective leakage inductance. The first gap causes the leakage inductances to be greater than if the first outer leg did not form the first gap. The coupled inductor may be used in a power supply, and the power supply may be used in a computing apparatus.
Single phase inductors have non-linear inductance values, and M-phase coupled inductors having non-linear leakage inductance values. Each inductor includes, for example, at least one of the following: a saturable magnetic element, a gap of non-uniform thickness, a core formed of a distributed gap material, or a non-homogeneous core. A DC-to-DC converter includes an inductor having a non-linear inductance value, a switching subsystem, and an output filer. Another DC-to-DC converter includes an output filter, a coupled inductor having non-linear leakage inductance values, and switching subsystems.
An M-phase coupled inductor including a magnetic core and M windings, where M is an integer greater than one. The magnetic core is formed of a core material, and the magnetic core includes a first outer leg forming a first gap. The first gap includes a first gap material having lower magnetic permeability than the core material. Each winding is wound at least partially around at least a portion of the magnetic core, and each winding has a respective leakage inductance. The first gap causes the leakage inductances to be greater than if the first outer leg did not form the first gap. The coupled inductor may be used in a power supply, and the power supply may be used in a computing apparatus.
Single phase inductors have non-linear inductance values, and M-phase coupled inductors having non-linear leakage inductance values. Each inductor includes at least one of the following: a saturable magnetic element, a gap of non-uniform thickness, a core formed of a distributed gap material, or a non- homogeneous core. A DC-to-DC converter includes an inductor having a non-linear inductance value, a switching subsystem, and an output filer. Another DC-to-DC converter includes an output filter, a coupled inductor having non-linear leakage inductance values, and switching subsystems.
A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and the master controller and each slave can communicate using a ring communication scheme. A command generated by the master controller can be passed from the master controller to the subsequent slaves.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
