Abstract

A method for reducing wafer edge defects is provided. The method includes providing a wafer with a central region and an edge region, forming a hard mask layer on the wafer, forming a spacer pattern on the hard mask layer, forming a photoresist layer covering the spacer pattern, performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern, using the annular photoresist pattern as an etching mask, and sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of trenches in the wafer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/3105 - After-treatment

Abstract

A memory apparatus, comprising: a command decoder, generating an external refresh command; a refresh skip divider, coupled to the command decoder, catching the external refresh command and outputting a divider signal; a row hammer circuit, generating a row hammer signal; and a refresh control circuit, coupled to the command decoder, the refresh skip divider and the row hammer circuit, wherein the refresh control circuit receives the external refresh command, the divider signal and the row hammer signal, and the refresh control circuit generates an internal refresh command according to the external refresh command, the divider signal and the row hammer signal.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles

Abstract

A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

IPC Classes  ?

• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
• G11C 11/4076 - Timing circuits
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
• H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Abstract

The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X−1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/30 - Monitoring
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

A method for forming a packaging structure is provided. The method includes providing a first substrate and a second substrate. The first substrate includes a first base material and a first dielectric layer on the first base material, and the second substrate includes a second base material and a second dielectric layer on the second base material. The second base material has a first through hole. The first dielectric layer and the second dielectric layer have a first hole and a second hole, respectively. The method further includes connecting the second substrate to the first substrate in such a way that the second dielectric layer is connected to the first dielectric layer to form a first composite structure; thinning the top surface of the first composite structure to expose the first through hole; and forming a first conductive member in the first through hole.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor memory device includes a plurality of nanowires vertically stacked over a substrate, and a plurality of memory films wrapping around the plurality of nanowires, respectively. Each of the memory films includes a first oxide layer, a nitride layer and a second oxide layer sequentially formed over the corresponding nanowire. The semiconductor memory device also includes a gate electrode layer surrounding the plurality of memory films, and an isolation structure encapsulating the gate electrode layer. The isolation structure is in direct contact with the gate electrode layer and the nitride layers of the memory films.

IPC Classes  ?

• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.

IPC Classes  ?

• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

An electronic device and a control method for memory refresh operation thereof are provided. The electronic device includes a memory and a controller. The memory includes a plurality of timers, a plurality of buffers and an interrupt signal generator. Each of the buffers is configured to store at least one word line information, and generate a refresh word line information according to a timing result trigger signal of each corresponding timer. The interrupt signal generator generates an interrupt signal corresponding to an auto refresh operation according to the timing result trigger signal, a non-internal self-refresh mode signal and a non-accessing status. The controller receives the interrupt signal and transmits an auto refresh command to the memory according to the interrupt signal to enable the memory to perform the auto refresh operation.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/4076 - Timing circuits

Abstract

An operating method of a semiconductor device including a NOR type flash memory and a NAND type flash memory is improved. A flash memory includes a NOR type flash memory, a NAND type flash memory, a controller, and an internal bus connecting the NOR type flash memory and the NAND type flash memory to the controller. The controller controls the NOR type flash memory, or the NOR type flash memory and the NAND type flash memory based on a command received from an outside.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

In an aspect, the disclosure is directed to a cell erase method which includes not limited to: initiating an erase operation of a block of memory cells by applying an erase condition to the block of memory cells; performing a first erase verification procedure for at least a portion of the block of memory cells in comparison with a first erase verify voltage; adjusting the first erase verify voltage in response the portion of the block of memory cells having passed the first erase verification procedure; performing a second erase verification procedure for the block of memory cells in comparison with the adjusted erase verify voltage; performing a post program verification procedure for the block of memory cells in comparison with a post program verify voltage to detect leakage current of the block of memory cells; determining whether the adjusted erase verify voltage reaches a final erase verify voltage.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A 3-dimensional (3D) integrated circuit (IC) is provided. The 3D IC includes a plurality of chips, at least one through silicon via (TSV) structure, and a temperature sensor. The chips are stacked in the 3D IC. The TSV structure penetrates the chips. The temperature sensor is disposed in a first chip of the chips. The temperature sensor is disposed close to the TSV structure, and is configure to sense a temperature sensing result corresponding to a temperature of the TSV structure.

IPC Classes  ?

• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A dynamic memory and a control method for power down scheme are provided. The control method includes: receiving a power down command at a first time point; judging whether the first time point is in an operation period of a burst refresh operation; if the first time point is not in the operation period of the burst refresh operation: calculating a time difference between the first time point and a time point of a next refresh operation according to a second time point of a previous refresh operation and a refresh operation time interval, and determining whether to activate a low power operation mode of the dynamic memory according to the time difference.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
• G11C 11/408 - Address circuits

Abstract

A voltage generating circuit includes a first comparator, a boost circuit, a second comparator and an output circuit. The first comparator compares a first reference voltage with a first feedback voltage generated based on a first output node, and generates a first control signal accordingly. The boost circuit is controlled by the first control signal to output a boost voltage to the first output node. The second comparator compares a second reference voltage with a second feedback voltage generated based on a second output node, and generates a second control signal accordingly. The output circuit receives the boost voltage, and is controlled by the second control signal to convert the boost voltage 10 into a drive voltage and output it to the second output node. The boost voltage is determined by the first reference voltage, the drive voltage is determined by the second reference voltage.

IPC Classes  ?

• G11C 16/30 - Power supply circuits
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

A standby current detection circuit includes multiple first transistors. The first transistors are coupled in series to form a first detection circuit string, where N is a positive integer. The first detection circuit string is disposed on a scribe lane of a wafer, and the first detection circuit string is operated in a standby state and serves as a test medium for a standby current.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a floating gate, a dielectric stack, a control gate, and a protective layer. The substrate includes an active region and a peripheral region. The floating gate is disposed on the substrate. The dielectric stack is disposed on the floating gate. The control gate is disposed on the dielectric stack. The protective layer is disposed on the control gate. The protective layer located in the active region has a stepped portion.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A semiconductor structure includes a substrate and a target pattern. The target pattern is disposed on the substrate. The top-view pattern of the target pattern includes a main portion and a protruding portion. The main portion and the protruding portion are connected with each other along the long axis of the top-view pattern of the target pattern. The protruding portion is connected to the main portion. The protruding portion includes a first portion located on one side of the long axis. The maximum width of the first portion perpendicular to the long axis is less than half of the maximum width of the main portion.

IPC Classes  ?

• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

A method of manufacturing a memory device includes providing a substrate, forming a stack layer on the substrate, and forming a hard mask layer on the stack layer. The hard mask layer has a protrusion. The method includes forming a patterned mandrel on the hard mask layer, the patterned mandrel includes a first mandrel disposed adjacent to the protrusion, a second mandrel disposed on the top surface of the protrusion, and a third mandrel. The method further includes using the patterned mandrel as a mask, the hard mask layer and the stack layer are sequentially patterned to form a dummy structure and a word line structure on the substrate. The portion of the stack layer corresponding to the first and second mandrels is formed as the dummy structure. The portion of the stack layer corresponding to the third mandrel is formed as the word line structure.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A semiconductor structure including the following components is provided. Stack structures are located on a substrate and separated from each other. Isolation layers are located on the sidewalls of the stack structures. A contact is located on the substrate between two adjacent isolation layers. A landing pad is located on the contact. The landing pad is located on one of the two adjacent isolation layers. There is an opening on one side of the landing pad. A first dielectric layer is located in the opening. A porous dielectric layer is located between the first dielectric layer and the landing pad. The top surface of the porous dielectric layer is lower than the top surface of the landing pad and the top surface of the first dielectric layer to form a recess between the landing pad and the first dielectric layer. The recess exposes the sidewall of the landing pad.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer on the substrate; isolation structures extending through the dielectric layer into the substrate; and a floating gate on the dielectric layer and between the isolation structures, wherein the floating gate includes a first portion directly on the dielectric layer; and second portions on the sidewalls of the first portion.

IPC Classes  ?

• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/762 - Dielectric regions

Abstract

A current sensing circuit including a differential sensing amplifier and a pre-charging circuit is provided. The differential sensing amplifier includes a first input end, a second input end and a output end. The first input end is coupled to a selected cell via a first data line. The second input end is coupled to a reference cell via a second data line. The output end outputs a sensing data of the selected cell. The pre-charging circuit is coupled to the differential sensing amplifier. The pre-charging circuit is configured to provide a pre-charging circuit and perform a pre-charging operation on the first data line. The first data line has a cell current and the pre-charging circuit. The second data line has a reference current. The pre-charging circuit is determined according to the reference current.

IPC Classes  ?

• G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
• H03F 3/45 - Differential amplifiers

Abstract

A semiconductor memory device and control method thereof are provided, repairing defective bit lines even if the number of defective bit lines exceeds that of a spare bit line in any subarray in multiple subarrays. The semiconductor memory device includes a memory cell array having multiple subarrays, and a controller, configured to activate the word line and a corresponding word line in a second subarray which is separately arranged from the first subarray in a column direction when activating any word line in a first subarray of the plurality of subarrays. The controller is further configured to access the memory cells connected to the activated word line in the second subarray instead of the memory cells connected to the activated word line in the first subarray when a first condition (i.e., the number of defective bit lines exceeds the number of spare bit lines in the first subarray) is met.

IPC Classes  ?

• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A yield evaluation method and a yield evaluation apparatus are provided. The method is described below. Wafer manufacturing data, front-end wafer test data, and back-end product yield information in a manufacturing process of a semiconductor product is collected and multiple parameters related to a yield are selected. A relative information entropy of a defective product in multiple samples manufactured using each of the parameters relative to a global constant probability defective product is calculated to establish a product entropy calculator. The global constant probability defective product represents the defective product whose yield does not vary with the parameters. The wafer manufacturing data and the front-end wafer test data of the current product are collected and substituted into the product entropy calculator to evaluate the yield of the current product.

IPC Classes  ?

• G01R 31/26 - Testing of individual semiconductor devices

Abstract

A semiconductor device includes: a substrate; a source region and a drain region disposed in the substrate; a shallow trench isolation (STI) region disposed in the substrate and surrounding the source region and the drain region; a plurality of through substrate vias (TSV) through the substrate, wherein the plurality of through substrate vias are adjacent to the shallow trench isolation region; and a compound semiconductor structure isolating the shallow trench isolation region from the plurality of through substrate vias. The plurality of through substrate vias have a first stress type, and the compound semiconductor structure has a second stress type different from the first stress type.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A method for manufacturing a semiconductor structure including performing a first etching process on the substrate to form a first trench, and conformally forming a conformal layer on the surface of the first trench. The method further includes performing a second etching process on the substrate along the first trench to form a second trench below the first trench, wherein in the second etching process, the conformal layer has greater etch resistance than the substrate such that the top width of the second trench is greater than the bottom width of the first trench.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor memory device includes an error bit detection unit and a bit counting unit. The error bit detection unit detects whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and outputs the error bit data indicating pass/error information. The pass/error information indicates whether each detected bit is consistent. The bit counting unit counts the number of error bits in the error bit data indicating an inconsistency between the read data and the expected data, or counts the number of pass bits in the error bit data indicating consistency between the read data and the expected data. Furthermore, the semiconductor memory device also includes an interface for a read operation to input external expected values and an interface for the read operation interfaces to output the number of error bits or pass bits instead of the read data.

IPC Classes  ?

• G11C 29/08 - Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor

Abstract

A semiconductor device is capable of improving calculating ability and processing efficiency in AI learning and the like. A flash memory (100) includes a NAND-type or NOR-type memory cell array (110) and a calculation processing part (190). The calculation processing part (190) includes a bit line current detection part (200); a voltage holding part (210) holding a voltage corresponding to the detected current; an adding part (220) adding voltages held by the voltage holding part (210); and an A/D conversion part (230) performing A/D conversion on an addition result of the adding part (220). The calculation processing part (190) may calculate a sum of the current flowing in a bit line in a row direction and/or a column direction when the memory cell array is read.

IPC Classes  ?

• G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron

Abstract

A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits

Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes: active regions, defined in a semiconductor substrate; word line structures, formed on the semiconductor substrate, and intersected with the active regions, wherein each of the word line structures includes a floating gate and a control gate stacked on the floating gate; first protection layers, respectively covering an upper part of the control gate in one of the word line structures, wherein a bottom end of the control gate in each word line structure is lower than a bottom end of each first protection layer; and a second protection layer, covering the first protection layers, and wrapping the word line structures.

IPC Classes  ?

• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Abstract

A semiconductor memory device and a writing method thereof. The semiconductor memory device includes a memory control circuit and a memory array. The memory array includes a target memory bank. The target memory bank includes a target memory cell and a sense amplifier circuit. The sense amplifier circuit is coupled to the target memory cell via a bit line, receives a data signal within a first voltage value range from the memory control circuit, and generates a bit line signal within a second voltage value range on the bit line according to the data signal. The second voltage value range is greater than the first voltage value range.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4094 - Bit-line management or control circuits

Abstract

A delay locked loop includes a delay line, a phase detector, a controller, an output clock generator, and a feedback circuit. The delay line receives an input clock signal and a control code, and generates a delayed clock signal by delaying the input clock signal according to the control code. The phase detector receives a reference clock signal and a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal to generate phase comparison information. The controller generates the control code and a switching signal according to the phase comparison information. The output clock generator selects the delayed clock signal or an inverted signal of the delayed clock signal according to the switching signal to generate an output clock signal. The feedback circuit generates the feedback clock signal according to the output clock signal.

IPC Classes  ?

• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
• G11C 19/00 - Digital stores in which the information is moved stepwise, e.g. shift registers
• H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Abstract

The present invention provides an initial setting device of semiconductor memory, which includes a voltage detection part, a first non-volatile memory device, a control unit, and a determination unit. The voltage detection part detects the voltage of the power supply. The first non-volatile memory device stores the first setting information, which is used for setting the operation condition of the semiconductor memory. The control unit reads the first setting information from the first non-volatile memory device according to the voltage level of the detected power supply. The determination unit determines whether first setting information that was read is valid. The reading condition of the first setting information is changed and the first setting information is read simultaneously every time the first setting information is determined as invalid until the first setting information is determined as valid.

IPC Classes  ?

• G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting

Abstract

A method of forming a semiconductor structure includes providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region. A patterned floating gate layer is formed on the array region and the peripheral region, and a stacked layer is conformally formed on the substrate, wherein a recess is formed over the transition region. A photoresist layer is formed on the substrate, and the photoresist layer is patterned to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, and a recess pattern is formed. The array region pattern and the recess pattern are sequentially transferred to the stacked layer, the patterned floating gate layer and the substrate to form a plurality of arrays and a pair of blocking structures.

IPC Classes  ?

• H10B 41/42 - Simultaneous manufacture of periphery and memory cells
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region

Abstract

A semiconductor memory device is provided and includes at least one sense amplifier and a control unit. The at least one sense amplifier includes a pair of first transistors and a pair of second transistors. The control unit provides voltages that are adjusted based on characteristics of the pair of first transistors and the pair of second transistors of each sense amplifier of the at least one sense amplifier to the pair of first transistors and the pair of the second transistors of each sense amplifier of the at least one sense amplifier so that voltages of a pair of bit lines connected to each sense amplifier of the at least one sense amplifier are close to a specific target voltage during an offset elimination operation.

IPC Classes  ?

• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first source/drain region and a second source/drain region disposed within the substrate, and a gate structure disposed on the substrate and between the first source/drain region and the second source/drain region. The semiconductor device further includes an interlayer dielectric layer disposed over the first source/drain region, the second source/drain region, and the gate structure. The interlayer dielectric layer includes a second trench extending into the second source/drain region. The semiconductor device further includes a dielectric layer disposed in the second trench, and a second source/drain contact disposed over the second source/drain region and filling the remaining portion of the second trench.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A semiconductor device includes: a substrate; a source region disposed on the substrate; a drain region disposed on the source region; and a floating main body region disposed between the source region and the drain region. The floating main body region vertically separates the source region from the drain region. The semiconductor device further includes: a gate region laterally wrapped around the floating main body region; and a gate dielectric located between the floating main body region and the gate region, and insulated the floating main body region from the gate region. A material of the gate dielectric has a negative capacitance feature.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A physical unclonable function (PUF) code generating apparatus includes a PUF code generating element and a PUF code storage element. The PUF code generating element is configured to generate a PUF code. The PUF code storage element is coupled to the PUF code generating element. The PUF code storage element is configured to receive and store the PUF code. The PUF code generating element includes multiple first memory cells. Each of the first memory cells includes a gate layer, a semiconductor layer, and a tunnel oxide layer. The tunnel oxide layer is located between the gate layer and the semiconductor layer. The tunnel oxide layer includes a central area and a peripheral area. A ratio of a minimum thickness of the peripheral area to a maximum thickness of the central area of the tunnel oxide layer is defined as a corner ratio, and the corner ratio is less than 0.99.

IPC Classes  ?

• H04L 9/08 - Key distribution

Abstract

A semiconductor memory device includes a plurality of word lines, a bit line, a memory cell array, a sense amplifier, and an adjustment unit. The memory cell array includes a plurality of memory cells, wherein each of the plurality of memory cells is connected to one of the plurality of word lines and the bit line. The sense amplifier is connected to the bit line. The adjustment unit counts the number of erroneously-read memory cells whose read values are different from an expected value during a data reading operation of the memory cell while changes a parameter related to a condition of a sensing operation of the sense amplifier. The adjustment unit adjusts a value of the parameter so that the number of erroneously-read memory cells is the minimum.

IPC Classes  ?

• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

Abstract

A semiconductor device, including a semiconductor substrate; an isolation feature on the semiconductor substrate; a plurality of strip-shaped active regions defined by the isolation feature, wherein a column position of an edge of each of the strip-shaped active regions in one row is laterally shifted by a shift distance relative to a column position of a respective edge of each of the strip-shaped active regions in an adjacent row, and the shift distance is one to two times a width of the strip-shaped active regions; and capacitor contacts on both ends of each of the strip-shaped active regions.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure includes a central region and a periphery region. The periphery region surrounds the central region. The semiconductor structure includes a target layer pattern formed in the central region, and a dummy pattern formed in the periphery region, and the target layer pattern and the dummy pattern are formed by the target layer. The dummy pattern includes a first portion and a second portion. The extending direction of the second portion is different from the extending direction of each of the target layer patterns, and the first portion and the second portion extend in different directions. The second portion of one of the dummy patterns is connected to one of the target layer patterns or the first portion.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

In an aspect, the disclosure is directed to an electrical circuit which includes not limited to: a first bonding pad having a bias voltage, a voltage pull-up circuit configured to set the bias voltage of the first bonding pad to a high voltage, a voltage pull-down circuit configured to switch bias voltage of the first bonding pad from the high voltage to a low voltage in response to the voltage pull-down circuit receiving a first control signal which activates the voltage-pull down circuit, a rise time delay control circuit configured to control a rise time of the bias voltage of the first bonding pad, wherein the bias voltage of the first bonding pad starts to rise in response to the first control signal deactivating the voltage pull-down circuit, and a driving circuit configured to drive a second control signal to activate the driving circuit.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• G11C 16/30 - Power supply circuits
• G11C 16/32 - Timing circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A memory device and its manufacturing method are provided. Memory cells of the memory device arranged in an array respectively include an access transistor and a storage capacitor connected to the access transistor through a capacitor contact (CC) structure. Based on a specific arrangement manner, the CC structures are closely arranged in pairs. Each pair of the CC structures are connected to a neighboring access transistor and isolated from each other through an isolation wall. Each isolation wall includes an inner wall and outer walls located on opposite sides of the inner wall. The inner wall has sufficient etch selectivity with respect to the outer walls. Despite etchants or reactive substances inevitably consume the outer walls during manufacturing, the etchants or the reactive substances may be blocked by the inner wall without penetrating the entire isolation wall. Therefore, an electrical isolation between the neighboring CC structures may be guaranteed.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method for forming semiconductor structures is provided. The method includes forming a first patterning photoresist layer having a first opening on a first patterning layer, trimming the first patterning photoresist layer, transferring the first pattern of the trimmed first patterning photoresist layer to the first patterning layer, performing a first pattern reversal process to reverse the first pattern of the first patterning layer into the second opening, forming a second patterning layer in and on the second opening, forming a second patterning photoresist layer having a third opening on the second patterning layer, transferring the second pattern of the second patterning photoresist layer to a first stacking layer, performing a second pattern reversal process to reverse a third pattern between the second opening and the third opening into a fourth opening, and extending the fourth opening to the substrate.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/8234 - MIS technology

Abstract

A memory structure includes a substrate structure and a memory cell disposed on the substrate structure. The memory cell includes device layers stacked on the substrate structure, a word line, a first contact, and a second contact. The device layer includes a semiconductor layer, a first doped region, a second doped region, a channel region located between the first doped region and the second doped region, and a capacitor. The first and second doped regions and the channel region are disposed in the semiconductor layer. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first and second electrode layers. The word line is disposed on a sidewall of the channel layer. The first contact is electrically connected to the first doped regions. The second contact is electrically connected to the second electrode layers. A manufacturing method thereof is provided.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure includes a substrate, an insulating layer formed on the substrate, and a plurality of pairs of linear structures arranged in parallel and formed in the insulating layer, wherein each pair of linear structures has a first linear structure and a second linear structure. There is a first space S1 between an end portion of the first linear structure and an end portion of the second linear structure, there is a second space S2 between a center portion of the first linear structure and a center portion of the second linear structure, and the second space S2 is greater than the first space S1.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

Disclosed is a memory chip including a plurality of first power pads and a first bus. The first bus is connected to the first power pads. One of the first power pads is coupled to the first bus via a switch device. A data width of the memory chip is determined according to a conduction state of the switch device.

IPC Classes  ?

• G11C 29/54 - Arrangements for designing test circuits, e.g. design for test [DFT] tools
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• G11C 5/14 - Power supply arrangements

Abstract

Disclosed are a method and an apparatus for memory testing. The method comprises following steps: using a test program group including N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and executing a neural network operation on the N test data to estimate a yield of M dies passing the test program group.

IPC Classes  ?

• G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor

Abstract

A testing device and a testing method thereof. The testing device includes a controller and a data storage device. The controller receives multiple command sequences respectively sent by application platforms through an input interface. The data storage device stores multiple circuit information corresponding to each of the application platforms and each of the command sequences corresponding to each of the application platforms. The controller, during a test period, is connected to at least one device under test through an output interface. The controller executes a test operation on the at least one device under test according to each of the circuit information corresponding to each of the application platforms and each of the command sequences corresponding to each of the application platforms.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/319 - Tester hardware, i.e. output processing circuits

Abstract

The method of forming the semiconductor device includes the following steps. An isolation structure is formed between a plurality of active areas. Semiconductor structures are formed over the active areas, and a portion of each semiconductor structure is embedded in the isolation structure. Sacrificial structures are formed on the semiconductor structures. An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure. The sacrificial structures are removed to form patterned semiconductor structures. A dielectric structure is formed on the patterned semiconductor structure. A control structure is formed on the dielectric structure.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/762 - Dielectric regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A sense amplifier capable of performing a logical NOT operation is provided, which includes a sense circuit, configured to sense a first voltage of a bit line and a second voltage of an inverse bit line; a first transistor, coupled between a first terminal of the sense circuit and the bit line; a second transistor, coupled between a second terminal of the sense circuit and the inverse bit line; and a third transistor, coupled between the bit line and the inverse bit line. First and second memory cells are respectively controlled by first and second word lines, and connected to the bit line. When the sense amplifier is in an inverse writing state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. A first logical state of the first voltage is complementary to a second logical state of the second voltage.

IPC Classes  ?

• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

An inspection method for inspecting a semiconductor structure is provided. The semiconductor structure includes a first conductive line, a second conductive line, a first conductive line contact and first transistors connected to the first conductive line, and second transistors connected to the second conductive line, wherein each of the first transistors includes a first contact and each of the second transistors includes a second contact. The inspection method includes a pre-charge operation, irradiating the first conductive line contact with an electron beam; an imaging operation, obtaining an image of the semiconductor structure; and a determination operation, which determines whether the second contact of any one of the second transistors becomes bright in the image. In response to the second contact of the any one of the second transistors becoming bright, the determination operation determines that there is a defect between the first conductive line and the second conductive line.

IPC Classes  ?

• H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
• G06T 7/00 - Image analysis
• H01J 37/22 - Optical or photographic arrangements associated with the tube
• H01J 37/28 - Electron or ion microscopesElectron- or ion-diffraction tubes with scanning beams

Abstract

A semiconductor structure includes a substrate, several buried word lines in the substrate, a dielectric material layer on the substrate, a semiconductor material layer on the dielectric material layer, and several contacts disposed on the substrate. The substrate includes several active regions and isolation structures that surround the active regions. The contacts are adjacent to the semiconductor material layer, and penetrate the semiconductor material layer, the dielectric material layer and parts of the substrate. The contacts are positioned in the respective active regions.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A photomask structure includes a plurality of first layout patterns, a plurality of second layout patterns, and a ring-shaped layout pattern. The first layout patterns and the second layout patterns are alternately arranged. Each of the first layout patterns has a first end and a second end. Each of the second layout patterns has a third end and a fourth end. The first end is adjacent to the third end. The second end is adjacent to the fourth end. The ring-shaped layout pattern surrounds the first layout patterns and the second layout patterns. The first end is connected to the ring-shaped layout pattern. The second end is not connected to the ring-shaped layout pattern. The third end is not connected to the ring-shaped layout pattern. The fourth end is connected to the ring-shaped layout pattern.

IPC Classes  ?

• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• G03F 1/44 - Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
• H01L 21/311 - Etching the insulating layers

Abstract

A memory device capable of performing in-memory computing is provided and includes a memory cell array, a sense amplifier, a voltage control circuit, and a word line decoding circuit. The memory cell array includes memory cells arranged in a two-dimensional array. The memory cells on each row of the memory cell array are connected to a corresponding word line, and the memory cells on each column of the memory cell array are connected to a corresponding bit line. The sense amplifier detects a voltage level of the activated bit line and a voltage level of an inverse bit line corresponding to the bit line. The voltage control circuit selects a detection voltage provided to the sense amplifier according to a control signal from a memory controller. The word line decoding circuit activates a first word line and a second word line according to the control signal.

IPC Classes  ?

• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

Provided is a dynamic random access memory including: a plurality of word line structures, a plurality of bit line structures, a plurality of node contacts, and a plurality of spacers. The plurality of word line structures are located in a substrate. The plurality of bit line structures are located above the substrate and span the plurality of word line structures. Each of the plurality of node contacts is located between two adjacent word structures and two adjacent bit line structures. The plurality of spacers are located on a plurality of sidewalls of the plurality of node contacts. Top portions and bottom portions of two spacers of two adjacent node contacts are connected to each other to form a plurality of first air gaps.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The invention introduces a semiconductor memory device having a capability of adjusting slew rate of data voltage signals generated by output buffers having different PVT characteristics based on ZQ calibration signal. The semiconductor memory device includes a memory, a calibration counter, a slew rate (SR) control circuit and an output buffer. The calibration counter receives a ZQ calibration signal and generates a SR calibration signal based on the ZQ calibration signal. The memory is coupled to the SR control circuit. The SR control circuit is coupled to the output buffer and the calibration counter, and configured to receive the SR calibration signal from the calibration counter. The output buffer is configured to generate a data voltage signal according to data obtained from the memory and perform a slew rate control on the data voltage signal based on the SR calibration signal.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

A semiconductor structure is provided. The semiconductor structure includes a pad layer, a first conductive layer, a second conductive layer, an interlayer dielectric layer, and a control gate. The pad layer is disposed on a substrate. The first conductive layer is disposed on the pad layer. The second conductive layer is disposed on the first conductive layer. The interlayer dielectric layer is disposed on the first conductive layer and the second conductive layer and is in contact with top surfaces of the first conductive layer and the second conductive layer. The control gate is disposed on the interlayer dielectric layer.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate

Abstract

A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A material layer is formed on the substrate. A first hard mask pattern is formed on the material layer. The top-view pattern of the first hard mask pattern is ring-shaped. The first hard mask pattern has an opening. A second hard mask pattern is formed on the first hard mask pattern. The second hard mask pattern fills the opening. The top-view pattern of the second hard mask pattern is completely located inside the outer contour of the top-view pattern of the first hard mask pattern. The pattern of the first hard mask pattern and the pattern of the second hard mask pattern are transferred to the material layer to form a first target pattern.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

Abstract

A memory device includes a substrate and a plurality of word lines. The word lines are disposed on the substrate. The word lines extend in the first direction and are arranged in the second direction. The first direction intersects the second direction. The memory device further includes a first sub-select gate extending in the first direction and separated from the outermost word line in the second direction. One end of the first sub-select gate has a first width in the second direction. The major portion of the first sub-select gate has a second width in the second direction. The second width is greater than the first width.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Abstract

A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 21/311 - Etching the insulating layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

An erasing method of a memory device includes the following steps. It is determined whether a memory passes the first erasing verification operation according to the first erasing verification threshold. When the memory does not pass the first erasing verification operation, an erasing operation is performed on the memory. When the memory passes the first erasing verification operation, a flag is generated and it is determined whether the memory passes a second erasing verification operation according to the second erasing verification threshold. When the memory does not pass the second erasing verification operation, the erasing operation is performed on the memory. When the memory passes the second erasing verification operation, an over-erase correction is performed on the memory. It is determined whether there is a flag indicating that all addresses pass the first erasing verification to determine whether the memory passes the first or second erasing verification operation.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A probe tip landing method for a measurement system is provided. The probe tip landing method includes performing a first descending operation to lower a probe toward a sample by a first descending distance; performing a second descending operation to lower the probe toward the sample; and performing an inspection operation during the second descending operation. The inspection operation includes an imaging operation, scanning the sample to obtain a first image including a probe tip of the probe; and a determining operation, checking the first image to determine that in the first image, whether a region connected with the probe tip becomes bright. The probe tip landing method further includes in response to the region connected with the probe tip in the first image becoming bright, determining that the probe has contacted a surface of the sample and the probe has landed successfully.

IPC Classes  ?

• G01Q 30/02 - Non-SPM analysing devices, e.g. SEM [Scanning Electron Microscope], spectrometer or optical microscope
• G01Q 20/00 - Monitoring the movement or position of the probe

Abstract

A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 5/14 - Power supply arrangements

Abstract

A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.

IPC Classes  ?

• G11C 29/50 - Marginal testing, e.g. race, voltage or current testing

Abstract

An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

IPC Classes  ?

• G11C 16/10 - Programming or data input circuits
• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• G11C 16/24 - Bit-line control circuits
• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A method for forming a semiconductor device includes providing a substrate that has a first region and a second region adjacent to the first region; forming several first components on the substrate and in the first region, and forming a second component on the substrate and in the second region; forming a first material layer over the first components to cover the first components; and forming a patterned dummy layer that is embedded in the first material layer; forming a second material layer over the second component to cover the second component; and performing a polishing process on the first material layer and the second material layer simultaneously. The second material layer and the first material layer include different materials.

IPC Classes  ?

• H01L 21/321 - After-treatment
• H01L 21/3105 - After-treatment
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10B 41/43 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor

Abstract

An AND-type flash memory capable of achieving high integration after providing a miniaturized memory cell size includes: a plurality of diffusion regions (70) formed in a substrate in a column direction, a plurality of gates (20) formed between the opposite diffusion regions (70), a selection control line (SGD), a selection control line (SGS), and a plurality of word lines (WL0 to WLn-1). The selection control line (SGD) is connected to each gate of a bit line side selection transistor. The selection control line (SGS) is connected to each gate of a source line side selection transistor. The word lines (WL0 to WLn-1) are connected to gates of memory cells. Each of the bit line side selection transistor, the source line side selection transistor, and the plurality of memory cells has a channel area in the row direction.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/24 - Bit-line control circuits
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided is a DRAM including includes bit line stack patterns on a substrate, spacers on sidewalls of the bit line stack patterns, capacitor contacts electrically connected to active regions in the substrate, and capacitor landing pads covering the capacitor contacts, first portions of the spacers, and a portion of the bit line stack patterns. In each spacer, a second dielectric layer is located between a lower portion of a first dielectric layer and a lower portion of a third dielectric layer, and a fourth dielectric layer is located between an upper portion of the first dielectric layer and an upper portion of the third dielectric layer. Top surfaces of second portions of the plurality of spacers not covered by the plurality of capacitor landing pads are lower than top surfaces of the first portions of the plurality of spacers.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method for forming a die package structure, including disposing a plurality of dies on a carrier substrate, wherein the top surface of each die has a plurality of signal junctions. The method also includes forming a vertical wire on each of the signal junctions, forming a supporting dielectric layer on the carrier substrate, wherein the supporting dielectric layer covers the dies and exposes the top of the vertical wires, and forming a plurality of redistribution traces on the supporting dielectric layer, wherein the redistribution traces are electrically connected to each of the vertical wires. The method further includes forming a bump at the bonding site of each of the redistribution traces, and performing a cutting process to singulate the dies.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like

Abstract

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a capacitor, a patterned conductive layer and a contact. Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a capacitor, a patterned conductive layer and a contact. The substrate includes an array region and a peripheral region. A transistor is disposed in the substrate in the array region. A conductive device is disposed in the substrate in the peripheral region. The capacitor is disposed on the substrate and electrically connected to the transistor. The patterned conductive layer is disposed on the capacitor and includes a pattern portion and a connection portion connected to the pattern portion. The pattern portion is located in the array region and exposes a part of the capacitor, and the connection portion is extended into the peripheral region. The contact is disposed on the substrate in the peripheral region and connects the connection portion and the conductive device.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A memory device including a memory cell array, a signal generator, a word line decoder, a bit line decoder, a sensing amplifier circuit and a register circuit is provided. The signal generator generates a control signal according to a wrap around read command. The word line decoder, the bit line decoder, and the sensing amplifier circuit read data stored in the memory cell array according to the wrap around read command, so as to output a first wrap around read data. The register circuit is configured to latch the first wrap around read data and outputs successive wrap around read data according to the control signal and the latched first wrap around read data after the first wrap around read data is output. When the register circuit outputs the successive wrap around read data, the word line decoder, the bit line decoder, and the sensing amplifier circuit are disable.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 7/08 - Control thereof

Abstract

A flash memory that improves the reliability of data stored in a memory cell array is provided in the disclosure. A wear leveling method of the flash memory of the disclosure includes the following operation. The memory cell array includes multiple sectors, the method includes the following operation. A region is set for storing a first flag and a second flag in each sector of multiple sectors of the memory cell array. The first flag indicates whether bit correction has occurred, and the second flag indicates whether specific data is stored. The second flag of a source sector among the sectors in which the specific data is stored is set. The specific data is written to a new sector among the sectors in which the first flag is in a reset state, and the second flag of the new sector is set.

IPC Classes  ?

• G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

Abstract

A semiconductor structure is provided. The structure includes a substrate, first and second word lines, first and second storage capacitor contacts, a bit line, an insulating layer, and an inverted U-shaped isolation layer. The substrate has first and second active areas adjacent to each other, and the first and second word lines are formed in the substrate. The first and second storage capacitor contacts are respectively coupled to the first and second active areas, and disposed on the same side of the bit line. The bit line spans the first and second word lines. The insulating layer is formed between the first and second storage capacitor contacts. The inverted U-shaped isolation layer is formed in the insulating layer and spans the bit line.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method for forming a semiconductor device includes forming a capacitor contact pad in an isolation layer. The method includes forming a first dielectric layer over the isolation layer. The method includes forming a recess in the first dielectric layer over the capacitor contact pad. The method includes conformally forming a protection layer in the recess. The method includes forming a second dielectric layer over the first dielectric layer. The method includes forming a trench through the isolation layer, the first dielectric layer, the protection layer, and the second dielectric layer to expose the capacitor contact pad. The method includes laterally etching the first dielectric layer and the second dielectric layer to enlarge the trench. The method includes conformally forming the bottom electrode layer of the stacked capacitor in the enlarged trench.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An apparatus includes a memory, a Memory Section Attribute Storage (MSAS) and a memory access circuit (MAC). The memory includes a plurality of memory sections. The MSAS includes one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes. The MAC is configured to receive, from a host, a memory access request that specifies an address to be accessed in the memory, to identify a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS, to receive, from the MSAS, a security policy that corresponds to the target memory section, and to apply the security policy to the memory access request.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers
• G06F 12/14 - Protection against unauthorised use of memory

Abstract

A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

IPC Classes  ?

• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A flash memory includes multiple gate stacks arranged on a substrate, and a spacer structure. The spacer structure includes multiple thin spacers covering sidewalls of lower portions of the gate stacks and multiple thick spacers covering sidewalls of upper portions of the gate stacks. The thick spacers are located over the respective thin spacers, and the thick spacers are thicker than the thin spacers. The flash memory also includes a dielectric structure disposed on the spacer structure, and an air gap sealed by the dielectric structure and the spacer structure. The air gap includes a body portion between the thin spacers and a head portion between the thick spacers, and the body portion is wider than the head portion.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

A control circuit is provided herein, which can suppress the prolongation of a delay operation, so that the sequence using the DLL circuit to adjust the delay of the internal clock signal can be finished within a predetermined execution period. A control circuit includes a delay control unit delaying an input clock signal to generate an output clock signal based on the phase difference between the input clock signal and an output clock signal. The control circuit further includes a clock control unit. When the phase difference is greater than the first predetermined amount, the clock control unit inputs a clock signal delayed from the input clock signal by a second predetermined amount to the delay control unit as the input clock signal.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• H03L 7/183 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Abstract

A semiconductor structure including a substrate, multiple first pads, and multiple second pads is provided. The first pads are disposed on the substrate and are separated from each other. The second pads are disposed on the substrate and are separated from each other. Each of the first pads and each of the second pads are separated from each other. A top-view shape of the each of the first pads is different from a top-view shape of the each of the second pads. A portion of the first pads surrounds the same second pad.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate

Abstract

A memory device includes at least one memory bank, a plurality of data pins coupled to a plurality of package pins, a data input/output (IO) circuit, at least one bank IO circuit and a plurality of switches. The package pins correspond to a first bit order, and the data pins correspond to a second bit order. The data IO circuit is configured to communicate a first data with the data pins, wherein the first data is arranged in the first bit order. The bank IO circuit is configured to communicate a second data with the memory bank, wherein the second data is arranged in the second bit order. The plurality of switches perform at least one swapping operation on the first data to generate the second data or to perform the at least one swapping operation on the second data to generate the first data.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A semiconductor device, including a first MOS device, a second MOS device, a first dielectric layer, a stop layer, and a second dielectric layer, is provided. The first MOS device and the second MOS device are located on a substrate. The first dielectric layer is beside the first MOS device and the second MOS device. The stop layer is disposed on the first dielectric layer. The second dielectric layer covers the stop layer. The thickness of the second dielectric layer above the first MOS device is greater than the thickness of the second dielectric layer above the second MOS device.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/311 - Etching the insulating layers
• H01L 21/3115 - Doping the insulating layers
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

A control circuit includes a control unit, a delay line unit, and a detection unit. The delay line unit delays an input clock signal based on the delay amount and generates an output clock signal. The detection unit performs a detection operation to detect the number of delayed clock cycles from the input clock signal to the output clock signal. The control unit changes the delay amount during a delay operation and controls the delay line unit so that the input clock signal is synchronized with the output clock signal. Before the delay operation, the detection unit performs the detection operation multiple times and detects a plurality of numbers of delayed clock cycles. The control unit sets the delay amount for the detection operation and sets the delay amount for the delay operation according to plurality of detected numbers of delayed clock cycles.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter

Abstract

A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A memory controller for controlling a flash memory is provided. The memory controller includes a control circuit and a voltage generator. The control circuit is configured to program one or more pages of the flash memory in sequence, wherein each page includes a plurality of bytes. The voltage generator is configured to adjust the output voltage according to the control signal from the control circuit. The control circuit performs a programming verification operation on each byte of a current page of the one or more pages in a page programming mode, and calculates the first number of bytes which fail the programming verification operation and performs a programming operation again. The control circuit determines the programming mode of the page after the current page as the page programming mode or the byte programming mode according to the first number.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits
• G11C 16/30 - Power supply circuits

Abstract

A non-volatile memory and an operating method thereof are provided. The non-volatile memory includes a memory array and a controller. Each main memory cell string, a first judgment memory cell string, and a second judgment memory cell string of the memory array respectively includes a plurality of main memory cells, a plurality of first judgment memory cells and a plurality of second judgment memory cells. During a programming operation, the controller determines, according to a data level of each main memory cell, a data level of the corresponding first judgment memory cell, determines, according to data levels of each first judgment memory cell and its preceding first judgment memory cell, a data level of the 10 corresponding second judgment memory cell, and accordingly determines whether to perform a pre-programming operation during an erasing operation.

IPC Classes  ?

• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• G11C 16/10 - Programming or data input circuits
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

IPC Classes  ?

• B81C 3/00 - Assembling of devices or systems from individually processed components
• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

A method for forming a semiconductor structure includes providing a substrate with an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. The method further includes conformally forming a capping layer on the barrier layer and performing an annealing process, such that the dopant diffuses into the grain boundary of the barrier layer. The method further includes removing the capping layer and filling the opening with a conductive material.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate with a trench between active regions, a tunneling dielectric layer disposed on the substrate, a floating gate layer disposed on the tunneling dielectric layer, and an isolation feature disposed in the trench and on the substrate. The isolation feature has a first opening and a second opening below the first opening. The semiconductor structure further includes a mask disposed on the sidewall of the first opening, and a dielectric stack layer disposed directly above the mask and the second opening.

IPC Classes  ?

• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 21/762 - Dielectric regions
• H01L 29/66 - Types of semiconductor device

Abstract

A method for detecting a seam in a film is provided. The following process is performed on a film in a first wafer: (a) a scan is performed to obtain a gray level image; (b) a region positioning process is performed on the gray level image to define target regions and a seam region located in each target region; (c) a gray level value of each pixel in each seam region is obtained, and the number of pixels whose gray level values are lower than a gray level threshold value in each seam region is calculated; (d) a pixel quantity threshold value is generated according to the number in each seam region. Then, the process (a) to (c) is performed on a film in a second wafer, and a seam region having the number exceeding the pixel quantity threshold value is determined to be a defect region.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G06T 7/00 - Image analysis
• G06T 7/11 - Region-based segmentation
• G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods

Abstract

A dry etching method for reducing fluorocarbon-containing gas emissions is provided. The method includes supplying a first gas to a reaction chamber to adjust a process parameter related to the reaction chamber. The method also includes supplying a second gas to the reaction chamber. The method further includes turning on a power source to ionize the second gas, thereby generating plasma. The plasma is used to remove part of a material layer on a substrate. The composition of the first gas is different from the composition of the second gas.

IPC Classes  ?

• H01J 37/32 - Gas-filled discharge tubes

Abstract

A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Abstract

A memory device includes a stack structure disposed above a substrate. The stack structure includes a plurality of stacks and a plurality of isolation layers alternating with each other. Each stack includes: a first source and drain layer; an insulating layer disposed on the first source and drain layer; a second source and drain layer disposed on the insulating layer; and a channel layer disposed on a sidewall of the insulating layer. A lower surface of the channel layer is connected to the first source and drain layer, and an upper surface of the channel layer is connected to the second source and drain layer. The memory device further includes a gate pillar extending through the stack structure; and a charge storage structure disposed between the channel layer and the gate pillar.

IPC Classes  ?

• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a word line structure, a dielectric structure, a contact plug, and a sidewall insulating layer. The substrate includes an active region. The word line structure is disposed in the substrate and in the active region. The dielectric structure is disposed on the word line structure. The contact plug is disposed on the substrate and in the active region. The contact plug includes a first conductive pillar disposed on the substrate and a second conductive pillar disposed on the first conductive pillar. The sidewall insulating layer is disposed on an upper portion of a sidewall of the contact plug. The sidewall insulating layer is in contact with the first conductive pillar, the second conductive pillar, and the dielectric structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A memory device includes a Non-Volatile Memory (NVM) comprising a plurality of sectors, and a memory access circuit. The memory access circuit is configured to receive, from a host, a logical address of a block of data, to compute a mapping of the logical address to a data physical address comprising a selected sector among the plurality of sectors and a selected data offset within the same selected sector, to compute a metadata physical address that comprises the selected sector and a metadata offset in the selected sector, and to access the block of data at the data physical address, and the metadata at the metadata physical address.

IPC Classes  ?

• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A semiconductor structure includes a substrate, a dielectric structure, a floating gate, and a control gate. The substrate has a protrusion, a first recess, and a second recess, wherein the first recess and the second recess are on opposite sides of the protrusion. The dielectric structure extends from the first recess and the second recess to above a top surface of the protrusion. The floating gate is disposed over the substrate and adjoins a sidewall of the dielectric structure. The control gate is disposed over the floating gate and extends over a top surface of the dielectric structure to directly above the protrusion.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

IPC Classes  ?

• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G01R 31/3193 - Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response