A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.
A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.
A manufacturing method of a micro electro mechanical system (MEMS) device includes forming a buffer protection layer on a semiconductor structure, wherein the semiconductor structure includes a wafer, a MEMS membrane, and an isolation layer between the wafer and the MEMS membrane, and the buffer protection layer is located in a slit of the MEMS membrane and on a surface of the MEMS membrane facing away from the isolation layer; etching the wafer to form a cavity such that a portion of the isolation layer is exposed though the cavity; etching the portion of the isolation layer; and removing the buffer protection layer.
A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.
Chip packages and methods for forming the same are provided. The chip package includes a substrate having a stepped sidewall, a first surface, and a second surface. The first surface and the second surface are opposite each other. The first surface and the second surface adjoin the stepped sidewall. The chip package also includes a capping layer having a first surface and a second surface opposite each other. The first surface of the capping layer faces the second surface of the substrate. The chip package further includes a dam structure and an adhesive layer. The dam structure bonds the capping layer to the substrate, and surrounds a sensing region in the substrate. The adhesive layer surrounds the dam structure and has a concave-tapered sidewall that extends along the outer edge of the dam structure in the direction from the second surface of the substrate to the capping layer.
A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.
A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.
H01L 23/528 - Layout of the interconnection structure
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
11.
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME
A semiconductor device structure is provided. The semiconductor device structure includes a first transparent substrate, a conductive layer, an insulating protective layer, a second transparent substrate, a device substrate, and a bonding layer. The first transparent substrate has a first surface and an opposite second surface. The conductive layer is disposed on the second surface of the first transparent substrate. The insulating protective layer covers the conductive layer and the first transparent substrate. The second transparent substrate is disposed above the first transparent substrate, and has a first surface facing the first transparent substrate and an opposite second surface. The device substrate is disposed on the second surface of the second transparent substrate. The bonding layer is bonded to the insulating protective layer and the first surface of the second transparent substrate.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.
Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A chip package includes a chip, a first support layer, a light emitter, a first light transmissive sheet, a redistribution layer, and a conductive structure. A top surface of the chip has a conductive pad and a first light receiver. The first support layer is located on the top surface of the chip. The light emitter is located on the top surface of the chip. The first light transmissive sheet is located on the first support layer and covers the first light receiver. The redistribution layer is electrically connected to the conductive pad and extends to a bottom surface of the chip. The conductive structure is located on the redistribution layer that is on the bottom surface of the chip.
H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0232 - Optical elements or arrangements associated with the device
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
H01L 31/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.
A leakage detecting assembly includes a sheet leakage detecting module, a signal output unit, and a monitoring control system. The sheet leakage detecting module covers a wielding area or a connection area of a pipeline, and surrounds the pipeline. The sheet leakage detecting module is in direct contact with an outer surface of the pipeline. The signal output unit is electrically connected to the sheet leakage detecting module. The monitoring control system is electrically connected to the signal output unit.
A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.
A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.
A chip package includes a semiconductor substrate, an interlayer dielectric (ILD) layer, a first metal shielding layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, an inclined sidewall adjoining the first and second surfaces, and a through hole through the first and second surfaces. The ILD layer is located on the first surface of the semiconductor substrate, and a first conductive pad structure and a second conductive pad structure are disposed in the ILD layer. The first metal shielding layer is located on the ILD layer. A portion of the first metal shielding layer is located in the ILD layer and on the second conductive pad structure. The redistribution layer is located on the second surface of the semiconductor substrate, a wall surface of the through hole, and the first conductive pad structure.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
21.
Chip package including substrate having through hole and redistribution line
A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.
A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.
An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.
Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.
A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.
An antenna device includes a first substrate, a second substrate, an antenna layer, and a redistribution layer. The first substrate has a first surface, a second surface opposite to the first surface, and an inclined sidewall adjoining the first and second surfaces. The second substrate is below the first substrate. The first surface of the first substrate faces toward the second substrate. The antenna layer is located on the first surface of the first substrate. The redistribution layer extends from the second surface of the first substrate to the second substrate along the inclined sidewall of the first substrate, and the redistribution layer has a first section in contact with an end of the antenna layer.
A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.
A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.
A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.
An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.
A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.
A chip package includes a substrate, first and second dielectric layers, first and second metal layers, and first conductive vias. The first dielectric layer is on a bottom surface of the substrate. The first metal layer is on a bottom surface of the first dielectric layer. The first metal layer has first sections, and every two adjacent first sections have a gap therebetween. The second dielectric layer is on a bottom surface of the first metal layer and the bottom surface of the first dielectric layer. The second metal layer is on a bottom surface of the second dielectric layer, and has second sections respectively aligned with the gaps. Two sides of the second section respectively overlap two adjacent first sections. The first conductive via is in the second dielectric layer and in electrical contact with the first and second sections.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
45.
Chip package with substrate having first opening surrounded by second opening and method for forming the same
A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.
A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H01L 31/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices
H01L 31/0232 - Optical elements or arrangements associated with the device
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.
H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.
A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/04 - ContainersSeals characterised by the shape
A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.
A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
G01L 19/06 - Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.
A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.
A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/54 - Providing fillings in containers, e.g. gas fillings
H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
H01L 23/055 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads having a passage through the base
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.
H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.
A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
63.
Wafer-level packaging sensing device and method for forming the same
A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.
A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/76 - Making of isolation regions between components
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.
A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.
This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.
A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
72.
Chip package having a trench exposed protruding conductive pad
A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.
A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.
H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 23/04 - ContainersSeals characterised by the shape
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/528 - Layout of the interconnection structure
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/00 - Details of semiconductor or other solid state devices
79.
Chip scale sensing chip package and a manufacturing method thereof
This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A spray coater is used to spray a photoresist on a front surface of a wafer. The spray coater includes a vacuum chuck, a flow guiding ring, and a positioning ring. The vacuum chuck has a top surface and a side surface adjacent to the top surface. The wafer is located on the top surface and protrudes from the top surface of the vacuum chuck. The flow guiding ring is disposed around the vacuum chuck and has a groove. The wafer protruding from the top surface covers the flow guiding ring, and an opening of the groove faces a back surface of the wafer opposite to the front surface. The positioning ring is disposed around the flow guiding ring, such that the flow guiding ring is between the positioning ring and the side surface of the vacuum chuck.
B05C 13/02 - Means for manipulating or holding work, e.g. for separate articles for particular articles
B05C 11/02 - Apparatus for spreading or distributing liquids or other fluent materials already applied to a surfaceControl of the thickness of a coating
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
81.
Photosensitive module and method for forming the same
A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.
A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.
A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the first surface and covers the conducting pad. The method also includes bonding the sensing device to a circuit board. The cover plate is removed after bonding the sensing device to the circuit board. The method further includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.
A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.
A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.
A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/76 - Making of isolation regions between components
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.
A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
G01L 19/06 - Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
92.
Chip package having a dual through hole redistribution layer structure
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).
H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.
A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.
H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.
A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.
patents