Hexagem AB

Sweden

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        United States 9
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2025 3
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2021 2
Before 2021 9
IPC Class
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 9
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof 6
B82Y 40/00 - Manufacture or treatment of nanostructures 4
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier 3
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer 3
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Status
Pending 1
Registered / In Force 15
Found results for  patents

1.

SEMICONDUCTOR DEVICE COMPRISING MICROLED STRUCTURES

      
Application Number EP2024077613
Publication Number 2025/113850
Status In Force
Filing Date 2024-10-01
Publication Date 2025-06-05
Owner HEXAGEM AB (Sweden)
Inventor
  • Björk, Mikael
  • Heurlin, Magnus
  • Samuelson, Lars

Abstract

The proposed solution relates to a semiconductor device (30) comprising an epiwafer (10) and wherein a plurality of InGaN platelets (100), each InGaN platelet being monolithically grown on the epiwafer and configured with a top c-plane surface. An upper mask layer (200) is provided with mask apertures (220) over the InGaN platelets, wherein said mask apertures have a width which is smaller than said top c-plane surface. A plurality of microLED structures (240) comprising quantum well, QW, layers (242), are grown on the top c-plane surface in one of said mask apertures. The solution further relates to a microLED device (500) comprising the semiconductor device, and a method for fabricating the semiconductor device.

IPC Classes  ?

  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
  • H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

2.

SEMICONDUCTOR TEMPLATE AND FABRICATION METHOD

      
Application Number 18971280
Status Pending
Filing Date 2024-12-06
First Publication Date 2025-05-29
Owner HEXAGEM AB (Sweden)
Inventor
  • Bi, Zhaoxia
  • Ohlsson, Jonas
  • Samuelson, Lars

Abstract

A method for fabrication of an InGaN semiconductor template, comprising growing an InGaN pyramid having inclined facets on a semiconductor substrate; processing the pyramid by removing semiconductor material to form a truncated pyramid having a first upper surface; growing InGaN, over the first upper surface, to form an InGaN template layer having a c-plane crystal facet forming a top surface. The InGaN semiconductor template is suitable for further fabrication of semiconductor devices, such as microLEDs configured to emit red, green or blue light.

IPC Classes  ?

  • H10H 20/821 - Bodies characterised by their shape, e.g. curved or truncated substrates of the light-emitting regions, e.g. non-planar junctions
  • H10H 20/01 - Manufacture or treatment
  • H10H 20/812 - Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
  • H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN

3.

SEMICONDUCTOR STRUCTURES FOR MICROLEDS

      
Application Number EP2024067853
Publication Number 2025/056207
Status In Force
Filing Date 2024-06-25
Publication Date 2025-03-20
Owner HEXAGEM AB (Sweden)
Inventor
  • Samuelson, Lars
  • Bi, Zhaoxia
  • Björk, Mikael
  • Heurlin, Magnus
  • Berg, Martin

Abstract

BGRR) over a surface of the epiwafer in the respective InGaN platelets (100), wherein said height correlates with emission wavelength. The solution further relates to a microLED device (800) comprising the semiconductor structure, and a method for fabricating the semiconductor structure.

IPC Classes  ?

  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

4.

Semiconductor device having a planar III-N semiconductor layer and fabrication method

      
Application Number 17844247
Grant Number 11862459
Status In Force
Filing Date 2022-06-20
First Publication Date 2022-12-08
Grant Date 2024-01-02
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Samuelson, Lars
  • Storm, Kristian
  • Ciechonski, Rafal
  • Markus, Bart

Abstract

A semiconductor device having a planar III-N semiconductor layer includes a substrate including a wafer and a buffer layer of a buffer material different from a material of the wafer, the buffer layer having a growth surface, an array of nanostructures epitaxially grown from the growth surface, a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T, where the number of lattice cells spanning a center distance between adjacent nanostructures are different at the growth surface and at the coalesced planar layer, and a growth layer epitaxially grown on the planar layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
  • H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
  • C30B 25/04 - Pattern deposit, e.g. by using masks
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate

5.

Semiconductor template and fabrication method

      
Application Number 17436818
Grant Number 12218275
Status In Force
Filing Date 2020-03-18
First Publication Date 2022-08-04
Grant Date 2025-02-04
Owner HEXAGEM AB (Sweden)
Inventor
  • Bi, Zhaoxia
  • Ohlsson, Jonas
  • Samuelson, Lars

Abstract

A method for fabrication of an InGaN semiconductor template, comprising growing an InGaN pyramid having inclined facets on a semiconductor substrate; processing the pyramid by removing semiconductor material to form a truncated pyramid having a first upper surface; growing InGaN, over the first upper surface, to form an InGaN template layer having a c-plane crystal facet forming a top surface. The InGaN semiconductor template is suitable for further fabrication of semiconductor devices, such as microLEDs configured to emit red, green or blue light.

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
  • H01L 33/24 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

6.

Forming a planar surface of a III-nitride material

      
Application Number 17197540
Grant Number 11664221
Status In Force
Filing Date 2021-03-10
First Publication Date 2021-07-15
Grant Date 2023-05-30
Owner HEXAGEM AB (Sweden)
Inventor Ohlsson, Jonas

Abstract

A semiconductor device including a nanostructure, including a planar layer of a III-nitride semiconductor crystal, which layer includes an array of epitaxially grown nanowire structures, and semiconductor material which is redistributed from said nanowire structures in a reformation step after epitaxial growth, arranged to fill out a spacing between the nanowire structures, where the array of nanowire structures and the semiconductor material form a coherent layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • B82Y 40/00 - Manufacture or treatment of nanostructures

7.

III-nitride semiconductor devices

      
Application Number 16076205
Grant Number 11342477
Status In Force
Filing Date 2017-02-13
First Publication Date 2021-06-17
Grant Date 2022-05-24
Owner HEXAGEM AB (Sweden)
Inventor
  • Samuelson, Lars
  • Ohlsson, Jonas
  • Bi, Zhaoxia

Abstract

A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization.

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
  • H01L 33/24 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
  • H01L 33/38 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes with a particular shape

8.

SEMICONDUCTOR TEMPLATE AND FABRICATION METHOD

      
Application Number EP2020057451
Publication Number 2020/187986
Status In Force
Filing Date 2020-03-18
Publication Date 2020-09-24
Owner HEXAGEM AB (Sweden)
Inventor
  • Bi, Zhaoxia
  • Ohlsson, Jonas
  • Samuelson, Lars

Abstract

A method for fabrication of an InGaN semiconductor template, comprising growing an InGa N pyramid having inclined facets on a semiconductor substrate; processing the pyramid by removing semiconductor material to form a truncated pyramid having a first upper surface; growing InGaN, over the first upper surface, to form an InGaN template layer having a c-plane crystal facet forming a top surface. The InGaN semiconductor template is suitable for further fabrication of semiconductor devices, such as microLEDs configured to emit red, green or blue light.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

9.

Semiconductor device having a planar III-N semiconductor layer and fabrication method

      
Application Number 16652572
Grant Number 11393686
Status In Force
Filing Date 2018-10-05
First Publication Date 2020-07-23
Grant Date 2022-07-19
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Samuelson, Lars
  • Storm, Kristian
  • Ciechonski, Rafal
  • Markus, Bart

Abstract

A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).

IPC Classes  ?

  • H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
  • H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

10.

Forming a planar surface of a III-nitride material

      
Application Number 16341381
Grant Number 10991578
Status In Force
Filing Date 2017-10-05
First Publication Date 2020-02-20
Grant Date 2021-04-27
Owner HEXAGEM AB (Sweden)
Inventor Ohlsson, Jonas

Abstract

A semiconductor device including a nanostructure, comprising a planar layer (1020) of a Ill-nitride semiconductor crystal, which layer includes an array of epitaxially grown nanowire structures (1010), and semiconductor material (1016) which is redistributed from said nanowire structures in a reformation step after epitaxial growth, arranged to fill out a spacing between the nanowire structures, wherein the array of nanowire structures and the semiconductor material form a coherent layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • B82Y 40/00 - Manufacture or treatment of nanostructures

11.

SEMICONDUCTOR DEVICE HAVING A PLANAR III-N SEMICONDUCTOR LAYER AND FABRICATION METHOD

      
Application Number EP2018077233
Publication Number 2019/068919
Status In Force
Filing Date 2018-10-05
Publication Date 2019-04-11
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Samuelson, Lars
  • Storm, Kristian
  • Ciechonski, Rafal
  • Markus, Bart

Abstract

A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

12.

FORMING A PLANAR SURFACE OF A III-NITRIDE MATERIAL

      
Application Number EP2017075298
Publication Number 2018/073013
Status In Force
Filing Date 2017-10-05
Publication Date 2018-04-26
Owner HEXAGEM AB (Sweden)
Inventor Ohlsson, Jonas

Abstract

A semiconductor device including a nanostructure, comprising a planar layer (1020) of a Ill-nitride semiconductor crystal, which layer includes an array of epitaxially grown nanowire structures (1010), and semiconductor material (1016) which is redistributed from said nanowire structures in a reformation step after epitaxial growth, arranged to fill out a spacing between the nanowire structures, wherein the array of nanowire structures and the semiconductor material form a coherent layer.

IPC Classes  ?

  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

13.

Gallium nitride nanowire based electronics

      
Application Number 15594043
Grant Number 10236178
Status In Force
Filing Date 2017-05-12
First Publication Date 2017-11-02
Grant Date 2019-03-19
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Bjork, Mikael

Abstract

GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
  • B82Y 40/00 - Manufacture or treatment of nanostructures
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/786 - Thin-film transistors
  • H01L 29/861 - Diodes
  • H01L 29/872 - Schottky diodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate

14.

FORMING A PLANAR SURFACE OF A III-NITRIDE MATERIAL

      
Application Number EP2017057893
Publication Number 2017/168012
Status In Force
Filing Date 2017-04-03
Publication Date 2017-10-05
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Samuelson, Lars
  • Bi, Zhaoxia
  • Ciechonski, Rafal
  • Storm, Kristian

Abstract

A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first Ill-nitride material through a mask provided over a substrate; growing a second Ill-nitride semiconductor material on the seeds; planarizing the grown second semiconductor material to form a cohesive structure from the plurality of discrete base elements, said cohesive structure having a substantially planar upper surface.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

15.

III-NITRIDE SEMICONDUCTOR DEVICES

      
Application Number EP2017053187
Publication Number 2017/137635
Status In Force
Filing Date 2017-02-13
Publication Date 2017-08-17
Owner HEXAGEM AB (Sweden)
Inventor
  • Samuelson, Lars
  • Ohlsson, Jonas
  • Bi, Zhaoxia

Abstract

A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization.

IPC Classes  ?

  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

16.

Gallium nitride nanowire based electronics

      
Application Number 14378063
Grant Number 09653286
Status In Force
Filing Date 2013-02-12
First Publication Date 2015-01-15
Grant Date 2017-05-16
Owner HEXAGEM AB (Sweden)
Inventor
  • Ohlsson, Jonas
  • Bjork, Mikael

Abstract

GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/861 - Diodes
  • H01L 29/872 - Schottky diodes
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
  • H01L 29/786 - Thin-film transistors
  • B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
  • B82Y 40/00 - Manufacture or treatment of nanostructures
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate