A commissioner device is configured to determine, within a connection interval, a first anchor point during which communication with a first commissionee device occurs using the first communication protocol. The commissioner device is configured to determine, within the connection interval, a second anchor point during which communication with a second commissionee device of the plurality of commissionee devices occurs using the first communication protocol. The second anchor point is after the first anchor point in the connection interval and an end time of the first anchor point is separated from a beginning time of the second anchor point by a time period equal to or greater than a time period required to transmit a data packet using the second communication protocol. The commissioner device is configured to receive, during a time period determined by the second anchor point, a data transmission from the second commissionee device.
Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
3.
VIBRATION ISOLATION ASSEMBLIES FOR ELECTRONIC DEVICES
Vibration isolation can be provided for a vibration sensitive component to be bonded to electronic circuit boards or other surfaces by an assembly that includes two substrates with rigid portions that are electrically coupled to each other via a flexible interconnect. The rigid portions of the two substrates are bonded together via an elastic structure in a stacked arrangement with the first substrate above the second substrate. The flexible interconnect electrically couples the first substrate to the second substrate and the second substrate is configured to be bonded and electrically coupled to an electronic circuit board or other larger substrate via contacts on a surface of the rigid portion of the second substrate. The vibration sensitive component can be bonded to the rigid portion of the first substrate and couped to the flexible interconnect via the first substrate, thereby coupling it to the second substrate and the larger substrate.
H01R 12/62 - Fixed connections for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures
4.
METHOD AND SYSTEM FOR A WIRELESS DEVICE TO SWITCH TO A NON-PRIMARY CHANNEL ACCESS (NPCA) PRIMARY CHANNEL TO TRANSMIT FRAMES TO ANOTHER WIRELESS DEVICE
A method and system for announcing, by a first wireless device, one or more non-primary channel access (NPCA) primary channels of a basic service set (BSS) operating channel for frame transmission. A determination is made that the primary channel is busy and switching to a NPCA primary channel in response to the primary channel being busy and overlapping BSS activity. A frame is transmitted over the NPCA primary channel to a wireless device based on a backoff counter of the NPCA primary channel reaching a predefined value, the backoff counter set based on an enhanced distributed channel access (EDCA) parameter set.
A multi-chip package includes two electronic components bonded to each other via electrical contacts on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that includes a upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more through-package interconnects that pass through the molding material. A first through-package interconnect couples an electrically conductive interconnect in a first redistribution layer to an electrically conductive interconnect in a second redistribution layer on an opposite side of the volume of molding material from the first redistribution layer, or it couples the interconnect to one of the components within the volume of molding material.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
6.
DIRECT CURRENT (DC)-DC CONVERTER OPERATIONAL MODE TRANSITION WITH LIMITED VOLTAGE UNDERSHOOT OR OVERSHOOT
Embodiments of a circuit for a direct current (DC)-DC converter and DC-DC converters are disclosed. In an embodiment, a circuit for a DC-DC converter includes a resistive divider connected to an electrical terminal of the DC-DC converter, an amplifier connected to the resistive divider, a clock synchronization unit connected to a control circuit of the DC-DC converter and configured to generate control signals for the control circuit for switching the DC-DC converter between different operational modes, a first comparator connected to the amplifier and to the control circuit of the DC-DC converter, a second comparator connected to the resistive divider and to the control circuit of the DC-DC converter, and a voltage generator connected to the first comparator and configured to generate a comparator input voltage for the first comparator in response to an output voltage from the amplifier.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
7.
OVER-VOLTAGE PROTECTION FOR VARIABLE OUTPUT VOLTAGE SMPS
A method of detecting an over-voltage of an output of a variable output SMPS during a transition from a first target output voltage to a, higher, second target output voltage, and corresponding apparatus and controller, are disclosed comprising determining a signal representative of an output voltage, wherein the output voltage is an output voltage of the SMPS; determining a time-varying signal representative of a maximum allowed output voltage; comparing the signal representative of the output voltage with an instantaneous value of the signal representative of a maximum allowed output voltage; and in response to the signal representative of the output voltage being greater than an instantaneous value of the signal representative of a maximum allowed output voltage, indicating an over-voltage. A corresponding SMPS including such method controller or apparatus is also disclosed.
An embodiment of a semiconductor device includes a semiconductor substrate and one or more lower dielectric layers on the surface of the substrate. Source, drain, gate, and field plate openings, which are formed in a self-aligned manner, extend through the lower dielectric layer(s) to the substrate. A conformal dielectric layer is disposed over the lower dielectric layer(s) and into the gate and field plate openings. The conformal dielectric layer includes first portions on sidewalls of the gate opening, second portions on sidewalls of the field plate opening, and a third portion on the substrate at a bottom extent of the field plate opening. Gate spacers are formed on the first portions of the conformal dielectric layer. A gate electrode in the gate opening contacts the gate spacers and the semiconductor substrate. A field plate in the field plate opening contacts the second and third portions of the conformal dielectric layer.
An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode and first and second current-carrying electrodes, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal and DC-coupled to a first bias network electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF-isolated from the first control electrode. The amplifier device further includes a second transistor that includes a second control electrode that is RF coupled to the second input terminal and a second bias network electrically coupled to the second transistor, wherein the second bias network is configured to apply a second DC bias to the second transistor and is RF-isolated from the second transistor.
A packaged semiconductor device has a top surface and a bottom surface opposite the top surface. The packaged semiconductor device includes a device die, a plurality of perimeter landings, connection lines, and molding compound. The device die has a first surface and a second surface opposite the first surface. The device die is arranged in a central region of the packaged semiconductor device. The first surface of the device die is arranged towards the bottom surface of the packaged semiconductor device, and the second surface of the device die is arranged towards the top surface of the packaged semiconductor device. The plurality of perimeter landings are exposed on the bottom surface of the packaged semiconductor device and are arranged at perimeter regions of the bottom surface surrounding the device die. The connection lines are connected to the second surface of the device die. Each connection line provides electrical connection between a corresponding connection pad on the second surface of the device die and a corresponding one of the plurality of perimeter landings. The molding compound at least partially encapsulates the device die and the plurality of perimeter landings. The plurality of perimeter landings are made of a material having a mass fraction of tin of at least 95%.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A device may include a substrate having a plurality of laminated layers and a plurality of electrical interconnect pads on an outer surface of the plurality of laminated layers. The substrate may include a first plurality of magnetic material deposits on the outer surface of the plurality of laminated layers. A device may mount to the substrate. The device includes an electronic component including a plurality of terminals, and a base including a plurality of through-hole. A second plurality of magnetic material deposits may be on a second surface of the base. When the device is coupled to the substrate, each magnetic material deposit of the first plurality of magnetic material deposits is attracted by a magnetic force to a magnetic material deposit of the second plurality of magnetic deposits.
An integrated circuit includes a compressive stressor and a tensile stressor, each located directly over an active region of a transistor, where a portion of the compressive stressor and a portion of the tensile stressor directly overlap with each other. In some embodiments, utilizing a compressive stressor and tensile stressor located directly over an active region with overlapping portions may allow for an adjustment of the stress applied to a channel region of a transistor to compensate for stress imparted by package structures.
A power switch includes a first transistor and a second transistor, coupled in series between a first power supply voltage and a pad. The power switch also includes an analog multiplexer (MUX). The MUX is configured to provide a pad voltage to a control electrode of the first transistor when an overvoltage (OV) condition is detected on the pad, a second power supply voltage to the control electrode of the first transistor when an undervoltage (UV) condition is detected on the pad, and a reference voltage to the control electrode of the first transistor when neither the UV condition nor the OV condition is detected on the pad. The first power supply voltage is greater than the second power supply voltage, and the reference voltage is a fraction of the first power supply voltage.
A transmitter, including: a plurality of antennas; and a controller configured to: receive a first steering matrix for a first feedback tone; receive a second steering matrix for a second feedback tone; estimate an ideal second steering matrix including: estimating a set of random phasors applied to the columns of the second feedback matrix; and estimating a set of row-dependent delays applied to the rows of the second feedback matrix; estimate a vector of angles based upon the estimated set of random phasors; and calculate a steering matrix for a tone between the first feedback tone and the second feedback tone by interpolating between the first steering matrix and the ideal second steering matrix based upon the estimated vector of angles.
H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
In a wireless network having a plurality of nodes, determining a physical location of the plurality of nodes includes operating a first node of the plurality of nodes in a scanning mode to detect a second node of the plurality of nodes operating in an advertising mode within range of the first node, and repeating this for other nodes of the plurality of nodes to determine a list of node pairs that are within range of each other for each of the plurality of nodes in the wireless network. The list of node pairs from each of the plurality of nodes is transmitted to a controlling node. The controlling node instructs each of the node pairs to perform a channel sounding operation to determine a physical distance between the node pair and constructs a location map of the plurality of nodes based on the physical distance between each node pair.
A semiconductor device comprising an electrostatic discharge, ESD, protection device, the ESD protection device comprising a first PNP cell comprising: a substrate comprising a n-doped buried layer, NBL, extending laterally at a surface of the substrate, wherein the NBL comprises a first NBL portion, a second NBL portion and a third NBL portion laterally arranged at the surface of the substrate with the second NBL portion positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level that is less than a first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion; an epitaxial layer arranged on the surface of the substrate and comprising a PNP device comprising: a first p-doped region; a second p-doped region; and a n-doped region positioned between the first p-doped region and the second p-doped region, wherein the first p-doped region is aligned with the second NBL portion.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
This disclosure relates to a bootstrapped switching circuit. Example embodiments include a bootstrapped switching circuit (100) comprising: a positive output node (109+); a negative output node (109−); a first input node (106a) configured to receive a first input voltage (Vin1); a second input node (106b) configured to receive a second input voltage (Vin2). First, second third and fourth switches (101-104) are coupled between the input and output nodes (106a, 106b, 109+, 109−). A first negative bootstrapped level shifter (107a) and a first positive bootstrapped level shifter (107b) coupled between the first input node (106a) and a first clock signal circuit (110a) provide control signals to the first and second switches (101, 102). A second negative bootstrapped level shifter (108a) and a second positive bootstrapped level shifter (108b) coupled between the second input node (106b) and a second ground referenced supply line (110b) provide control signals to the third and fourth switches (103, 104). Each of the first, second, third and fourth switches (101, 102, 103, 104) comprise first and second MOSFETs (201a, 201b, 202a, 202b, 203a, 203b, 204a, 204b) of an opposite type in a series connected arrangement.
In an IEEE 802.11 wireless system, a sharing AP device (1A) shares a transmission opportunity with a shared AP device (2A) by transmitting a coordinated spatial reuse opportunity announcement control frame packet having defined signal fields which are used by the shared AP device (2A) to compute a transmit power limit for limiting interference at a first sharing STA device (1S) associated with the sharing AP device (1A) when transmitting one or more first downlink packets from the shared AP device (2A) to a first shared STA (2S) device associated with the shared AP device (2A).
A quadrature coupler includes four ports, four inductors, and six capacitors. The first through third capacitors are coupled in series between the first and fourth ports. A first intermediate node is between the first and second capacitors. A second intermediate node is between the second and third capacitors. The fourth through sixth capacitors are coupled in series between the second and third ports. A third intermediate node is between the fourth and fifth capacitors, and a fourth intermediate node is between the fifth and sixth capacitors. The first inductor is coupled between the first and second ports. The second inductor is coupled between the first and third intermediate nodes. The third inductor is coupled between the second and fourth intermediate nodes. The fourth inductor is coupled between the fourth and third ports. Variable tuning networks may be coupled between the first and fourth ports and the second and third ports.
Embodiments of a wireless device, a communications system and method are disclosed. In an embodiment, a wireless device comprises a wireless transceiver to receive and transmit frames, and a controller operably coupled to the wireless transceiver to process the frames, wherein the controller is configured to, in response to an enablement of a low-latency preemption mode from another wireless device, transmit a request for a low-latency preemption, and then transmit a low-latency frame to the another wireless device.
H04W 72/566 - Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
21.
Connector for Integration of Ethernet Time Synchronization Stacks
A time synchronization system, method, apparatus, and architecture are provided for synchronizing timing between two different time synchronization stacks with a timing synchronization connector which receives a frame transmit request at a first virtual Ethernet controller from a first time synchronization stack, which generates at a virtual timestamp module a sampled timestamp value for the frame by sampling a hardware counter, which forwards the sampled timestamp value for the frame over a second virtual Ethernet controller along with the frame to a second time synchronization stack, and which sends the sampled timestamp value for the frame to the first time synchronization stack, where the first and second time synchronization stacks each use the sampled timestamp value to compute a time synchronized Precision Time Protocol (PTP) clock domain signal.
Roaming for a non-access point (non-AP) device with a roaming access point (AP) multi-link device (MLD), wherein the roaming AP MLD includes a plurality of AP MLDs in different devices at different locations having one medium access control (MAC) service access point (SAP), including: exchanging management frames between the non-AP device and a current serving AP MLD that is one of the plurality of AP MLDs to select a future serving AP MLD that is one of the plurality of AP MLDs and to select future serving link of the future serving AP MLD; and exchanging management frames between the non-AP device and the serving AP MLD to switch from the current serving AP MLD and the future serving AP MLD.
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to generate a control frame carrying security related information for frame integrity protection in different locations in the control frame with other information in between the security related information and a wireless transceiver configured to wirelessly transmit the control frame to a second communications device.
An audio playback method for a Bluetooth low energy (BLE) system is described. The BLE system includes at least two BLE audio playback devices configured to be bonded to a BLE audio source device having two BLE transceivers. A first BLE audio playback device of the plurality of BLE audio playback devices may initially have an active connection to the BLE audio source device. The method includes sending audio data from the BLE audio source device to the first BLE audio playback device. A metric of an active connection signal and a bonded connection signal is determined. The method determines whether a second BLE audio playback device is a better candidate for audio playback than the first BLE audio playback device depending on at least the bonded connection signal metric. If it is a better candidate, the active connection is handed over to the second BLE audio playback device.
A semiconductor device having hybrid routing is provided. The semiconductor device includes a package substrate having a first major side and a second major side. A plurality of conductive bond-on-pad (BOP) pads and a plurality of conductive bond-on-trace (BOT) pads are formed at the first major side. A non-conductive layer is formed over the plurality of BOP pads. Openings in the non-conductive layer expose a central portion of each BOP pad of the plurality of BOP pads. An inlet region is formed in the non-conductive layer such that a first BOT pad of the plurality of BOT pads is located within the inlet region.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
26.
SYSTEM AND METHOD TO FACILITATE ACCESS BY A REMOTE COMPUTER TO A PCIE CONFIGURATION SPACE
Facilitating access to a PCIe configuration space of a PCIe function associated with a computer comprises receiving by a PCIe controller EP in the computer over a PCIe link a configuration request from a remote computer to access a PCIe configuration space. The PCIe controller then communicates over a communication fabric the configuration request to a dispatcher of the computer. The dispatcher determines from the configuration request, a PCIe function and operation indicated in the configuration request which is used to identify a respective subsystem to execute the configuration request and the configuration request is communicated to the respective subsystem based on the identification. The subsystem then executes the configuration request to facilitate access to the PCIe configuration space of the PCIe function by the remote computer and sharing of the PCIe function with the remote computer.
A delay locked loop (DLL) circuit comprises a voltage-controlled delay line (VCDL) that applies a time delay to a clock-in signal in order to provide a first output signal and a last output signal, wherein the magnitude of the time delay is based on the control-voltage signal and a delay code. The DLL circuit also comprises a feedback circuit that is configured to provide a feedback voltage signal based on the phase difference between the first output signal and the last output signal. When the delay locked loop circuit is in a calibration mode of operation: a fixed voltage source provides a fixed voltage signal as the control-voltage signal for the VCDL; and a delay code setter applies a delay code setting signal to the VCDL such that it applies a sequence of different candidate delay codes to the VCDL in order to identify a selected-delay-code as the code that results in a predetermined phase difference between the first output signal and the last output signal. When the delay locked loop circuit is in an active mode of operation: the feedback circuit provides the feedback voltage signal as the control-voltage signal for the VCDL; and the VCDL uses the selected-delay-code as the delay code.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
28.
MEMS Array Structures for Gyroscopes with High Resonant Frequencies
A MEMS inertial sensor device, method of operation, and fabrication process are described wherein a MEMS inertial sensor and drive actuation units are coupled together in operational engagement, where the MEMS inertial sensor includes a substrate and a proof mass array positioned in spaced apart relationship above a surface of the substrate and constructed with a plurality of proof mass sub-structures which are each separately connected to the substrate with orthogonally disposed pairs of spring suspension structures and which are each rigidly connected to one or more adjacent proof mass sub-structures with one or more connector bars so that the plurality of proof mass sub-structures move as a single proof mass array that can operate at resonant frequencies of at least 100 kHz when oscillating in first and second orthogonal directions.
A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and routing structure on a carrier substrate. At least a portion of the semiconductor die and routing structure are encapsulated with an encapsulant. A cavity formed in the encapsulant. A top portion of the routing structure is exposed through the cavity. A conductive trace is formed to interconnect the semiconductor die with the routing structure.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01R 12/57 - Fixed connections for rigid printed circuits or like structures characterised by the terminals surface mounting terminals
A first circuit path communicates a first, asynchronous, signal, and a second path communicates a second signal. A schmoo delay circuit receives the first and second signals and includes shmoo control circuitry and a delay generator. The delay generator receives a delay selector signal from the shmoo control circuitry indicative of an amount of delay. The shmoo delay circuit provides a delayed version of at least one of the first or second signals. A first logic circuit receives the delayed version of the at least one of the first signal or the second signal, and a second logic circuit receives another one of the first signal or the second signal. The shmoo control circuitry modifies the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
One example discloses a driver circuit, including: a high-side element coupled to receive a supply voltage and configured to be coupled to a first terminal of a load; a low-side element coupled to a ground and configured to be coupled to a second terminal of the load; a controller coupled to activate both the high-side element and the low-side element at a same time; and a reverse current blocking element coupled between the voltage supply and the high-side element; wherein the reverse current blocking element is configured to permit current flow from the voltage supply to the high-side element, and to block current flow from the high-side element to the voltage supply.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
32.
Compliant Stops for MEMS Inertial Device Drive PLL Stability
A MEMS inertial sensor device, method of operation, and fabrication process are described with a MEMS inertial sensor, drive actuation unit, drive measurement unit, and PLL circuit coupled together in operational engagement, where the MEMS inertial sensor includes a substrate, a proof mass positioned in spaced apart relationship above the substrate, a proof mass suspension member connected on a first end to the proof mass and connected on a second end to an anchor fixed to the substrate to enable the proof mass to laterally oscillate over the surface of the substrate, and a compliant stop structure positioned in relation to the proof mass suspension member to physically engage with lateral oscillating movement of the proof mass suspension member past a desired stroke travel distance without physically preventing lateral oscillating movement of the proof mass, thereby stiffening a spring stiffness measure of the proof mass suspension member.
G01C 19/5719 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using planar vibrating masses driven in a translation vibration along an axis
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
A battery management unit, BMU, configured to communicate, in parallel, with a plurality of cell monitoring circuits, CMCs, configured to provide for monitoring of battery cells and store a chain-identifier parameter initially comprising a predetermined default value, wherein the BMU is configured to perform a chain-identifier parameter assignment procedure comprising assigning a different chain-identifier parameter to each of the plurality of CMCs, wherein said assigning comprises using a unique ID of each CMC to individually select each one of the plurality of CMCs when assigning the respective different chain-identifier parameter, wherein the unique ID of each CMC is received by the BMU in response to the BMU being configured to send, in parallel to the CMCs using the predetermined default value, one or more request messages requesting that they report their unique IDs to the BMU.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
One example discloses a level shifter circuit, including: an input port configured to receive an input signal (IN); an output port configured to transmit an output signal (OUT); a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal; and a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
35.
ROTATING RESOURCE UNITS IN FRAMES FOR WIRELESS COMMUNICATIONS
Embodiments of a wireless device and method are disclosed. In an embodiment, a wireless device comprises a wireless transceiver to receive and transmit frames, and a controller operably coupled to the wireless transceiver to process the frames, wherein the controller is configured to generate at least one frame that includes a resource unit for a first user that is rotated in frequency such that a first frequency location of the resource unit for a first time period is different than a second frequency location of the resource unit for a second time period.
A battery management system comprising: a sequence of four or more battery connection terminals for connecting to a series of batteries; a resistance associated with each battery connection terminal; and a sequence of three or more ADCs. Each ADC is associated with a pair of the battery connection terminals and is configured to convert the difference between the analogue voltages at its first and the second ADC input terminals to a digital signal, and to provide that digital signal at its ADC output terminal. The battery management system also includes a digital processor that is configured to, for each ADC in the sequence: calculate an error voltage for the ADC based on: i) the digital signal for the preceding ADC in the sequence if there is one; and ii) the digital signal for the next ADC in the sequence if there is one; and provide a measured-voltage output signal by subtracting the error voltage from the digital signal for the ADC.
An alignment recess formed in a cover substrate such as a cover for a MEMS device allows a second substrate to be bonded to the cover substrate. The alignment recess is larger than the second substrate and has two corner regions diagonally opposite each other where a wall of the recess protrudes to form a notch. The notch is dimensioned such that when the second substrate is disposed within the recess with two opposing corners surrounded by respective notches of the recess, the angular position of the second substrate relative to the cover substrate can be controlled to within a desired amount of rotation.
Alignment features formed on a cover substrate allow for a second substrate to be bonded to the cover substrate while ensuring that the second substrate is not titled with respect to a plane defined by the alignment features. Die attachment material is patterned such that it deforms or flows underneath the second substrate while allowing corners of the second substrate to rest on landing areas that are elevated above the top surface of the cover substrate. Some of the landing areas may include additional features that are elevated above the landing areas to form notches which constrain the rotational position of the second in addition to its tilt.
An attenuation structure that includes one or more electrically resistive structures is disposed above or below a contact electrode such as a bond pad that is electrically coupled to a first region of an electronic device such as a transistor. The attenuation structure is capacitively coupled to the contact electrode and is configured to cause anisotropic attenuation of time-varying electrical signals applied to the contact electrode. The attenuation structure is characterized by a first attenuation coefficient along a first direction oriented toward the first region and by a second attenuation coefficient that is greater than the first attenuation coefficient along a second direction that is angularly separated from the first direction.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
One example discloses a converter circuit, including: an input configured to receive either a voltage or a current; an output configured to transmit either a voltage or a current; a voltage reference; a half-bridge (HB) node; a high-side (HS) switch coupled between the input and the HB node; a low-side (LS) switch coupled between the voltage reference and the HB node; and a controller coupled to the HB node, the HS switch, and the LS switch; wherein the controller is configured to send a first command signal after a first regulated time to turn on the HS switch after an HB voltage on the HB node begins rising in response to the LS switch having been turned off.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of DC power input into DC power output
41.
SYSTEM AND METHOD FOR BEACON FRAME GENERATION WITH AND WITHOUT MULTIPLE BASIC SERVICE SET IDENTIFIER (MBSSID) SUPPORT
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to generate a beacon frame based on Multiple Basic Service Set Identifier (MBSSID) support information and a wireless transceiver configured to wirelessly transmit the beacon frame to a second communications device.
Disclosed is a communication chain comprising a battery management unit (BMU) and a plurality of battery cell controllers (BCC), and method of operating the same, comprising: a most-remote BCCs transmitting a message towards the BMU and starting a local-clock counter; each of the other BCCs receiving and forwarding the message towards the BMU and starting a respective local-clock counter; the BMU receiving the message, starting a BMU-clock counter, transmitting a further message and stopping the BMU-clock counter to determine a BMU-interval-count; each of other BCCs receiving and forwarding the second message, and stopping the respective local-clock counter to determine a respective local-interval-count; the most-remote of the BCCs receiving the further message, and stopping the most-remote-local-clock counter to determine its local-interval-count; the BMU broadcasting the BMU-interval-count and the BCCs determining their respective communication delay
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to generate a protected control frame and a transceiver configured to transmit the protected control frame to a second communications device. The protected control frame includes a protected trigger frame, a protected block acknowledgement (BA) frame, or a protected block acknowledgement request (BAR) frame.
A motion plan safety analysis is performed by processing vehicle sensor signals to generate a motion plan which includes a reference trajectory value, by processing the reference trajectory value at a first MPC to generate a first current setpoint and a first plurality of future setpoints, by processing the first plurality of future setpoints at a second MPC to generate a second plurality of future setpoints, by processing the second plurality of future setpoints at the first MPC to generate a first plurality of predicted trajectory states, by processing the first plurality of future setpoints at the second MPC to generate a second plurality of predicted trajectory states, by evaluating the predicted trajectory states to generate a predetermined safety reaction for the vehicle, and by choosing between the first and second current setpoints based on the safety reaction to provide a safest setpoint to a vehicle actuator in the vehicle.
A controller for a one-time-programmable (OTP) memory is configured to, in response to a write request to program a single bit of an OTP value to the OTP memory, program a bit of the OTP value in the OTP memory, generate a set of PCBs corresponding to the OTP value, and program the PCBs into the OTP memory. Each PCB of the set of PCBs is generated as a logic function of a different subset of bits of the OTP value. The logic function only results in each PCB being programmed or remaining programmed in the OTP memory but not cleared. The OTP controller may be configured to, in response to the write request, program both the bit of the OTP value and a redundant bit, in which the set of PCBs includes a first PCB based on the bit and a second PCB based on the redundant bit.
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A system on a chip (SOC) includes a user space having one or more cores, and a hardware security engine (HSE). The HSE includes storage circuitry configured to store an SOC configuration table. The SOC configuration table is configured to store, in a first entry, a current and valid configuration record corresponding to a current configuration of the SOC. The HSE is configured to, in response to an update service request from a core of the user space, decrypt an encrypted file to obtain new configuration data, update a blank record in a second entry of the SOC configuration table to be the current and valid configuration record storing the new configuration data, and update the current and valid configuration record in the first entry to be a previous and valid configuration record.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A packaged semiconductor device has a first surface, a second surface opposite the first surface, and sidewalls therebetween. The semiconductor device includes: a device die arranged in a central region surrounded by the sidewalls; a plurality of electrically conductive contacts around a peripheral region of the second surface; and molding compound between electrically conductive contacts, and between the device die and the electrically conductive contacts. The electrically conductive contacts each have an end side surface forming a part of the sidewall, and remainder of the sidewall comprises surfaces of the molding compound. The packaged semiconductor device has recesses between the electrically conductive contacts, each recess has a first distance along the sidewall from the second surface towards the first surface, and a second distance from the sidewall towards the central region.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
Disclosed is a packaged semiconductor device having first and second major surfaces and comprising, a semiconductor die; conductive epoxy in contact with a surface of the semiconductor die, and exposed in a central region of the first major surface; a plurality of studs around a peripheral region of the first major surface; wire bonds between the semiconductor die and a surface of the studs which is remote from the first major surface, the wire bonds providing electrical connections between the semiconductor die and the plurality of studs; and encapsulant defining the second major surface and sidewalls of the packaged semiconductor device, wherein the first major surface is defined by the conductive epoxy, the encapsulant, and the studs.
A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/083 - Details of the phase-locked loop the reference signal being additionally directly applied to the generator
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
Systems and methods for transmitting signals through long delay lines are discussed. In some embodiments, a delay line may include: (i) a first delay element comprising: a first input terminal, a first output terminal, and a first reset terminal; and (ii) a second delay element comprising: a second input terminal coupled to the first output terminal, and a second output terminal coupled to the first reset terminal. In other embodiments, a method may include coupling an input terminal of a delay element to an output terminal of a preceding delay element, and coupling an output terminal of the delay element to a reset terminal of the preceding delay element.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
The present invention relates to a device comprising two communication units, wherein one of the two communication units additionally comprises a protection unit configured to protect against excessive electrical voltages. The state of the protection unit can be changed to enable or disable the protection. Furthermore, an associated method is disclosed.
Processing circuitry includes a selectively powered domain having a communications interface to communicate with power management circuitry via a bus in accordance with a bus protocol, and a processing core to control the communications interface, wherein the selectively powered domain is not powered when the processing circuitry is operating in any one of multiple low power modes. The processing circuitry also includes an always on power domain having a set of pins to communicate a set of handshake signals with the power management circuitry and a power management sequencer to control power mode transitions of the processing circuitry. When the processing circuitry is operating in one of the multiple low power modes such that the communications interface and the processing core are not powered, the power management sequencer generates a signature on the set of handshake signals to control power mode transitions from one of the multiple low power modes.
Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
H03B 5/06 - Modifications of generator to ensure starting of oscillations
A semiconductor device and a method of manufacturing the same include a die and a thermal layer, and a thick-silver layer disposed directly onto a first of the thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
A method of wireless communication includes configuring a first wireless communication device as a central and a second wireless communication device as a peripheral or vice versa. The first wireless communication device includes a number of controllers (transceivers). The method further includes forming an active link between the second wireless communication device and the first wireless communication device via a first controller. During each connection interval of a measurement period, the method further includes the steps of (i) transmitting only one data packet via the first controller for a central device or suspending transmission from the first controller for a peripheral, (ii) determining a first received signal quality from a data packet received via the first controller, (iii) receiving one data packet (central) or two data packets (peripheral) at a second controller, and (iv) determining a second received signal quality from the last received data packet at the second controller.
A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
As disclosed herein, circuitry and a method for providing a digitized voltage value of one capacitive sensor in which a second capacitive sensor is utilized for charge equalization. After charge equalization, an analog to digital converter (ADC) provides a digital value representative of the voltage of the one sensor.
G01D 5/24 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
Systems and methods for providing temperature compensation in oscillators circuits are discussed. In various embodiments, these systems and methods may be implemented in technologies where only resistors with the same type (positive or negative) of temperature coefficients of resistance are available. For example, in some implementations, an oscillator circuit may include a voltage generator coupled to an input terminal of a common gate amplifier through a first resistor, and a frequency-to-voltage converter coupled to another input terminal of the common gate amplifier through a second resistor, where the second resistor may be configured to reduce a frequency variation of the oscillator circuit in response to temperature changes.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
A receiver receives a wireless signal comprising a plurality of fields including a legacy short training field (L-STF), legacy long training field (L-LTF), and legacy signal (L-SIG) field transmitted to a plurality of antenna of the receiver. For each sub-band in a receiver bandwidth and when samples of the L-STF is received, a first angle based autocorrelation is performed to determine a group of sub-bands which maximize a magnitude based on the first autocorrelations for one or more sub-bands. For each sub-band in the receiver bandwidth and when samples of the L-LTF is received, a second angle based autocorrelation is then performed to refine the crude bandwidth pattern estimate. One or more signal fields and one or more data fields of the received signal are decoded based on the refined bandwidth pattern estimate.
A method for partial quantization to achieve full quantized model includes quantizing a plurality of weights and a respective activation function from each of a plurality of respective layers of an original Machine Learning Model (MLM) to generate a quantized MLM comprising a plurality of frozen quantized weights. The plurality of frozen quantized weights are extracted from at least one frozen layer of the layers of the quantized MLM. The plurality of weights are quantized from at least one updated layer of an updated MLM to generate a plurality of updated quantized weights. The respective activation function of the at least one updated layer of the updated MLM is quantized from a difference between the original MLM and the updated MLM, to form a respective quantized activation function. A new quantized MLM is generated from the frozen quantized weights, the updated quantized weights and the respective quantized activation function.
A system comprising a first gate driver comprising: a first die including a first controller for controlling a gate of a first power switch; a second die arranged with the first die and galvanically isolated from the first die, the second die comprising communication circuitry; wherein the first die includes a first connection element and the second die includes a second connection element, wherein the first and second connection elements are configured to provide a communication channel between the galvanically isolated first die and second die; and wherein the second die comprises at least one communication terminal for coupling to a second gate driver comprising a second controller, the second controller for controlling a gate of a second power switch; wherein the communication channel provides for communication between the first controller and the second controller.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
62.
A PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A packaged semiconductor device (200) is disclosed, having a first major surface (210), a second major surface (220), and sidewalls (230) therebetween, the packaged device comprising: a moulding compound (240) around a perimeter of the device and defining at least a part of the sidewalls; a lid (250) defining the first major surface, and defining a cavity (252) within the packaged semiconductor device; wherein the lid extends from a central region, to and beyond an upper surface of the moulding compound, and comprises a lip (260) around at least part of the moulding compound; further comprising an adhesive material (270), between a top surface of the moulding compound and the lid and providing a bond therebetween. Related methods are also disclosed.
H01L 23/043 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
H01L 21/52 - Mounting semiconductor bodies in containers
63.
MEMS Device and Fabrication Process with Reduced Z-Axis Stiction
A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having an inertial transducer element formed in a multi-layer semiconductor structure, where the first inertial transducer element comprises a first monocrystalline semiconductor proof mass element and a second conductive electrode element separated from one another by an air sensing gap, and where at least a first sensing gap surface of the first monocrystalline semiconductor proof mass element is a first rough surface that has been selectively etched to reduce stiction between the first monocrystalline semiconductor proof mass element and the second conductive electrode element.
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
64.
POWER AMPLIFIER (PA) SELF-HEATING TRACKING FOR WITH SELF-HEATING TIME CONSTANT ESTIMATION
Embodiments of self-heating tracking circuits for a power amplifier (PA) are disclosed. In an embodiment, a self-heating tracking circuit for a PA includes a PA replica circuit in proximity to the PA and an estimation unit configured to estimate a self-heating time constant of the PA in response to turning on the PA replica circuit and turning off the PA replica circuit.
A method and system for wireless transmission comprises receiving bits of resource units (RU) at a physical layer processing unit of a wireless device. The bits of the RUs are parsed into a plurality of RU fragments carried by one or more spatial streams. One of the resource unit fragments is modulated with a first modulation and another of the resource unit fragments is modulated with a second modulation which is different from the first modulation. Each spatial stream carrying the resource units fragments which are modulated is then mapped to one or more antenna for wireless transmission.
A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A communication system, including: a first modulator configured to modulate a first periodic signal with a first frequency based upon an input signal; a second modulator configured to modulate a second periodic signal with a second frequency based upon the input signal; an isolated differential channel including isolation capacitors with a first line connected to the first modulator and a second line connected to the second modulator; a mixer configured to mix signals received from the first line and the second line of the differential channel and to produce a mixer output signal; a bandpass filter connected to the mixer configured to filter the mixer output signal; an envelope detector configured to detect an envelope of the filtered mixer output signal; and a detector configured to detect a data signal in the envelope of the filtered mixer output signal and to produce an output signal.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
A requestor of a data processing system provides read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size onto a system interconnect. A memory array stores write data and corresponding error correction code (ECC) check bits in response to write access requests and provides read data and corresponding ECC check bits for the read data in response to read access requests. A memory controller executes a read-modify-write (RMW) sequence between a store buffer and the memory array to implement a partial write transaction in response to a partial write access request, in which the memory controller stores the partial write data into the store buffer upon receiving the partial write access request and suppresses signaling of ECC errors to the requestor during the RMW sequence.
A hub device comprising: a first port, a second port and a hub controller. The first port is configured to be connected to an initiator controller. The second port is configured to be connected to a target device, and wherein the target device has an address. The hub controller is configured to receive the target device address from the initiator controller via the first port, and in response: set a first-port-clock-line of the first port to busy; transmit the received target device address to the second port, to which the target device is connected; enable a bridge between the initiator controller and the target device, via the first port and the second port; release the first-port-clock-line of the first port from busy; communicate an acknowledgement message from the target device to the initiator controller via the bridge; and communicate a data transmission between the initiator controller and the target device via the bridge.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate a frame that includes interference information indicating an existence or an occurrence of a wireless communications interference and a wireless transceiver configured to transmit the frame through an antenna.
A method of detecting and mitigating an SEL is provided. The method includes measuring a current of a first circuit block of a semiconductor device and determining that the measured current exceeds a first threshold. In response to the measured current exceeding the first threshold, a supply voltage of the first circuit block is reduced from a nominal voltage value to a predetermined voltage value. After reducing the supply voltage to the predetermined voltage value, the supply voltage is restored to the nominal voltage value.
H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
A method of method of dynamic channel switching by a station (STA), including: receiving a resource unit (RU) allocation in an initial frame exchange; determining that the STA cannot operate in its operating BW covering a primary channel based upon the RU allocation; switching to secondary channel(s) per an RU allocated to it to carry out communication by the STA during a transmit opportunity (TXOP); carrying out the communication during the TXOP; and switching back to the primary channel no later than an end of the TXOP if detecting that an AP will not do the initial frame exchange with it in the secondary channel(s) within the TXOP.
A non-access point (non-AP) multi-link device (MLD) is arranged to roam within a roaming AP MLD comprising a plurality of AP MLDs. The non-access point MLD receives from the roaming AP MLD an announcement. In an example, the announcement indicates that the roaming AP supports one of a link level roaming and MLD roaming within the roaming AP MLD. Based on the announcement, the non-AP MLD sends a roaming request to the roaming AP MLD, where the roaming request indicates one of the link level roaming and MLD roaming. A roaming response is received from the roaming AP MLD where the response indicates at least one new link established from the non-AP MLD to the roaming AP MLD. Based on the new link which is established, the non-AP MLD exchanges frames with the roaming AP MLD.
A method of forming a semiconductor device is provided. The method includes placing a semiconductor die on a carrier substrate and affixing a rigid-flex sub-assembly on the semiconductor die. The rigid-flex sub-assembly includes a rigid portion and a flex portion having a conductive trace. A distal region of the flex portion is bent such that the bent distal region is not coplanar with the rigid portion. An encapsulant encapsulates at least a portion of the semiconductor die and the rigid-flex sub-assembly.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
An amplifier device, such as an operational amplifier device or unity gain buffer, may include a first input terminal, an inverting input terminal, a non-inverting input terminal, a reference voltage supply terminal, a negative voltage supply terminal, and an output terminal. The amplifier device may include one or more cascode arrangements, such as a first cascode arrangement coupled between the negative voltage supply terminal and the output terminal. A first transistor of the first cascode stage may be configured to receive a variable bias voltage at its gate terminal. A second transistor of the first cascode stage may be configured to receive a fixed bias voltage at its gate terminal. The variable bias voltage may correspond to a first input voltage supplied at the first input terminal.
H03F 1/52 - Circuit arrangements for protecting such amplifiers
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
76.
BUFFER COMPATIBLE WITH SKEW CRITICAL PROTOCOLS IMPLEMENTED IN AN INTEGRATED CIRCUIT AND METHODS FOR ROUTING METAL LINES TO THE BUFFER IN THE INTEGRATED CIRCUIT
A buffer in an integrated circuit comprises one or more logic circuits, an input signal pin electrically coupled to an input of one of the one or more logic circuits, and an output signal pin electrically coupled to an output of one of the one or more logic circuits. The input signal pin and output signal pin are positioned on a same routing track of the integrated circuit which specifies a routing in the integrated circuit. A respective segment of a net routed to the input and output signal pin is on the same routing track.
A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.
A receiver circuit, comprising: an receiver-input-terminal configured to receive input-signalling; an receiver-output-terminal configured to provide output-signalling; a plurality of sub-receivers, each configured to compare the received input-signalling with a different effective threshold value in order to provide a digital sub-receiver-output-signal, wherein the different effective threshold values have weighted values in a sequence between a least significant value and a most significant value; a controller configured to, in response to detecting calibration-signalling at the receiver-input-terminal: process the digital sub-receiver-output-signals in order to identify the sub-receiver with the most significant effective threshold value that is triggered by the calibration-signalling as a triggered-sub-receiver; identify a preceding-sub-receiver as the sub-receiver that has an effective threshold value that is before that of the triggered-sub-receiver in the sequence of weighted effective threshold values; and configure the receiver circuit such that, for subsequent signal processing, the sub-receiver-output-signal from the preceding-sub-receiver is provided to the receiver-output-terminal.
Embodiments of receiver device and method are disclosed. In an embodiment, a receiver device comprises a wireless transceiver arranged to receive and transmit packets, and a controller operably coupled to the wireless transceiver to process the packets, wherein the controller is configured to receive a packet from a transmitter device and process the packet using one or more of dual correlators and dual finite state machines (FSMs), wherein the dual correlators include a first correlator to detect extended long-range (ELR) packets and a second correlator to detect non-ELR packets, and wherein the dual FSMs include a first FSM to process the ELR packets and a second FSM to process the non-ELR packets.
A semiconductor device includes a semiconductor substrate with an upper surface and a channel, a dielectric layer disposed over the upper surface, and a diffusion barrier layer disposed over the dielectric layer. The diffusion barrier layer is patterned to include multiple segments. A gate electrode is formed over the semiconductor substrate and is electrically coupled to the channel. A drain opening is spatially separated from a first side of the gate electrode. A drain electrode, which also is electrically coupled to the channel, includes a first portion formed within the drain opening, and a second portion that overlies a segment of the diffusion barrier layer. A conductive field plate between the gate electrode and the drain electrode includes a field plate layer and another segment of the diffusion barrier layer. The drain electrode and the field plate layer may be formed from portions of a same conductive layer.
A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.
A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.
H03K 19/018 - Coupling arrangementsInterface arrangements using bipolar transistors only
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
83.
CANCELLATION CIRCUIT USING DIGITAL TO TIME CONVERTER
A cancellation circuit includes a limiter connected to an output of a first transmitter power amplifier that converts in input sinewave to a digital square wave and a digital to time converter (DTC) connected to the limiter. A RF digital to RF converter is connected to the DTC that converts the digital square wave input into an analog RF output. A cancellation amplifier with an input receives an output from the RF digital to RF converter and has an output connected to an output of a second transmitter power amplifier. The cancellation amplifier produces a cancellation signal to cancel an interference signal at the output of the second transmitter power amplifier from the output of the first transmitter power amplifier. A power detector is connected to the output of the second power amplifier that produces a power value detected at the output of the second power amplifier.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate a control signal and a wireless transceiver configured to, in response the control signal, perform a low-density parity-check (LDPC) encoding operation to generate an encoded data unit with extra LDPC symbol segments.
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 5/00 - Arrangements affording multiple use of the transmission path
A transistor includes a semiconductor die with an active region and one or more non-active regions that do not overlap or overlie the active region. The transistor further includes a group of multiple transistor fingers in the active region. One or more source vias are located adjacent to sides of the group of transistor fingers. One or more source manifolds are located in the non-active region(s), and the source manifold(s) electrically connect the source via(s) with at least one source region of the multiple transistor fingers.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A bus system, including a clock line, a first data line, and a second data line. The bus system further includes an initiator connected to a first end of the clock line, the first data line, and the second data line. The initiator sends a start indication on the clock line and the first data line, sends command bits followed by address bits on the first data line, and sends a stop indication on the clock line and the first data line. The bus system also includes a target connected to a second end of the clock line, the first data line, and the second data line. The target sends target acknowledge information followed by target interrupt information on the second line while the command bits and address bits are sent.
A scalable reconfigurable intelligent surface (RIS) includes a plurality of RIS elements. The RIS elements include: a radio frequency identification (RFID) chip that powers the RIS element; a RFID antenna connected to the RFID chip; a RIS variable impedance controlled by the RFID chip; and a RIS antenna connected to the RIS variable impedance. The plurality of RIS elements produces a reflection beam that may be directed to a specific location. The RFID chip receives steering information to steer the reflection beam.
H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
H01Q 3/34 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means
88.
RELAYING FRAMES BETWEEN DEVICES USING A RELAY DEVICE WITH LOWER MEDIA ACCESS CONTROL FUNCTIONS
Embodiments of relay device, communications system and method are disclosed. In an embodiment, a relay device comprises a wireless transceiver to receive and transmit frames, and a controller operably coupled to the wireless transceiver to process the frames, wherein the controller is configured to receive a frame from the transmitter device, perform a relay operation to relay the frame from the transmitter device to the destination device, wherein the relay device is configured to perform the relay operation using only lower MAC functions, and transmit the frame from the transmitter device to the destination device.
A MEMS device includes a substrate, a set of spring, and a proof mass suspended above and coupled to the substrate by the springs. Each spring includes a corresponding anchor on the substrate and a beam extending away from that anchor. Each beam has a fixed end that is coupled to the anchor by a first linkage at one end of the beam proximal to the anchor and a free end that is coupled to the proof mass by a second linkage at an end of the beam that is distal to the anchor. The anchors are arranged symmetrically around a center of the proof mass. The proof mass translates vertically with respect to the substrate and when a vertical displacement of the proof mass toward the substrate reaches a predefined value, the free end of each spring contacts the substrate and prevents the proof mass from contacting the substrate.
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
An apparatus comprising: a driving circuit; a switchable termination resistance circuit configured to selectively provide a resistance based on an output of the driving circuit; wherein the output of the driving circuit is provided by a parallel arrangement of a first branch having a first switch and a second branch having a second switch, wherein the second branch provides greater current than the first branch, and wherein the driving circuit is configured to provide, in response to an enable signal received at an input of the driving circuit, the output comprising a first current by turning on the second switch for a predetermined time period following the provision of the enable signal to cause the provision of the termination resistance, and, after said predetermined time period, turn off the second switch such that the output comprises a second current, less than the first current.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
91.
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVEGUIDE AND METHOD THEREFOR
A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A controller for a power converter includes a generator module configured to generate a sequence of pulses each having a width defined by a rise moment, R, and fall moment, F, stored in respective RM and FM registers. The sequence of pulses have a repetition rate, T, that is modulated by a repetition period, RP, value stored in a RP register. A memory of the controller has tables of R values, F values and RP values configured to be written into the generator module RM, FM and TM registers respectively. A direct memory access (DMA) module of the controller is configured to write R, F and RP values from the respective memory table into the RM, FM, and TM registers respectively, in response to a DMA trigger. A core coupled to the DMA module is configured to write the R, F and RP values into the memory table.
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
A multidevice package includes upper and lower surfaces with the lower surface disposed beneath a first die forming part of the package. The lower surface includes a first a set of electrical contacts and a recessed region with a second set of electrical contacts configured to allow a second die to be coupled to the lower surface and electrically coupled to the first die via the second set of contacts. The recessed region is sufficiently recessed to allow the package to be coupled to a mounting surface such as a printed circuit board via the first set of contacts while the second die remains suspended above the mounting surface.
A power module may include multiple transistors each respectively having a first current-carrying terminal coupled to a voltage supply, a second current-carrying terminal coupled to an output node, and a control terminal, multiple output driver stages each coupled to the control terminal of a respectively different transistor of the transistors, and a driver module. The driver module may include multiple pre-drivers each coupled to a respectively different output driver stage of the output driver stages and a control module having an input and having multiple outputs coupled to the pre-drivers. The control module may be configured to receive a control signal at the input and to selectively control the pre-drivers to drive at least a subset of the plurality of transistors via the output driver stages based on the control signal.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
B60L 50/51 - Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells characterised by AC-motors
95.
SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND LEAD FRAME
A semiconductor package has top and bottom surfaces and includes a vertical direction extending from the top surface to the bottom surface. The semiconductor package comprises a semiconductor die and a lead frame. At least one of each pair of neighboring leads comprises an elongate lug extending towards the other of the pair of neighboring leads. A region of each lug remote from the lead has a thickness which is smaller than a full thickness of the lead frame. The semiconductor package further comprising molding compound encapsulating the semiconductor die and forming the semiconductor package. The molding compound fills the spaces between the leads and fills spaces separating the die pad from the leads.
A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.
G11C 17/02 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using magnetic or inductive elements
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to generate a frame including a Media Access Control (MAC) header and a security encapsulation for MAC header protection and a transceiver configured to transmit the frame to a second communications device. The security encapsulation includes packet number (PN) information, key identification (ID) information, and message integrity check (MIC) information.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
99.
Field Oriented Control Of Permanent Magnet Synchronous Motor With Constant Power Factor Control Loop
A method for Field Oriented Control (FOC) of a Permanent Magnet Synchronous Motor (PMSM) with a constant Power Factor Control (PFC) Loop includes measuring a rotor position of the PMSM. A plurality of stator voltages of the PMSM is controlled with a required direct (d)-axis current, a required quadrature (q)-axis current, the rotor position and a plurality of measured stator currents of the PMSM in a three-phase stationary reference frame. The required d-axis current is determined with a required power factor, the plurality of measured stator currents transformed into two-phase stationary reference frame, the measured stator currents transformed into a rotational reference frame, and each of a required α-axis voltage and a required β-axis voltage transformed into the two-phase stationary reference frame, wherein a power factor of the PMSM is controlled to be equal to the required power factor.
Embodiments of pin lift detection circuit for a direct current (DC)-DC converter and DC-DC converters are disclosed. In an embodiment, a pin lift detection circuit for a DC-DC converter includes a current source, a switch connecting the current source to an electrical terminal of the DC-DC converter, a resistive divider connected to the switch and to the electrical terminal of the DC-DC converter, an amplifier connected to the resistive divider, a comparator connected to the amplifier and to the resistive divider, a digital filter connected to the comparator and configured to generate a flag signal in response to a disconnection between the electrical terminal of the DC-DC converter and a load of the DC-DC converter, and a timer circuit configured to generate control signals for the switch, the comparator, and the digital filter.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
