A semiconductor device includes a substrate, plugs and a storage node pad structure. The plugs are disposed on the substrate and include first plugs with a conductive material and second plugs with an insulating material. The storage node pad structure is disposed on the plugs and includes first extension pads and at least one second extension pad. The first extension pads have a predetermined first length in a first direction and are separated from each other and arranged as an array along the first direction, being in physical contact with one of the first plugs. The at least one second extension pad has a length greater than the predetermined first length and is in physical contact with at least one of the plugs.
A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.
A semiconductor structure includes a substrate, a first bottom electrode and a second bottom electrode disposed on the substrate, an upper supporting layer extending laterally between the first bottom electrode and the second bottom electrode and directly contacting the first bottom electrode and the second bottom electrode, a cavity between the upper sacrificial layer and the substrate, a capacitor dielectric layer covering along the first bottom electrode and the second bottom electrode, and a conductive material disposed on the capacitor dielectric layer. A portion of the first bottom electrode has a slope profile having a lower end not lower than a lower surface of the upper supporting layer.
A method of forming a photomask includes: providing a target pattern; generating a first offset pattern according to the target pattern and a first offset value; generating a second offset pattern according to the first offset pattern and a second offset value; operating the first offset pattern and the second offset pattern with a Boolean operation to obtain a first assist feature; and outputting the target pattern and the first assist feature to form the photomask. The manufacturing time of the resulting photomask can be shortened and fidelity of patterns produced by the photomask can be improved so as to facilitate transfer of the target pattern to the semiconductor substrate precisely.
A semiconductor device which includes a substrate, storage node pads, a capacitor structure and a supporting structure, and a forming method thereof are disclosed. The substrate includes a cell region and a periphery region. The storage node pads are disposed on the substrate and located in the cell region. The capacitor structure is disposed on the storage node pads and includes bottom electrodes in contact with the storage node pads. The supporting structure is disposed on the storage node pads and interleaved among the bottom electrodes. The supporting structure includes a first supporting layer and a second supporting layer sequentially from bottom to top. The second supporting layer includes a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, and the second supporting layer with the second thickness is disposed between the cell region and the periphery region to provide improved structural support.
In a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, conductive layer structures, plug structures, spacers and stop layers. The plug structures are disposed between two of the conductive layer structures in a second direction perpendicular to the first direction. The spacers are disposed between the conductive layer structures and the plug structures. The stop layers are disposed on the spacers between the conductive layer structures and the plug structures and has a bottommost surface disposed between a bottom surface of the conductive layer structures and a bottom surface of the spacers. The plug structures comprise at least one protrusion member extending from the bottommost surface toward the conductive layer structure and disposed between the stop layer and the substrate. Accordingly, contact area between the plug structures and the substrate can be increased.
A semiconductor device includes a substrate. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially disposed on the substrate. A source structure is formed in the first dielectric layer. A drain structure is formed in the third dielectric layer. A channel structure extends through the second dielectric layer and directly contacts the source structure and the drain structure. A gate structure is disposed at two sides of the channel structure. The gate structure includes a conductive layer and a gate dielectric layer. The gate dielectric layer is along sidewalls and a bottom surface of the conductive layer, and is interposed between the conductive layer and the channel structure and the second dielectric layer.
A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.
The present disclosure relates to a semiconductor device and a fabricating method thereof, includes a substrate, a gate structure, a plug hole, a plug spacer, a metal silicide layer, and a plug. The gate structure is disposed on the substrate. The plug hole is disposed within a dielectric layer to partially extended into the substrate. The plug spacer is disposed on a sidewall of the plug hole to partially expose the substrate. The metal silicide layer is disposed at a bottom of the plug hole, wherein a portion of the substrate is sandwiched between the metal silicide layer and the plug spacer. The plug is disposed in the plug hole to physically contact the portion of the substrate. Accordingly, through forming the plug spacer to precisely define the forming location and the depth of the metal silicide layer, thereby achieving the function on improving the performance of the semiconductor device.
A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 12/00 - Dynamic random access memory [DRAM] devices
11.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a first stacked structure disposed in the semiconductor substrate, and a contact structure. The semiconductor substrate includes a fin-shaped structure. The first stacked structure is disposed straddling the fin-shaped structure, extends in a horizontal direction, and disposed in the cell region and the peripheral region. The first stacked structure includes an electrically conductive layer including a first portion in the cell region and a second portion in the peripheral region, a capping layer disposed on the electrically conductive layer, and a dielectric capping layer disposed on the capping layer and the electrically conductive layer. The dielectric capping layer contacts a top surface of the second portion. The contact structure directly contacts the electrically conductive layer and is electrically connected with the first stacked structure.
A semiconductor device, a method of forming the same and a method of measuring the same are disclosed. The semiconductor device includes a substrate, a first dielectric layer, first alignment marks, a second dielectric layer and second alignment marks. The first dielectric layer is arranged on the substrate, the first alignment marks are arranged in the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second alignment marks are arranged in the second dielectric layer and spaced apart from each other, each having a stepped structure. The first and second alignment marks do not interfere with each other. A precisely positioned interconnection structure can thus be defined in the semiconductor device.
A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrally-formed contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.
A semiconductor device includes a substrate, a connecting layer on the substrate, and a capacitor structure arranged on the connecting layer. The connecting layer includes an array of connecting pads, a peripheral structure adjacent to the array of connecting pads, and a plurality of first extending pads arranged between the peripheral structure and the array of connecting pads. The connecting pads respectively have one of the bottom electrodes of the capacitor structure disposed thereon. The first extending pads respectively have two of the bottom electrodes of the capacitor structure disposed thereon to reinforce the peripheral portions of the capacitor structure.
A contact pad structure and a manufacturing method thereof are disclosed in the present invention. The contact pad structure includes a substrate, a first dielectric layer, a second dielectric layer, first contact pads, an etching stop layer, a first void, and a second void. The first contact pads are disposed on a first region of the substrate. The first dielectric layer is disposed on the substrate, covers the first contact pads, and includes a recess located between two adjacent first contact pads. The etching stop layer is disposed on the first dielectric layer and partially located in the recess. The second dielectric layer is disposed on the etching stop layer and partially located in the recess. The first void is disposed in the etching stop layer and located in the recess. The second void is disposed in the second dielectric layer and located in the recess.
The present disclosure provides a semiconductor memory device and a method of fabricating the same, including a substrate, a plurality of bit lines, a bit line contact, a spacer, a liner layer, and a storage node contact. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one active area. The spacer is disposed on sidewalls of each of the bit lines and the bit line contact. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, between the bit line contact and the one of the bit lines in an extending direction of the bit lines. The storage node contact and the bit lines are alternately arranged with each other.
The present disclosure provides a semiconductor device and a fabricating method thereof includes a source structure, a drain structure, a gate structure, a bottom dielectric layer, a gate dielectric layer, a channel structure, and a metal nitride layer. The source structure and the drain structure are stacked in a vertical direction, and the gate structure is between the drain structure and the source structure. The bottom dielectric layer is disposed between the drain structure and the source structure. The channel structure is disposed between the drain structure and the source structure and is electrically connected the drain structure and the source structure, and the channel structure is partially disposed in the gate structure. The gate dielectric layer is disposed between the channel structure and the gate structure. The metal nitride layer is disposed between the gate dielectric layer and the gate structure.
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
Disclosed are a semiconductor device and a method for preparing a semiconductor device. The semiconductor device is provided with contact pad structures in contact holes. Each of the contact pad structures is configured to comprise a first contact pad, a second contact pad adaptively covering the first contact pad, and a contact plug located on the second contact pad. The first contact pad is in full contact with an active region in a substrate. In addition, an air gap is formed between the first contact pad and a side wall on a side of the respective contact hole.
A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, a plurality of active areas, a shallow trench isolation and a plurality of buried gates. The active areas are formed on the substrate, wherein each active area includes a semiconductor layer, and a first interface exists between the semiconductor layer and the substrate. The shallow trench isolation is disposed on the substrate and surrounds the active areas. Each buried gates is buried in one of the plurality of active areas and disposed above the first interface. Accordingly, the isolation effect between the active areas can be enhanced on the condition of maintaining a certain level of integration. Meanwhile, the possible device defects derived from the raised level of integration can be ameliorated.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
An input data pre-alignment circuit includes a first amplifier, a second amplifier, a clock control unit, a feedback signal generator, and a signal alignment unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The clock control unit is used for receiving pair-wised clock signals. The feedback signal generator is coupled to the second amplifier and the clock control unit. The signal alignment unit is coupled to the second input terminal of the first amplifier, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the feedback signal generator.
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
Present invention relates to a semiconductor device and a method of fabricating the same including a substrate, a plurality of word lines, a dielectric layer, and a plurality of bit lines. The word lines are embedded in the substrate to intersect with an active structure and a shallow trench isolation within the substrate. The dielectric layer covers the word lines. The bit lines are disposed over the substrate, along a first direction. The bit lines include at least one first bit line and a plurality of second bit lines, with the first bit line overlapping the active structure and the shallow trench isolation at the same time, and physically contacting the dielectric layer through a bottom surface thereof without being electrically connected to the active structure, and with each of the second bit line including a plurality of bit line contacts disposed therebelow, to directly contact the active structure.
A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a semiconductor substrate, bit line structures, isolation structures, a storage node contact structure, and first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends in a first direction, and the bit line structures are arranged in a second direction. The isolation structures are located between the bit line structures adjacent to one another. The storage node contact structure is located between two adjacent bit line structures and located between two adjacent isolation structures in the first direction. The storage node contact structure includes four corner portions. The first voids are disposed in the storage node contact structure, and the first voids are located in at least two of the four corner portions.
A semiconductor memory device and a method of forming the same include a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance.
A semiconductor memory device includes a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance.
A semiconductor structure includes a substrate having a peripheral region and a memory region. A plurality of bit lines are disposed on the substrate, extending along a first direction to pass through the peripheral region and the memory region, and arranged in parallel along a second direction, wherein the first direction and the second direction are is perpendicular. A plurality of insulating plugs and first spacer structures are alternately arranged along the first direction between the bit lines on the peripheral region. A plurality of conductive plugs and second spacer structures are alternately arranged along the first direction between the bit lines on the memory region. The first spacer structures and the second spacer structures comprise a same material, and along the first direction, widths of the second spacer structures are smaller than widths of the first spacer structures.
A semiconductor structure, including a plurality of metal patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the metal patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and one short axis of the first outer line, one short axis of the central line and one short axis of the second outer line are misaligned along the first direction.
A method for fabricating a semiconductor memory device includes: forming word lines and bit lines; forming filling patterns between the bit lines and at ends of the bit lines, and forming first gaps surrounded by the filling patterns and the bit lines; depositing an insulating material, to fill up the first gaps surrounded by the filling patterns and the bit lines, and forming cavities surrounded by the insulating material in each of the first gaps respectively; etching the insulating material to form a strip-shaped isolation structure and columnar isolation structures, where the cavity of the strip-shaped isolation structure is exposed to form a seam; after etching the insulating material, removing a portion of the filling patterns to form second gaps, where the second gaps are surrounded by the columnar isolation structures and the bit lines; and depositing a conductive material to fill up the second gaps and the seam concurrently.
A reference voltage controlled equalization input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used for receiving the reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit.
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end portion of the metal silicide layer is clamped between the second spacer and the first spacer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
32.
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor memory device includes a substrate, a plurality of bottom electrodes arranged on the substrate along a row direction and a column direction to form an array. The row direction and the column direction are perpendicular. A supporting layer is disposed on the substrate and in direct contact with the bottom electrodes to support the bottom electrodes. At least a first slit, at least a second slit, and at least a third slit that extend along different directions are formed in the supporting layer and partially expose sidewalls of the bottom electrodes.
The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.
The present disclosure provides a semiconductor device and a fabricating method thereof, and the semiconductor device includes a substrate, a capacitor structure, a supporting structure and a supplementary layer. The capacitor structure is disposed on the substrate, and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The supporting structure is disposed between adjacent ones of the columnar bottom electrodes, and the supporting structure includes a first supporting layer and a second supporting layer stacked from bottom to top. The supplementary layer is disposed between each of the columnar bottom electrodes and the supporting structure, to directly in contact with the first supporting layer, the second supporting layer, and sidewalls of the columnar bottom electrodes.
A self-controlled input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The feedback signal generator is coupled to the second amplifier. The gain control unit is coupled to the feedback signal generator, the second input terminal of the first amplifier, the first output terminal of the first amplifier, and the second output terminal of the first amplifier.
The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a capacitor structure, a sidewall high-k dielectric layer and a supporting structure. The capacitor structure is disposed on the substrate, and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein each of the columnar bottom electrodes includes a recess on the top. The sidewall high-k dielectric layer is disposed on two opposite sidewalls of each of the columnar bottom electrodes, wherein a portion of the capacitor dielectric layer is filled in the recess and sandwiched between the columnar bottom electrodes and the sidewalls high-k dielectric layer. The supporting structure is disposed between the adjacent ones of the columnar bottom electrodes, and includes a first supporting layer and a second supporting layer stacked from bottom to top.
A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.
A semiconductor memory device includes: a substrate; bit lines disposed on the substrate and extending along a first direction; a strip-shaped isolation structure, where the upper portion of the strip-shaped isolation structure includes a seam; a conductive residue disposed in the seam; columnar isolation structures disposed between the bit lines and separated with each other; conductive plugs disposed between the bit lines and separated with each other, where the conductive residue and the conductive plugs include the same conductive material.
The invention discloses a semiconductor device including a substrate, a stacked structure, a trench, a channel structure, and a barrier layer. The stacked structure is disposed on the substrate, wherein the stacked structure includes a first metal layer, at least one stacked layer and a second metal layer from bottom to top. The trench is disposed in the stacked structure. The channel structure is disposed in the trench, wherein the channel structure fills up the trench. The barrier layer is disposed in the second metal layer, wherein the trench penetrates through the barrier layer. Therefore, the barrier layer can effectively prevent the diffusion of metal ions in the second metal layer from polluting the channel structure in the trench, and the structural reliability and performance of the semiconductor device can be improved.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
41.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof are disclosed in the present invention. The semiconductor device includes a source structure; a gate structure disposed above the source structure; a first opening penetrates through the gate structure in a vertical direction; a semiconductor structure; a gate dielectric layer; an insulation structure; and a void. The semiconductor structure is partially disposed in the first opening, and at least a portion of the gate structure is located at two opposite sides of the semiconductor structure in a horizontal direction. The gate dielectric layer is disposed in the first opening and located between the semiconductor structure and the gate structure. At least a portion of the insulation structure is disposed in the first opening, at least a portion of the semiconductor structure is located between the insulation structure and the gate dielectric layer, and the void is located in the insulation structure.
A self-controlled equalization circuit includes a first amplifier, a second amplifier, a feedback signal generator, a frequency delay signal generator, a feedback enabling unit, an equalization control unit, and a gain control unit. The first amplifier includes a first input terminal and a second input terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The frequency delay signal generator is used for receiving a frequency signal. The feedback enabling unit is coupled to the output terminal of the frequency delay signal generator and the feedback signal generator. The equalization control unit is coupled to the feedback signal generator, the feedback enabling unit, and the first amplifier. The gain control unit is coupled to the feedback signal generator, the second input terminal of the first amplifier, and output terminals of the first amplifier.
The invention discloses a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, storage node pads, a capacitor structure and a supporting structure. The storage node pads are disposed on the substrate. The capacitor structure is disposed on the storage node pads and includes a plurality of capacitors. The capacitor structure includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, wherein the top portion of the bottom electrode layer is provided with a recess. The supporting structure includes a plurality of first supporting layers and a plurality of second supporting layers from bottom to top, and the supporting structure connects two adjacent capacitors, wherein the recesses face each second supporting layer respectively.
A three-dimensional memory device includes a substrate and a stack structure including alternating conductive layers and dielectric layers disposed on the substrate, and a memory string structure extending vertically through the stack structure. The memory string structure includes a conductive pillar and a storage layer disposed between the conductive pillar and the stack structure and surrounding the conductive pillar. The storage layer includes a plurality of first protruding portions at interfaces between the conductive layers and the dielectric layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A method for forming a metal oxide semiconductor device includes performing a first atomic layer deposition cycle M times to form a first stacked channel layer and a second atomic layer deposition cycle N times to form a second stacked channel layer on the first stacked channel layer. M and N are positive integers. The first stacked channel layer and the second stacked channel layer have different metal compositions and collectively form the channel layer of the metal oxide semiconductor device.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
The present disclosure provides a semiconductor device and a fabricating method thereof, and the semiconductor device includes a substrate, a plurality of conductive pads, and a plurality of conductive columns. The conductive pads are separately disposed in a first insulating layer, over the substrate. The conductive columns are separately disposed in a second insulating layer, individually contacting each of the conductive pads. The second insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked on sidewalls of the conductive columns, wherein the second dielectric layer physically contacts the first dielectric layer, the conductive pads and the third dielectric layer at the same time. The second insulating layer is allowable to avoid the short-circuit issue caused by excessively lateral etching, thereby improving the structural reliability and the performances.
A method for forming a semiconductor structure for a memory device, including providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein, forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure, and forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer.
The slew rate control circuit includes a slew rate control unit, a capacitive delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit is used for receiving a plurality of control voltages. The capacitive delay unit is coupled to the slew rate control unit for receiving an input signal. The delay unit is coupled to the capacitive delay unit. The first output unit and the second output unit are coupled to the capacitive delay unit. The third output unit is coupled to the delay unit. The first output signal and the second output signal are two signals without controllable slew rates. A slew rate of the third output signal is controlled by the capacitive delay unit. A slew rate of the fourth output signal is controlled by the capacitive delay unit and the delay unit.
H03K 5/06 - Shaping pulses by increasing durationShaping pulses by decreasing duration by the use of delay lines or other analogue delay elements
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
49.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.
The present disclosure provides a method of fabricating a semiconductor device, which includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active area, a second active area disposed outside the first active area, and a third active area disposed outside the second active area. The shallow trench isolation is disposed in the substrate to surround the active structure. Through the second active area and the third active of the active structure, the structural stability of the semiconductor device may be enhanced to improve the stress around the semiconductor device, thereby preventing from structural collapse or deformation.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.
The present disclosure provides a semiconductor device and a method of fabricating the same, which includes a substrate, a resistor structure, a bit line structure, and a bit line contact. The substrate has an active area and a plurality of isolating regions. The resistor structure is disposed on the isolating regions, and includes a first semiconductor layer, a first capping layer, a first spacer. The bit line structure is disposed on the substrate to intersect the active area and the isolating regions, and includes a second semiconductor layer, a first conductive layer, a second capping layer, and a second spacer. The bit line contact is disposed in the substrate to partially extend into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer include a same semiconductor material.
The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts directly contact the active areas and include a plurality of first plugs, with each first plug including an insulating material and a conductive material stacked sequentially from bottom to top. Within the semiconductor memory device, at least one active area simultaneously contacts two of the first plugs, or a storage node pad physically contacts at least two of the first plugs. Thus, the present disclosure is beneficial on forming the semiconductor memory device with better component reliability.
A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.
A semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. The capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. The lower portions of the capacitors near the edge of the array region are tilted. The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. The stress in the capacitor array structure of the semiconductor memory device may be reduced.
A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
The invention discloses a pattern layout of an active region and a forming method thereof. The feature of the present invention is that in the sub-pattern unit, an appropriate active area pattern is designed according to the bit line pitch (BLP) and the word line pitch (WLP), the active area pattern is a stepped pattern formed by connecting a plurality of rectangular patterns in series, and the active area pattern is arranged along a first direction, the angle between the first direction and the horizontal direction is A. In addition, according to the angle A, the shortest distance (P) between adjacent stepped patterns, the length and width of sub-pattern units, etc., The positions of some stepped active area patterns are adjusted, so that the distance between multiple active area patterns can be consistent when being repeatedly arranged, thereby improving the uniformity of overall pattern distribution.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H01L 23/528 - Layout of the interconnection structure
G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
59.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an insulating layer, a plurality of bit lines, and a bit line contact. The insulating layer is disposed on the substrate, the bit lines are disposed on the insulating layer, and the bit line contact is disposed between the bit lines and the substrate, to electrically connect the bit lines, wherein the bit line contact comprises a first conductive layer and a first oxidized interface layer, and a bottommost surface of the first oxidized interface layer is lower than a top surface of the insulating layer. Through these arrangements, the semiconductor device includes the bit line contact having a composite semiconductor layer, which is allowable to improve the structural reliability of the bit lines and the bit line contacts, thereby achieve better performance.
A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a substrate, trenches, an oxide semiconductor layer, a gate dielectric layer, and word line structures. The substrate includes active regions and an isolation structure located between the active regions. The active regions contain silicon. The trenches are disposed in the active regions and the isolation structure. The oxide semiconductor layer is disposed in each trench. The gate dielectric layer is disposed on the oxide semiconductor layer and located in each trench. The word line structures are disposed on the gate dielectric layer and located in the trenches, respectively. At least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each word line structure.
A method for forming a semiconductor structure includes providing a substrate, forming an upper sacrificial layer, an upper supporting layer and a hard mask layer on the substrate, forming bottom electrodes through the upper sacrificial layer, the upper supporting layer and the hard mask layer, forming at least an opening between the bottom electrodes and through the hard mask layer and the upper supporting layer to partially expose the upper sacrificial layer. A portion of at least one of the bottom electrodes exposed from the opening has a slope profile, and a lower end of the slope profile is not lower than a lower surface of the upper supporting layer. The method further includes removing the upper sacrificial layer from the opening to form a cavity, and forming a capacitor dielectric layer along the bottom electrodes and a conductive material filling the cavity.
The present disclosure provides a semiconductor memory device and a method of fabricating the same, with the semiconductor memory device including a substrate, a plurality of capacitor structures, a stress insulating layer, and at least one interface layer. The capacitor structures are separately disposed on the substrate, and each of the capacitor structures includes a plurality of capacitors. The stress insulating layer is disposed on the substrate to cover the capacitor structures. The interface layer is disposed within the stress insulating layer, between any two adjacent ones of the capacitor structures, wherein a tip portion of the at least one interface layer is higher than a top surface of each of the capacitor structures. In this way, the stress mode of the substrate may be adjusted through disposing the interface layer, so as to achieve the effect of eliminating redundant stress, and to improve the structural reliability of the device.
The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of storage node pads, a supporting structure, and a capacitor structure. The storage node pads are disposed on the substrate. The supporting structure is disposed on the substrate and includes a first supporting layer and a second supporting layer from bottom to top. The capacitor structure is disposed on the substrate, and the capacitor structure includes columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer stacked from bottom to top, wherein the columnar bottom electrodes include a first columnar bottom electrode having a symmetric columnar structure and a second columnar bottom electrode having an asymmetric columnar structure, and the first columnar bottom electrode and the second columnar bottom electrode respectively include at least one horizontal extending portion along a horizontal direction.
A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
65.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
The present disclosure provides a semiconductor device and a fabricating method thereof, including a substrate, a supporting structure and a capacitor structure. The supporting structure is disposed on the substrate, and the supporting structure includes a first supporting layer and a second supporting layer. The capacitor structure is disposed on the substrate and includes a plurality of bottom electrode layers. Each of the bottom electrode layers includes two portions extended upwardly, and one of the two portions has a first thickness between the substrate and the first supporting layer, and a second thickness between the first supporting layer and the second supporting layer, and the first thickness is greater than the second thickness.
The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a bit line structure and a resistor structure. The substrate has a plurality of active areas and an isolating region. The resistor structure includes a first semiconductor layer and a first capping layer from bottom to top. The bit line structure includes a second semiconductor layer, a first conductive layer, and a second capping layer from bottom to top, wherein the first semiconductor layer and the second semiconductor layer include coplanar top surface and a same semiconductor material. In this way, the resistor formed thereby is allowable to obtain structural reliability and stable surface resistance, under a simplified process flow.
A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.
The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
The present disclosure provides a semiconductor memory structure and a method of fabricating the same includes a substrate; at least one first groove disposed on an upper surface of the substrate, with an edge corner of a top portion of the first groove being arc-shaped; a first dielectric layer disposed along an inner wall of the first groove; a second dielectric layer formed on a surface of the first dielectric layer, to fill up the first groove, wherein a top portion of the first dielectric layer is lower than a top portion of the second dielectric layer and an upper surface of the substrate, and a first recess is formed between the second dielectric layer and the substrate; and a metal filling layer disposed in the first recess, to fill in a partial space of the first recess.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor device includes a substrate having a plurality of parallel active regions, an isolation structure in the substrate to separate the active regions, a buried word line disposed in the substrate and cutting through the isolation structure and the active regions, and a dielectric insert structure disposed in the substrate, directly under the buried word line and between end portions of adjacent two of the active regions. A bottom surface of the dielectric insert structure is lower than a bottom surface of the isolation structure.
H01L 23/528 - Layout of the interconnection structure
H01L 27/108 - Dynamic random access memory structures
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.
The present disclosure provides a semiconductor device and a method of fabricating the same, which includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active area, a second active area disposed outside the first active area, and a third area disposed outside the second active area. The shallow trench isolation is disposed in the substrate to surround the active structure. Through the second active area and the third active of the active structure, the structural stability of the semiconductor device may be enhanced to improve the stress around the semiconductor device, thereby preventing from structural collapse or deformation.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.
The present disclosure provides a three-dimensional memory device and a method of fabricating the same, which includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangements, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 12/00 - Dynamic random access memory [DRAM] devices
The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.
The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and at least one second word line arranged by a second pitch, and the second pitch is greater than the first pitch.
The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.
A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and an interconnection structure on the second dielectric layer. The interconnection structure includes at least two lateral extending portions on the second dielectric layer, and a U-shaped portion through the second dielectric layer and a portion of the first dielectric layer and connected between adjacent ends of the two lateral extending portions.
A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.
A semiconductor structure includes an array of active patterns, a peripheral pattern around the array of active patterns, and at least a branch pattern connected to an inner edge of the peripheral pattern. The active patterns respectively extend along a first direction and are arranged end-to-end along the first direction and side-by-side along a second direction that is different form the first direction. The branch pattern extends along the first direction. An end portion of the branch pattern and an end portion of one of the active patterns that is immediately side-by-side next to the branch pattern are flush along the second direction.
A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.
A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 12/00 - Dynamic random access memory [DRAM] devices
The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.
The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.
The present disclosure relates to a semiconductor memory device and a fabricating method thereof, includes a substrate, a plurality of gate structures, a plurality of isolation fins, at least one bit line, and a plug. The gate structures are disposed in the substrate, being parallel with each other along a first direction. The isolation fins are disposed on the substrate, parallel with each other and extending along the first direction, over each of the gate structures respectively. The bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The bit line includes a plurality of pins extending toward the substrate, being alternately arranged with the isolation fins along the second direction. The plug is disposed on the substrate, being alternately with the bit line in the first direction.
A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
A three-dimensional memory device includes a staircase structure comprising steps respectively comprising a conductive layers and a dielectric layer. A sidewall of the conductive layer is recessed from a sidewall of the dielectric layer to form a recess that exposes a portion of a bottom surface of the dielectric layer.
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
91.
Semiconductor memory device and method for forming the same
A semiconductor memory device including a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance.
The present invention discloses a semiconductor memory device and a forming method thereof. The semiconductor memory device includes a substrate, a plurality of bit lines, a strip-shaped isolation structure, a conductive residue, a plurality of columnar isolation structures and a plurality of conductive plugs. The bit lines are located on the substrate and extend along the first direction. The strip-shaped isolation structure is located at the ends of the bit lines and extends along the second direction, and the strip-shaped isolation structure includes a seam. In particular, the conductive residue is disposed in the seam. The columnar isolation structures are separated from each other and disposed between the bit lines. The conductive plugs are separated from each other and disposed between the bit lines, in which the conductive plugs and the conductive residue include the same conductive material.
The present disclosure provides a semiconductor device and a method of fabricating the same, and the semiconductor device includes a substrate, active areas, and an isolation structure. The active areas are parallel and separately disposed with each other in the substrate, and each of the active areas includes an active fin and active ends disposed at two sides of the active fin. The active fin and the active ends include different materials. The isolation structure is disposed in the substrate to surround the active areas. With this arrangement, the extending area of the active areas may be improved, so as to make sure the storage node contacts formed subsequently may directly and stably contact with the active areas.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.
The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.
A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.
The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
99.
Semiconductor device and method for forming the same
A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.
A semiconductor memory device includes a substrate and a capacitor. The capacitor is disposed on the substrate, and the capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer sequentially stacked from bottom to top and an aluminum-containing insulation layer. The aluminum-containing insulation layer includes aluminum titanium nitride or aluminum oxynitride, and is in direct contact with the capacitor dielectric layer and disposed between the bottom electrode layer and the top electrode layer. Therefore, the semiconductor memory device may effectively improve the leakage current.
