Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
A control circuit is configured to interact with a memory device to perform read and write operation at the memory device where the memory device includes memory transistors organized in a set of tiles. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, each active read request being addressed to a respective tile in the set of tiles; a write queue configured to store active write requests for writing data to the memory device, each active write request being addressed to a respective tile in the set of tiles; and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize a number of the active write requests in the write queue that are addressed to different tiles of the memory device.
Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules, each memory module including one or more quasi-volatile memory circuits interconnected to at least one memory controller where each memory module includes a set of memory ports; a DIMM controller and processor in communication with each of the memory modules; and multiple processor ports to be coupled to respective processing units external to the memory system. The memory ports of each memory module are coupled to the processor ports and to the DIMM controller and processor so that each memory module is accessible by respective processing units that are coupled to the processor ports and by the DIMM controller and process.
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/92 - Capacitors with potential-jump barrier or surface barrier
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
7.
MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL-ALL-AROUND FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION
A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
8.
Memory Structure Of Three-Dimensional NOR Memory Strings Of Channel-All-Around Ferroelectric Memory Transistors And Method Of Fabrication
A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processors. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
10.
THREE-DIMENSIONAL NOR MEMORY ARRAY OF THIN-FILM FERROELECTRIC MEMORY TRANSISTORS IMPLEMENTING PARTIAL POLARIZATION
A memory structure including three-dimensional NOR memory strings and method of operation is disclosed. In some embodiments, the memory device implements partial polarization to provide a reference signal for read operation. The reference signal realizes a third logical state distinguishable from the first and second logical stages in the ferroelectric memory transistor, such as associated with the program and erase states. In another embodiment, the memory device provides a reference signal for read operation by averaging a first signal associated with a program state and a second signal associated with an erased state of the ferroelectric memory transistor. In some embodiments, the memory device implements one or more partial polarization states to provide a multi-level memory cell with more than one logical bit stored in each memory cell.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
11.
THREE-DIMENSIONAL NOR MEMORY ARRAY OF THIN-FILM FERROELECTRIC MEMORY TRANSISTORS IMPLEMENTING PARTIAL POLARIZATION
A memory structure including three-dimensional NOR memory strings and method of operation is disclosed. In some embodiments, the memory device implements partial polarization to provide a reference signal for read operation. The reference signal realizes a third logical state distinguishable from the first and second logical stages in the ferroelectric memory transistor, such as associated with the program and erase states. In another embodiment, the memory device provides a reference signal for read operation by averaging a first signal associated with a program state and a second signal associated with an erased state of the ferroelectric memory transistor. In some embodiments, the memory device implements one or more partial polarization states to provide a multi-level memory cell with more than one logical bit stored in each memory cell.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
G11C 16/26 - Sensing or reading circuitsData output circuits
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory its, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
14.
MEMORY ARRAY OF THREE-DIMENSIONAL NOR MEMORY STRINGS WITH WORD LINE SELECT DEVICE
A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
15.
HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY
A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
G06F 3/06 - Digital input from, or digital output to, record carriers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
16.
MEMORY ARRAY OF THREE-DIMENSIONAL NOR MEMORY STRINGS WITH WORD LINE SELECT DEVICE
A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
17.
FABRICATION METHOD FOR A THREE-DIMENSIONAL MEMORY ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS USING HIGH-ASPECT-RATIO LOCAL WORD LINE DAMASCENE PROCESS
A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a high aspect-ratio damascene process to form local word line structures that extends through the multiple layers of the three-dimensional memory structure. In particular, the high aspect-ratio local word line damascene process forms the gate stack layers, including the channel layer, the gate dielectric layer and the gate conductor layer, in the same sequence of additive deposition processes without any of the gate stack layers being subjected to any intervening etching process. In this manner, the integrity of the gate stack layers and their interfaces are well preserved and the transistor characteristics of the ferroelectric storage transistors are enhanced.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
18.
Quasi-volatile memory device with a back-channel usage
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
19.
Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
20.
Memory circuit, system and method for rapid retrieval of data sets
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/92 - Capacitors with potential-jump barrier or surface barrier
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
21.
FABRICATION METHOD FOR A THREE-DIMENSIONAL MEMORY ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL
A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a liner underlayer in the deposition process of the channel layer where the liner underlayer provides a uniform surface for the deposition of the channel layer and also serves as an etch stop layer in the subsequent metal replacement process. In another embodiment, the fabrication process applies a liner layer in vertical shafts during the local word line process to reduce or eliminate irregular features in the local word line structures, thereby enhancing the electrical characteristics and reliability of the memory arrays thus formed.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A method and system for building a block data transfer (BT) DRAM provides a solution to fix the performance gap between memory and processor. The data conversion time per word between the analog circuits and the digital circuits inside the BT DRAM is smaller than the processor clock cycle time, that enables the average data transfer speed of a BT DRAM to match to the operation speed of a processor. When continuously transferring a plurality of data blocks, a BT DRAM can achieve a close-to-zero-latency performance and is completely self-refreshing.
A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.
A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.
A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests, a write queue configured to store active write requests, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device. In other embodiments, a memory system includes a control circuit configured to interact with a memory device to perform read and write operations implements virtual memory bank addressing.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
A memory device includes: (a) one or more memory circuits having physical memory pages identified by physical page addresses, each physical memory page being provided to store a memory page; and (b) a control circuit configured for managing read or write operations in each memory circuit. The control circuit manages both a wear-leveling scheme and read and write operations in the memory circuits.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
30.
Memory controller including a write staging buffer to manage write requests for a high capacity memory circuit with large number of independently accessible memory banks
A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.
Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
32.
Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and having a set of memory ports. The memory system includes a first processor port, a second processor port, and one or more DIMM interface ports to be coupled to respective processors for providing access to the set of memory modules. In another embodiment, an artificial intelligence (AI) computing system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and an arithmetic function block performing multiply and accumulate functionalities using data stored in the memory modules. The set of memory modules are accessed to perform read, write and erase memory operations in a rotating manner in each computing cycle.
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 23/528 - Layout of the interconnection structure
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
39.
MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREFOR
A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H01L 23/528 - Layout of the interconnection structure
A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
41.
Memory circuit, system and method for rapid retrieval of data sets
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/92 - Capacitors with potential-jump barrier or surface barrier
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
42.
MEMORY STRUCTURE INCLUDING HIGH DENSITY THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC STORAGE TRANSISTORS AND METHOD OF FABRICATION
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The ferroelectric storage transistors are junctionless field-effect transistors having a ferroelectric polarization layer formed adjacent a semiconductor oxide layer as the channel region. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The storage transistors can be charge-trapping type storage transistors or ferroelectric storage transistors. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process. In some embodiments, the memory structure includes first and second semiconductor layers and respective first and second conductive layers forming the source and drain regions, which are spaced apart by a channel spacer dielectric layer. Each conductive layer is formed between the respective semiconductor layer and the channel spacer dielectric layer.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
44.
High capacity memory circuit with low effective latency
A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G06F 3/06 - Digital input from, or digital output to, record carriers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
45.
MEMORY STRUCTURE INCLUDING THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process. In some embodiments, the ferroelectric storage transistors are junctionless field-effect transistors (FeFETs) having a ferroelectric polarization layer as the gate dielectric layer formed adjacent a semiconductor oxide layer as the channel region.
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
H01L 27/11592 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the peripheral circuit region
46.
Device with embedded high-bandwidth, high-capacity memory using wafer bonding
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process. In some embodiments, the ferroelectric storage transistors are junctionless field-effect transistors (FeFETs) having a ferroelectric polarization layer as the gate dielectric layer formed adjacent a semiconductor oxide layer as the channel region.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are manufactured in a process that includes forming operational trenches for vertical local word lines and forming auxiliary trenches to facilitate back-alley metal replacement and channel separation by a backside selective etch process. In some embodiments, the ferroelectric storage transistors are junctionless field-effect transistors (FeFETs) having a ferroelectric polarization layer as the gate dielectric layer formed adjacent a semiconductor oxide layer as the channel region. In some embodiments, ferroelectric storage transistors in the memory stacks are isolated by air gap cavities.
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11587 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the top-view layout
49.
Methods for fabricating a 3-dimensional memory structure of nor memory strings
A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor devices; semiconductor chips; semiconductor chipsets; integrated circuits and integrated circuit modules; none of the foregoing to include optical media containing prerecorded audiovisual recordings, informational, educational or entertainment content, or magnetic media containing prerecorded audiovisual recordings, informational, educational or entertainment content
54.
MEMORY SYSTEM IMPLEMENTING WRITE ABORT OPERATION FOR REDUCED READ LATENCY
A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/25 - Testing of logic operation, e.g. by logic analysers
G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 16/08 - Address circuitsDecodersWord-line control circuits
In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
56.
MEMORY DEVICE INCLUDING ARRANGEMENT OF INDEPENDENTLY AND CONCURRENTLY OPERABLE TILES OF MEMORY TRANSISTORS
In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.
In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
59.
THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line, the common source line and the common bit line formed on a first side of the channel region and the ferroelectric gate dielectric layer and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes formed on a second side, opposite the first side, of the ferroelectric gate dielectric layer.
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
H01L 27/11592 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the peripheral circuit region
60.
THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL IN A CHANNEL LAST PROCESS
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/11587 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the top-view layout
H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/11592 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the peripheral circuit region
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/92 - Capacitors with potential-jump barrier or surface barrier
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
62.
Staggered word line architecture for reduced disturb in 3-dimensional nor memory arrays
A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
63.
Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11585 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS]
66.
Cool electron erasing in thin-film storage transistors
A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Semiconductor memory systems and architectures for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, a memory processor array includes an array of memory cubes, each memory cube in communication with a processor mini core to form a computational memory. In another embodiment, a memory system includes processing units and one or more mini core-memory module both in communication with a memory management unit. Mini processor cores in each mini core-memory module execute tasks designated to the mini core-memory module by a given processing unit using data stored in the associated quasi-volatile memory circuits of the mini core-memory module.
Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
70.
3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS
Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
71.
THIN FILM STORAGE TRANSISTOR WITH SILICON OXIDE NITRIDE CHARGE TRAPPING LAYER
A thin-film storage transistor includes a charge storage film provided between a channel region and a gate conductor where the charge storage film includes a tunneling dielectric layer formed adjacent the channel region and a charge trapping layer formed adjacent the tunneling dielectric layer. In some embodiments, the charge trapping layer is a layer including silicon, silicon oxide and silicon nitride materials. In one embodiment, the charge trapping layer is a layer including a mixture of silicon, silicon oxide and silicon nitride materials, where the silicon oxide and silicon nitride may or may not be their respective stoichiometric compounds.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A method for forming a three-dimensional memory structure above a semiconductor substrate includes forming two or more active stack sections, each formed on top of each other and separated by a dielectric buffer layer, where each active stack section includes multilayers separated by isolation dielectric layers and trenches with shafts filled with a sacrificial material. After the multiple active stack sections are formed, the method removes the sacrificial material in the shafts and removes portions of the dielectric buffer layer between shafts of adjacent active stack sections. The method fills the openings with a gate dielectric layer and a gate conductor. In some embodiments, the gate dielectric layer is discontinuous in the shaft over the depth of the multiple active stack sections.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Carbon has many advantageous uses as a sacrificial material in the fabricating thin-film storage transistors, such as those organized as NOR memory strings. In one implementation, the carbon layers are replaced by heavily doped n-type polysilicon source and drain regions at a late step during device fabrication. As a result, many high temperature steps within the fabrication process may now be carried out without concern for thermal diffusion from the heavily doped polysilicon, thus allowing phosphorus to be used as the n-type dopant.
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
74.
Three-dimensional memory structure fabrication using channel replacement
A process for fabricating a three-dimensional NOR memory string of storage transistors implements a channel-last fabrication process with channel replacement using silicon germanium (SiGe). In particular, the process uses silicon germanium as a sacrificial layer, to be replaced with the channel material after the charge-storage layer of the storage transistors is formed. In this manner, the channel region is prevented from experiencing excessive high-temperature processing steps, such as during the annealing of the charge-storage layer.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
75.
Methods for forming multilayer horizontal NOR-type thin-film memory strings
Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.
A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical "1" step and write logical "0" step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
79.
THIN-FILM STORAGE TRANSISTOR WITH FERROELECTRIC STORAGE LAYER
According to one embodiment of the present invention, a storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset relative to a ntype silicon conduction band that is less than the lowering of the tunneling barrier in the 10 tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band offset of the charge-trapping layer is selected to have a value between -1.0 eV and 2.3 eV.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
81.
Memory interface with configurable high-speed serial data lanes for high bandwidth memory
A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
82.
QUASI-VOLATILE MEMORY WITH REFERENCE BIT LINE STRUCTURE
A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
83.
3-dimensional nor strings with segmented shared source regions
A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 19/1776 - Structural details of configuration resources for memories
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
85.
Memory device including reference bit line for increasing read operation accuracy
A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.
H10B 43/23 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
G11C 8/14 - Word line organisationWord line lay-out
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
86.
VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS AND FABRICATION THEREOF
A VNOR memory string includes: (a) first and second pillars embedded in multiple composite layers, each composite layer comprising an insulator layer and a conductor layer, the first and second pillars each comprising a first semiconductor material of a first conductivity; (b) a second semiconductor layer of a second conductivity type opposite the first conductivity type on the outside of third pillar also embedded in the composite layers, the third pillar contacting both the first and second pillars; and (c) a storage layer provided between the second semiconductor layer and each of the conductor layer in the composite layers.
A VNOR memory string includes: (a) first and second pillars embedded in multiple composite layers, each composite layer comprising an insulator layer and a conductor layer, the first and second pillars each comprising a first semiconductor material of a first conductivity; (b) a second semiconductor layer of a second conductivity type opposite the first conductivity type on the outside of third pillar also embedded in the composite layers, the third pillar contacting both the first and second pillars; and (c) a storage layer provided between the second semiconductor layer and each of the conductor layer in the composite layers.
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
88.
BIT LINE AND SOURCE LINE CONNECTIONS FOR A 3-DIMENSIONAL ARRAY OF MEMORY CIRCUITS
A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.
A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
90.
3-dimensional NOR memory array architecture and methods for fabrication thereof
A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
92.
Quasi-volatile memory with enhanced sense amplifier operation
A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.
By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H01L 27/11587 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the top-view layout
H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.
A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.
A memory system includes: a memory array including numerous quasi-volatile memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code: a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit.
A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refresh circuit writing back the first portion of the ECC-encoded code word.
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
100.
Method for in situ preparation of antimony-doped silicon and silicon germanium films
A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
