Systems and methods are provided for timing synchronization of serial data stream outputs of a plurality of serializers. The method involves providing a first serial data stream output of a first serializer of the plurality of serializers to an "AND" gate; selecting each serializer of the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the "AND" gate, and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the "AND" gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling the timing synchronization based on the determined timing offsets.
A circuit assembly, including a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink between the FPGA board and the mezzanine board; and a rigid mezzanine connection between the FPGA board and the mezzanine board, the rigid mezzanine connection extending through an opening in the heat sink.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
3.
METHODS FOR TAPPING AND INTERRUPTING COMMUNICATIONS ON A FIBER OPTIC CABLE
Methods and apparatuses for tapping a fiber optic communication cable are described herein. The tap comprises a first fiber port to receive via the fiber optic communication cable a first optical signal comprising a communication, a second fiber port to send via the outgoing fiber optic communication cable a second optical signal comprising the communication, one or more monitoring ports to send via the conductor-based monitoring cable a monitoring electrical signal, one or more converters in electrical communication with the first fiber port and the second fiber port, the one or more converters operable to convert optical signals into electrical signals, and a splitter in electrical communication with the one or more converters and the monitoring port, the splitter operable to convert the first electrical signal into the second electrical signal and the monitoring electrical signal.
H04B 1/74 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for increasing reliability, e.g. using redundant or spare channels or apparatus
Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.
Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03M 9/00 - Parallel/series conversion or vice versa
H04L 7/00 - Arrangements for synchronising receiver with transmitter
6.
Systems and methods for measuring latency in a network device
Systems and methods are provided for measuring latency in a network device, which can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.
Systems and methods are provided for timestamping, which can include a signal generator, a detector, a sampler, a pulse detector, a timer, and a time-stamper. The signal generator can define a signal profile. The detector can i) detect a data event, and, upon detecting the data event, ii) instruct the signal generator to change from operating in a first mode of operation to operating in a second mode of operation. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits. The pulse detector can detect a change in the signal profile by detecting a change in value in the plurality of bits. The timer can time the change in the signal profile to provide at least one detection time measurement. The time-stamper can record in association with the data event a timestamp based on the at least one detection time measurement.
Systems and methods are provided for timing signals. The systems and methods can include a signal-timing FPGA circuit. The signal-timing FPGA circuit includes a serializer, a pulse detector, at least one slower portion, a timer, and a signal generator. The serializer can convert data streams between serial transmission and parallel transmission. The serializer includes a serial input sampler for sampling signals received at the serializer, and a clock multiplier for changing signal frequencies. The at least one slower portion has a slower clock speed. The slower clock speed is slower than a clock speed of the clock multiplier. The timer is in communication with the serializer. The signal generator can generate and transmit a signal including a pulse portion and a non-pulse portion to the serializer via the at least one slower portion. The pulse portion differs in value from the non-pulse portion of the signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
9.
Distributed FPGA solution for high-performance computing in the cloud
A data processing system, method and device. A device can include a plurality of data cards having host interface connectors initially configured to transmit signals according to a first communication protocol and data card connectors that communicate with external devices using a different communication protocol. The data cards are converted so that the host interface connectors also transmit signals using the second communication protocol. The plurality of data cards are interconnected so that signals can be routed through the data cards to provide desired data processing functions. A cross-point switch fabric allows the signals to be routed to the appropriate data card or cards. Multiple devices can be interconnected to provide a distributed data processing grid providing access to the data processing functions for external devices that do not communicate using the first communication protocol.
A data processing system, method and device. A device can include a plurality of data cards having host interface connectors initially configured to transmit signals according to a first communication protocol and data card connectors that communicate with external devices using a different communication protocol. The data cards are converted so that the host interface connectors also transmit signals using the second communication protocol. The plurality of data cards are interconnected so that signals can be routed through the data cards to provide desired data processing functions. A cross-point switch fabric allows the signals to be routed to the appropriate data card or cards. Multiple devices can be interconnected to provide a distributed data processing grid providing access to the data processing functions for external devices that do not communicate using the first communication protocol.
A data processing system, method and device, A device can include a plurality of data cards having host interface connectors initially configured to transmit signals according to a first communication protocol and data card connectors that communicate with external devices using a different communication protocol. The data cards are converted so that the host interface connectors also transmit signals using the second communication protocol. The plurality of data cards are interconnected so that signals can be routed through the data cards to provide desired data processing functions. A cross-point switch fabric allows the signals to be routed to the appropriate data card or cards. Multiple devices can be interconnected to provide a distributed data processing grid providing access to the data processing functions for external devices that do not communicate using the first communication protocol.
A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports.
G06K 7/06 - Methods or arrangements for sensing record carriers by means which conduct current when a mark is sensed or absent, e.g. contact brush for a conductive mark
G06K 7/04 - Methods or arrangements for sensing record carriers by mechanical means, e.g. by pins operating electric contacts
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
G06F 1/08 - Clock generators with changeable or programmable clock frequency
A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports. One or more of the data card connectors may be repurposed as one or more host interface connections or one or more of the host interface connectors may be repurposed as one or more data card connectors.
patents
