Provided is a product-sum operator having low energy consumption and high operation accuracy. The product-sum operator 1 is constituted of: a resistive digital/analog conversion unit 11 which includes a plurality of RDACs and converts digital values of respective elements of an input vector into analog voltages and outputs the analog voltages; a capacitive digital/analog conversion unit 12 which includes a plurality of CDACs, receives the analog voltages output from the resistive digital/analog conversion unit 11, and has capacity ratios that correspond to digital values of respective elements of a matrix and are set between input and output terminals and between output terminals and the ground; a successive comparison-type analog/digital conversion unit 13 which includes a plurality of successive comparison-type ADCs, converts a voltage of a node commonly connected to respective output terminals of the capacitive digital/analog conversion unit 12 into a digital value, and outputs the digital value; and a current consumption control unit 14 which controls current consumption of the resistive digital/analog conversion unit 11, wherein an output from the successive comparison-type analog/digital conversion unit 13 is set as an output vector.
G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
G06F 3/05 - Digital input using the sampling of an analogue quantity at regular intervals of time
G06G 7/14 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for addition or subtraction
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
G06G 7/184 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for integration or differentiation using capacitive elements
aaa with a reference voltage that increases or decreases over a full-scale voltage range. If the signal voltage is lower than the threshold voltage, the comparator 120 compares the signal voltage of the analog signal to be converted that is input to the comparator 120 with a reference voltage that increases or decreases over a portion of the voltage range. A time digital converter such as a counter 130 starts or stops clock-based time measurement on the basis of a comparison result by the comparator 120 and outputs measured time information as a conversion digital signal of an analog signal to be converted.
Provided are: an image sensor that operates with low noise and low power, even if a pixel is a three-transistor structure; and an image sensing method. An image sensor 1 includes a plurality of pixels 10 arranged two dimensionally in a row direction and a column direction, a vertical scan circuit 11 that selects pixels of a particular row, a plurality of analog-digital converters 12 that performs column-parallel analog-digital conversion of signals from the pixels 10 of the row selected by the vertical scan circuit 11, and a control unit 14 that controls the foregoing. The image sensor 1 outputs, as an analog-digital conversion value of a pixel signal, the difference between: a reference signal value that is the result of digital conversion performed by the analog-digital converter 12, of the difference between a first reset voltage extracted by a voltage buffer part of each of the pixels 10 of the selected row and a voltage at the time of reset release; and an accumulated signal value that is the result of digital conversion performed by the analog-digital converter 12, of the difference between a voltage at the time of a second reset and a voltage immediately preceding the second reset operation extracted by the voltage buffer part.
Provided is an image sensor which operates at high speed with high accuracy and with power consumption. An image sensor 1 comprises: a pixel unit 11 in which a plurality of pixels 11a comprising a sensor element for detecting a physical quantity existing in nature and converting the physical quantity into an electric signal are two-dimensionally disposed in a row direction and a column direction; a digital-analog conversion unit comprising a current-type digital-analog converter 18 to generate a ramp wave; an analog-digital conversion unit 15 comprising a plurality of integrating-type analog-digital converters 15a to convert signals from the pixels 11a into digital signals by comparing with the ramp wave; and a digital control unit 10 for digitally controlling a current value to be flown through a resistor in the current-type digital-analog converter 18. The digital control unit 10 inputs a digital value to the digital-analog converter 18, the digital value incorporating a value varying in proportion to time and a stepped offset value for compensating for a delay in an output signal from the digital-analog converter 18.
The objective of the present invention is to provide a product-sum calculator having high calculating speed and low energy consumption. A product-sum calculator 1 is provided with a voltage output digital/analogue converting unit 11 which consists of a plurality of DACs, into which a vector having a plurality of digital values as each element, and a matrix having a plurality of digital values as each element are input, and which converts the digital value of each element in the vector into an analog voltage, a capacitance type digital/analogue converting unit 12 which consists of a plurality DACs, into which each output voltage of the voltage output digital/analogue converting unit 11 is input, and in which capacitance ratios corresponding to the digital values of each element in the matrix are set between input and output terminals and between the output terminals and ground, and an analogue/digital converting unit 13 which consists of a plurality of ADCs, into which the voltages of nodes connected in common to each output terminal of the capacitance type digital/analogue converting unit 12 are analogue input, and which converts the same to digital values, wherein the output of the analogue/digital converting unit 13 is an output vector.
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
An image sensor capable of obtaining a high dynamic range without reducing a frame rate. An image sensor includes a pixel region where a plurality of pixels each including a sensor element that detects a naturally occurring physical quantity and converts the physical quantity into an electric signal are arranged in a row direction and a column direction, a row selection unit that selects any of the pixels in the pixel region in units of rows and contributes to readout of the electric signal from each of the pixels and resetting of an accumulated charge, a pixel readout unit that reads out the electric signal from each of the pixels selected by the row selection unit in column-parallel, and a column selection unit that selects the pixel in any column from a pixel row selected by the row selection unit and controls a charge accumulation amount of the selected pixel.
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 25/443 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
Provided is an image sensor which operates at high speed and high accuracy with power consumption. A CMOS image sensor 10 is configured from: a pixel unit 1 in which a plurality of pixels 1a, which are provided with sensor elements that detect physical quantities present in the natural world and convert the physical quantities into electrical signals, are two-dimensionally arranged in the row direction and column directions; a resistive digital-to-analog converter 8 to which a plurality of unit circuits, of which resistors are connected to output terminals of CMOS inverters, are connected in parallel and which generates a ramp wave; and an analog-to-digital conversion unit 5 which is provided with a plurality of integral analog-to-digital converters 5a and compares signals from the pixels 1a with the ramp wave to convert the signals into digital signals.
H03M 1/56 - Input signal compared with linear ramp
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
H03M 1/78 - Simultaneous conversion using ladder network
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
Provided is an image sensor capable of achieving a high dynamic range without a reduction in frame rate. The image sensor 10 is configured to be provided with: a pixel area 1 where multiple pixels, each having a sensor element for detecting and converting a physical quantity in the natural world into an electric signal, are two-dimensionally arranged in a row direction and a column direction; a row selection unit 2 for selecting arbitrarily defined row of pixels in the pixel area 1 one by one and contributing to readout of the electric signals from the pixels and resetting of charges stored therein; a pixel readout unit 3 for column-parallel readout of the electric signals from the respective pixels selected by the row selection unit 2; and a column selection unit 4 for selecting an arbitrarily defined column of pixels from among the pixel rows selected by the row selection unit 3 and controlling the amounts of charges stored in the selected pixels.
Individual A/D converters constituting a time domain A/D converter group according to an embodiment of the present invention each comprises: a reference voltage selection circuit that is connected to a reference signal generation circuit for generating a first reference signal to sweep a full-scale range and a second reference signal to periodically sweep a limited voltage range a plurality of times and that switches between the first and second reference signals that are outputs of the reference signal generation circuit; a comparator that compares the first or second reference signal selected by the reference voltage selection circuit with an input signal; an internal A/D converter that implements an A/D conversion by use of a comparison output signal from the comparator; and a cumulative adder-subtracter that, if the second reference signal has been selected, outputs a signal obtained by averaging A/D conversion values obtained from the A/D conversion.
A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.
A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.
H03M 1/34 - Analogue value compared with reference values
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03M 1/56 - Input signal compared with linear ramp
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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