A method for advertising an extended advertising packet, a method for receiving an extended advertising packet, a communications system, and a related device are disclosed. In the method for advertising an extended advertising packet and the method for receiving an extended advertising packet, an extended advertising packet generated by a Bluetooth advertising device carries information about receiving time and a receiving channel for an auxiliary advertising packet. A Bluetooth receiving device may obtain both an advertising packet type of the auxiliary advertising packet and the information about the receiving time and the receiving channel for the auxiliary advertising packet based on the information about the receiving time and the receiving channel for the auxiliary advertising packet that is obtained by parsing the extended advertising packet, to accurately receive the auxiliary advertising packet.
Provided are a duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, through a counting clock signal having a higher clock signal frequency than a calibration clock signal, a counting unit is configured to acquire a number of counting pulses generated in a high-level state and a low-level state of the calibration clock signal within a preset counting period, so as to obtain an actual duty cycle of the calibration clock signal. Compared with a method of acquiring a duty cycle of a calibration clock signal by comparing the calibration clock signal with a reference clock signal, inaccurate measurement of the duty cycle of the calibration clock signal after the reference clock signal is affected can be overcome. Therefore, accuracy of measurement of the duty cycle can be improved, and precision of calibration of the duty cycle can be improved accordingly.
A video image processing method includes: obtaining an area to be superimposed in a video image, wherein the area to be superimposed contains a plurality of display blocks; performing optical parameter statistical processing on each display block to obtain an optical parameter statistical value; determining whether an adjustment processing needs to be performed on the target display character based on a difference value between the optical parameter statistical value and an optical parameter value of a target display character; performing adjustment processing on the target display character to obtain a superimposed character in response to a determination that the difference value is less than or equal to a preset threshold, wherein a difference value between an optical parameter value of the superimposed character and the optical parameter statistical value of a corresponding display block is greater than the preset threshold; and superimposing the superimposed character with the corresponding display block.
A generation method for a living body detection model, a living body detection method and a related device. The generation method for a living body detection model comprises: according to a preset collection period, acquiring channel state information of multiple received signals of a Wi-Fi receiving device, each received signal comprising a plurality of subcarriers; respectively carrying out conjugate multiplication processing on the channel state information of any two of the multiple received signals acquired in each collection period, so as to acquire a plurality of corresponding conjugate multiplication result matrixes; respectively extracting amplitude information and phase information of the plurality of subcarriers from the plurality of conjugate multiplication result matrixes; on the basis of the amplitude information and the phase information of the plurality of subcarriers, acquiring a plurality of pieces of corresponding living body detection training data, so as to form a living body detection training data set; and using the living body detection training data in the living body detection training data set to perform learning and training, so as to acquire a corresponding living body detection model. The solution in the embodiments of the present invention can improve the accuracy of living body detection.
Disclosed are a memory structure, a storage method, an entropy decoding method, a chip, a device, and a storage medium. The memory structure includes: a row storage circuit including a plurality of row storage components in a number identical to a number of rows of a decoding unit, where the row storage components correspond one-to-one to ordinates of the decoding unit, and each row storage component is configured to store a coding coefficient under a corresponding ordinate, and an abscissa of the coding coefficient; a column storage circuit including a plurality of column storage components in a number identical to a number of columns of the decoding unit, where the column storage components correspond one-to-one to abscissas of the decoding unit, and each column storage component is configured to store a coding coefficient under a corresponding abscissa, and an ordinate of the stored coding coefficient; and diagonal storage components in a number equaling 1 subtracted from the sum of the number of rows and the number of columns of the decoding unit, where each diagonal storage component is configured to store a coding coefficient on a corresponding diagonal position line, and an abscissa or an ordinate of the stored coding coefficient. According to the disclosure, an occupied area of the memory structure is reduced.
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
The present disclosure provides a shield and an electronic assembly. The electronic assembly comprises a base plate and a chip located on the base plate. According to the embodiments of the present disclosure, the shield is plate-shaped; in the shield, a first cover cap is connected to side walls around a second cover cap, the first cover cap is used for electromagnetic shielding around the chip, electromagnetic radiation is refracted multiple times on an inner surface of the first cover cap, energy of the electromagnetic radiation is lost during the refraction process, radiation energy of the electromagnetic radiation coupled to the first cover cap is reduced, and radiation energy radiated out of the first cover cap is reduced, such that an electromagnetic shielding effect of the shield is good; in addition, the second cover cap is closer to the chip than the first cover cap, and the second cover cap and the chip absorb heat generated by the chip; and because the first cover cap is connected to the second cover cap, the first cover cap can also absorb energy in the chip. In conclusion, the shield achieves not only the effect of heat radiation but also the effect of electromagnetic shielding, and is thus beneficial to reduce costs.
A television, a television wake-up method, and a television system. The method comprises: when a television enters a sleep state or a standby state, a Bluetooth module in a system chip of a television sets the value of a television state register in a Bluetooth chip of the television as a first numerical value, so that the Bluetooth chip of the television can quickly and accurately acquire information of the television being in a sleep state or a standby state by means of the numerical value of the television state register. Therefore, the speed and reliability of acquiring the television entering a sleep state or a standby state by the Bluetooth chip are improved, thereby improving the speed and reliability of the wake-up operation of the television.
Disclosed are a detection method and system for keypoints of a video image, a device, and a storage medium. The detection method includes: acquiring a current video image; dividing the current video image into a plurality of blocks; and acquiring keypoints from each block in sequence; where the acquiring keypoints includes: generating initial keypoints of the block; and extracting the initial keypoints in combination with a keypoint acquisition condition in a previous video image, so as to acquire the keypoints of the block. The disclosure detects the keypoints of the current video image accurately.
G06V 10/50 - Extraction of image or video features by performing operations within image blocksExtraction of image or video features by using histograms, e.g. histogram of oriented gradients [HoG]Extraction of image or video features by summing image-intensity valuesProjection analysis
G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
G06V 10/96 - Management of image or video recognition tasks
G06V 20/40 - ScenesScene-specific elements in video content
9.
IMAGE CORRECTION METHOD, ELECTRONIC DEVICE AND COMPUTER READABLE STORAGE MEDIUM
The present disclosure discloses an image correction method, an electronic device and a computer readable storage medium. The image correction method includes: obtaining an original image and a preset color adjustment strategy; obtaining pixel statistical information of the original image; determining a target color adjustment strategy based on the pixel statistical information and the preset color adjustment strategy; and adjusting the original image based on the target color adjustment strategy to obtain a target image with colors distinguishable by a user. The image correction method can adjust an original image through a target color adjustment strategy formed by different preset color adjustment strategies, so as to allow colors in the original image can be distinguished by a color-blind user. In addition, the color change in the original image is small, so as to improve the naturalness of the original image.
The disclosure discloses a video source transmission apparatus, a video source transmission method and a computer storage medium. The video source transmission apparatus includes: a video source acquisition module configured to capture video sources in multiple formats; a video source transmission module configured to transmit a video source; a control module connected with the video source acquisition module and the video source transmission module, the control module being configured to: obtain a video source to be transmitted from the video sources in multiple formats; buffer the video source to be transmitted in a circular queue; and control, after receiving a transmission control instruction, the video source transmission module to sequentially transmit the video source to be transmitted in the circular queue.
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
The present invention provides a multimedia product burn-in apparatus configured to test several multimedia products, including: a controller, configured to issue a running command; and a network server, connected to the controller and the several multimedia products respectively, the network server storing a test file, and the test file being generated by matching a signature and a log of the multimedia product, where the network server receives the running command to generate a control command, sends the test file to the several multimedia products according to the control command, and performs batch testing on the several multimedia products. The multimedia product burn-in apparatus saves a tester from repeatedly making individual changes to each multimedia product, achieves automated testing, and solves the problem of high manpower, material, and time costs caused by batch bum-in of the multimedia products in research and development and design stages.
An audio and video synchronization method and device (100) for a playback module, an electronic device (10) and a computer-readable storage medium are disclosed. The playback module includes an object-oriented program language standard library and an audio and video synchronization module of a kernel driver. The method includes: determining, in response to a playback instruction, a target player to build an audio module and a video module by the target player; creating, in the program language standard library, a synchronization instance corresponding to the target player, the synchronization instance having a unique instance identifier; and obtaining a reference clock corresponding to a real-time code stream of the synchronization instance based on the instance identifier, and controlling, according to a set synchronization mode, data outputs of the audio module and the video module corresponding to the target player based on the reference clock.
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
13.
CLOCK SIGNAL NOISE REDUCTION APPARATUS, NOISE REDUCTION METHOD, AND MULTI-PHASE DELAY-LOCKED LOOP
The present application discloses a clock signal noise reduction apparatus, a noise reduction method, and a multi-phase delay-locked loop. The clock signal noise reduction apparatus comprises a phase generation module, a phase selection module, and a frequency divider. The phase generation module is used for generating a multi-phase clock signal according to an input signal. An input end of the phase selection module is connected to an output end of the phase generation module, and is used for gating the path of the multi-phase clock signal according to phase information, and assigning a preset period of delay to the clock signal of the gated path, wherein the preset period is smaller than the cycle period of the multi-phase clock signal. An input end of the frequency divider is connected to an output end of the phase selection module, and is used for performing decimal-multiple frequency division on the multi-phase clock signal assigned the preset period of delay, so as to thus reduce signal noise.
The present disclosure discloses a clock signal noise reduction device and noise reduction method, and a multi-phase delay phase-locked loop. The clock signal noise reduction device includes a phase generator, a phase selector, and a frequency divider. The phase generator is configured to generate a multi-phase clock signal based on an input signal. The phase selector has an input end connected with an output end of the phase generator, and is configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel. The preset period is less than a cycle period of the multi-phase clock signal. The frequency divider has an input end connected to an output end of the phase selector, and is configured to perform fractional frequency division on the multi-phase clock signal delayed by the preset period.
Provided are a circuit board module and an electronic device. The circuit board module comprises: a bottom plate; and one or more chip modules located on the bottom plate and connected to the bottom plate. Each chip module comprises: an adapter plate and one or more chips arranged on the adapter plate at intervals, the area of the adapter plate being smaller than that of the bottom plate. Because dense pins are arranged at the bottoms of the chips, in order to connect wires of the pins on the chips, the chips need to be mounted on the adapter plate, and the chips are connected to the bottom plate by means of the adapter plate. Compared with the condition that the bottom plate uses a high-precision plate such as a multi-layer plate or a blind hole plate and the chips are directly mounted on the high-precision plate, the cost of the circuit board module is reduced by connecting the chips to the adapter plate of a small area and then connecting the chips to the bottom plate by means of the adapter plate.
A memory management method and module, a chip, an electronic device, and a storage medium. The memory management method comprises: scanning memory pages to which virtual addresses of a discontinuous memory mapping space are mapped to acquire a compressible memory page as a first memory page; compressing memory data in the first memory page to acquire corresponding memory compressed data; storing the memory compressed data in a data storage module, the data storage module being located in a memory space outside the discontinuous memory mapping space; after storing the memory compressed data in the data storage module, releasing the first memory page; and setting the corresponding virtual address as a page fault address. The memory utilization is improved.
A method and module for controlling the code rate of an encoder, and a chip, an electronic device and a storage medium. The method for controlling the code rate of an encoder comprises: when it is detected that an image processor receives an image frame to be processed, acquiring the state of a buffer pool; acquiring a corresponding noise reduction intensity according to the state of the buffer pool; and outputting the acquired noise reduction intensity to the image processor, so that the image processor performs noise reduction processing on the image frame by using the acquired noise reduction intensity, and outputting an image frame, which has been subjected to noise reduction processing, to an encoder, so that the encoder performs encoding processing on the image frame, which has been subjected to noise reduction processing. By means of the solution of the present application, the balance between image quality and an output code rate can be realized while an encoder has a low output code rate.
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
18.
DISPLAY DRIVING METHOD, MODULE AND CHIP, ELECTRONIC DEVICE AND STORAGE MEDIUM
The present disclosure relates to a display driving method, module, chip, electronic device, and a storage medium. Some embodiments of the present disclosure provide a display driving method, module, chip, electronic device, and a storage medium to improve the quality of the image presented. The present disclosure relates in part to the field of semiconductor integrated circuits.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
19.
TEXT COMPRESSION METHOD, MODULE, CHIP, ELECTRONIC DEVICE, AND STORAGE MEDIUM
The present disclosure relates to a text compression method, module, chip, electronic device and storage medium, wherein the method comprises: performing word segmentation processing on texts to be compressed, and collecting statistics about word length and word frequency of the words obtained after the word segmentation processing to construct a corresponding keyword list; compressing the texts to be compressed based on the constructed keyword list. The above scheme is beneficial to improve the compression ratio of text compression.
A duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, a counting unit uses a counting clock signal having a clock signal frequency higher than that of a correction clock signal to obtain the quantity of counting pulses generated in a high-level state and a low-level state of the correction clock signal within a preset counting period, so as to obtain an actual duty cycle of the correction clock signal. Compared with the manner of comparing a correction clock signal with a reference clock signal to obtain a duty cycle of the correction clock signal, the problem that duty cycle detection of the correction clock signal is inaccurate due to the fact that the reference clock signal is affected can be solved. Thus, the accuracy of the duty cycle detection can be improved, and the accuracy of the duty cycle calibration can be improved.
A video image processing method and apparatus, and a device and a storage medium. The apparatus comprises: an obtaining unit for obtaining an area for superposition in a video image, the area for superposition comprising a plurality of display blocks (S1); an optical parameter statistical unit for performing optical parameter statistical processing on each display block to obtain an optical parameter statistical value, the optical parameter statistical unit being a hardware unit (S2); a determination unit for determining, on the basis of a difference value between the optical parameter statistical value and an optical parameter value of a target display character, whether adjustment processing is needed (S3); a character adjustment unit for adjusting the target display character to obtain a superposed character when the difference value is less than or equal to a preset threshold, a difference value between an optical parameter value of the superposed character and an optical parameter statistical value of a corresponding display block being greater than the preset threshold (S4); and a first subunit for superposing the superposed character with the corresponding display block (S51). According to embodiments of the present invention, the CPU load, the calculation amount, and the bandwidth are reduced, and the chip design complexity and the chip area are also reduced.
The present utility model provides a shield and an electronic assembly. The electronic assembly comprises a base plate and a chip located on the base plate. According to the embodiments of the present utility model, the shield is plate-shaped; in the shield, a first cover cap is connected to side walls around a second cover cap, the first cover cap is used for electromagnetic shielding around the chip, electromagnetic radiation is refracted multiple times on an inner surface of the first cover cap, energy of the electromagnetic radiation is lost during the refraction process, radiation energy of the electromagnetic radiation coupled to the first cover cap is reduced, and radiation energy radiated out of the first cover cap is reduced, such that an electromagnetic shielding effect of the shield is good; in addition, the second cover cap is closer to the chip than the first cover cap, and the second cover cap and the chip absorb heat generated by the chip; and because the first cover cap is connected to the second cover cap, the first cover cap can also absorb energy in the chip. In conclusion, the shield achieves not only the effect of heat radiation but also the effect of electromagnetic shielding, and is thus beneficial to reduce costs.
An audio and video synchronization method and apparatus (100) for a playback module, an electronic device (10) and a computer-readable storage medium. The playback module comprises an object-oriented program language standard library and a kernel-driven audio and video synchronization module. The method comprises: in response to a playback instruction, determining a target player, and constructing an audio module and a video module by means of the target player; creating a synchronization instance corresponding to the target player in the program language standard library, the synchronization instance having a unique instance identifier; and obtaining a reference clock of a real-time code stream corresponding to the synchronization instance according to the instance identifier, and controlling data output of the audio module and the video module corresponding to the target player according to the set synchronization mode and the reference clock.
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
The present invention provides a multimedia product burn-in apparatus, used for testing a plurality of multimedia products, comprising: a controller configured to issue an operation command; and a network server separately connected to the controller and the plurality of multimedia products. The network server stores test files; the test files are generated by matching signatures of multimedia products with logs; the network server receives the operation command to generate a control command, and sends the test files to the plurality of multimedia products according to the control command to perform a batch test on the plurality of multimedia products. The multimedia product burn-in apparatus prevents repeated separate changes made by test personnel to respective multimedia products and achieves the effect of automated testing, thereby solving the problem of excessive manpower, consumable, and time costs caused by batch burn-in of multimedia products in the research and development stage and design stage.
A port processing method, used to enhance an electrostatic discharge protection capability and an overstress protection capability. The method comprises: step S1, providing a cable having a plurality of terminal contact cores leading out of the cable, the plurality of terminal contact cores comprising contact cores disposed at two sides of the cable, and signal cores disposed within the cable; and S2, changing the signal layout of the contact cores and the signal cores, so as to enhance the electrostatic discharge protection capability and the overstress protection capability. The method for changing the signal layout comprises: using the contact cores as a signal ground, and disposing a contact spring plate at a middle portion of each of the contact cores and each of the signal cores; and extending lengths of the contact cores outward.
H01R 43/00 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
Image and video processing methods and systems, and a data processing device and a medium. The image processing method comprises: extracting image features of an original image to obtain a first detailed image; selecting a target pixel and a local area from the first detailed image, the local area comprising the target pixel; calculating corresponding statistical feature information on the basis of a statistical relationship between other pixels in the local area and the target pixel, and updating the statistical feature information to color information of the target pixel in the first detailed image to obtain a second detailed image; and synthesizing the second detailed image and the original image to obtain a synthesized image. The scheme can be used to improve both of the image quality and the processing efficiency.
A text compression method, a module, a chip, an electronic device, and a storage medium. The method comprises: performing word segmentation processing on text to be compressed, and collecting statistics about word length and word frequency of words obtained after the word segmentation processing to construct a corresponding keyword list; and compressing said text on the basis of the constructed keyword list. The solution can improve the compression rate of text compression.
A comparator and a successive-approximation analog-to-digital converter. By providing an isolation transmission circuit between an input-stage circuit and a noise shaping input-stage circuit, the comparator can separately perform noise isolation on a first output signal and a second output signal which are output by the input-stage circuit and a third output signal and a fourth output signal which are output by the noise shaping input-stage circuit, and then input the signals to a latch-stage circuit, such that output ends of the input-stage circuit and the noise shaping input-stage circuit are independent of each other. Thus, a kickback noise caused by sharing an output end by the input-stage circuit and the noise shaping input-stage circuit can be avoided, such that the performance of a four-input comparator can be improved.
A display drive method, a module and a chip, an electronic device and a storage medium. Said method comprises: down-sampling a current frame of image to obtain a down-sampled image of the current frame (S110); acquiring a compressed down-sampled image of a previous frame of image and decompressing same to obtain the down-sampled image of the previous frame (S120); up-sampling the down-sampled image of the current frame and the down-sampled image of the previous frame to obtain an up-sampled image of the current frame and an up-sampled image of the previous frame (S130); performing high-frequency information restoration on the up-sampled image of the current frame and the up-sampled image of the previous frame to obtain a restored image of the current frame and a restored image of the previous frame (S140); and on the basis of the obtained restored image of the current frame and restored image of the previous frame, generating corresponding pre-overdrive display data (S150). The solution can improve the quality of presented images.
Embodiments of the invention provide an intelligent device and a method for controlling a boot screen of the intelligent device, applicable to the intelligent device supporting video hardware decompression. The method comprises steps of: completing hardware initialization operation, and storing a preset image in the first storage area, thereby enabling the image layer to display the preset image; starting a system kernel which controls the video driver module, and starting the video layer through the video driver module; reading the corresponding preset image in the first storage area, converting the preset image into video data, and writing the video data into the second storage area, thereby enabling the video layer to display the video data; and starting an application access to the system. During the whole startup process of the intelligent device, the contents displayed on a screen are all seamlessly connected, so that a phenomenon of black screen does not occur.
A method, apparatus and electronic device for detecting a display region of a video image in real time. The method includes: determining a bright pixel threshold line that distinguishes a display region from a black edge region of the current frame of image according to a pixel value of each pixel; determining a time-domain warning line according to time-domain motion statistic values of each row and each column of pixels of the current frame of image; determining a target optimal gradient line that distinguishes the display region from the black edge region of the current frame of image; and determining a boundary bright line between the display region and the black edge region of the current frame of image according to the bright pixel threshold line, the time-domain warning line and the target gradient line to determine the display region of the current frame of image.
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
A method for detecting a static logo of a video, an electronic apparatus and a storage medium. The method includes: calculating a pixel grayscale flag value, an edge gradient flag value and an edge direction flag value; calculating, in a preset neighborhood centered on the pixel at each pixel position of the current video frame, a first local confidence degree of the pixel grayscale flag value, a second local confidence degree of the edge gradient flag value, and a third local confidence degree of the edge direction flag value respectively; calculating a contribution score of each local confidence degree and a total contribution score of each pixel position; and gathering the total contribution score of each pixel position of the current video frame, and determining a static logo in the current video frame according to the total contribution score of each pixel position.
G06V 20/40 - ScenesScene-specific elements in video content
G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06F 18/22 - Matching criteria, e.g. proximity measures
G06V 20/62 - Text, e.g. of license plates, overlay texts or captions on TV images
33.
Encoded signal demodulation method, apparatus, device, and computer readable storage medium
The present disclosure relates to an encoded signal demodulation method, apparatus, and device. Some embodiments of the present disclosure are beneficial to improving demodulation performance.
The present disclosure relates to a demodulation method, apparatus, and device. Some embodiments of the present disclosure are beneficial to improving demodulation performance.
A method for processing an image, an apparatus for processing an image, an electronic device, and a storage medium. The method includes: obtaining a first aim-to-mask flag of a pixel to be interpolated; obtaining second aim-to-mask flags of pixels in a preset neighborhood of the pixel to be interpolated; determining flag categories and a number corresponding to each of the flag categories, in the first aim-to-mask flag and the second aim-to-mask flags; obtaining a third aim-to-mask flag of the pixel to be interpolated based on the flag categories and the number corresponding to each of the flag categories; obtaining interpolation data of the pixel to be interpolated based on the third aim-to-mask flag of the pixel to be interpolated; and performing motion compensation on the pixel to be interpolated based on the interpolation data.
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
G06T 3/4007 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/46 - Embedding additional information in the video signal during the compression process
A method for estimating a motion vector of a pixel block, a video processing apparatus, an electronic device and a storage medium. The method for estimating the motion vector of the pixel block includes: obtaining a plurality of candidate motion vectors of a current pixel block in a current video frame, the plurality of candidate motion vectors comprising at least a down-sampled candidate motion vector; calculating a confidence degree for a difference value between each of other candidate motion vectors except for the down-sampled candidate motion vector in the plurality of candidate motion vectors and the down-sampled candidate motion vector; and determining one candidate motion vector in the other candidate motion vectors as the motion vector of the current pixel block, the confidence degree for the difference value between the one candidate motion vector and the down-sampled candidate motion vector is highest.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
37.
Method for selecting reference frame, electronic device, and storage medium
A method for selecting a reference frame, an electronic device, and a storage medium. The method includes: calculating a sum of absolute values of pixel brightness differences of corresponding pixel locations in a current frame and a previous frame in a video; determining frame attribute of the current frame based on the sum of absolute values of pixel brightness differences, the frame attribute including a raw frame and a duplicate frame; counting a number of raw frames in M historical frames previous to the current frame; obtaining a current frame interpolation step size based on the number of raw frames in the M historical frames; obtaining a next frame phase to be interpolated based on a current frame interpolation phase and the current frame interpolation step size; and determining an interpolation reference frame based on the next frame to be interpolated.
The present disclosure relates to a motion compensation method and module, a chip, an electronic device, and a storage medium, to improve the problem of haloes easily appearing on the edges of moving objects.
H04N 19/55 - Motion estimation with spatial constraints, e.g. at image or region borders
H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/543 - Motion estimation other than block-based using regions
H04N 19/533 - Motion estimation using multistep search, e.g. 2D-log search or one-at-a-time search [OTS]
H04N 5/14 - Picture signal circuitry for video frequency region
H04N 5/21 - Circuitry for suppressing or minimising disturbance, e.g. moire or halo
H04N 19/23 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with coding of regions that are present throughout a whole video segment, e.g. sprites, background or mosaic
H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
H04N 19/517 - Processing of motion vectors by encoding
39.
Static identification area detecting method and module, chip, electronic device and medium
A static identification area detecting method and module, chip, electronic device and medium, which can improve the accuracy of static identification area detection.
The present disclosure relates to a scene detection method, a chip, an electronic device, and a storage medium, the present disclosure detects periodic scenes, which helps to improve the accuracy of motion estimation.
G06T 7/223 - Analysis of motion using block-matching
G06V 10/98 - Detection or correction of errors, e.g. by rescanning the pattern or by human interventionEvaluation of the quality of the acquired patterns
41.
Motion estimation method, chip, electronic device, and storage medium
The present disclosure relates to a motion estimation method, a chip, an electronic device, and a storage medium. The present disclosure is beneficial to improving the accuracy of motion estimation.
The present invention provides a video switching method based on multi-channel decoding and comprising: starting the intelligent device to accomplish an initialization operation of a system file; closing the display of an image layer, decoding and displaying an obtained boot video on the video layer; after a system desktop launcher is started, displaying a main interface on the image layer in a transparent form; after a system is started, the intelligent device creates and displays a display layer on the image layer, wherein a display area of the display layer is smaller than that of the image layer; and decoding and displaying remotely obtained video data on the display layer. The invention avoids the issue of waiting for the loading of the video data of the online video for playing after the boot video ends, resulting in a relatively long waiting time and lowering the user experience.
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
H04N 21/443 - OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
43.
Trusted execution environment-based key burning system and method
The present disclosure provides a trusted execution environment-based key burning system. After a terminal device is enabled, a normal operating system is started, the normal operating system acquires key data to be burned and outputs a switching signal and the key data to be burned, a microprocessor receives the switching signal in a monitor mode and the microprocessor is switched to the secure operating system from the normal operating system, the secure operating system receives the key data to be burned and decrypts the data to be burned according to preset key data, to acquire and write the corresponding original key data into a secure storage area of the secure operating system. Due to the use of the trusted execution environment-based key burning, the key is burned, stored and used safely. In addition, the cryptography protects the key from unexpected damage in transmission and keeps the key integral.
The invention provides a control system for controlling an intelligent system to reduce the power consumption based on a Bluetooth device, comprising: a main control chip; the Bluetooth device connected with the main control chip; a controller connected with the Bluetooth device and the main control chip, respectively, wherein the controller is connected with a power supply and is used for controlling the on and off of the power supply circuit of the control chip; and an isolation circuit connected among the Bluetooth device, main control chip and the controller, when the controller controls the power supply circuit to be switched off, the isolation circuit enables the Bluetooth device at an enabled state. The issues, that the cost is increased due to the fact that the single-chip microcomputer is additionally arranged to realize Bluetooth wake-up and the overall power consumption of the intelligent system is high, are overcome.
A microcode signature security management system based on a Trustzone technology comprises the steps of: starting a normal operating system; acquiring the signature-encrypted microcode file and outputting the signature-encrypted microcode file and a switching signal by the normal operating system; receiving the switching signal and starting the monitor mode by the microprocessor to start a secure operating system; receiving the signature-encrypted microcode file, performing signature verification on the signature-encrypted microcode file, loading the file when the signature verification passes, otherwise outputting microcode error information when the signature verification fails by the secure operating system. The security of microcode is ensured on the basis of a secure operating system safety environment to which a system layer is inaccessible. A cryptography tool measure is adopted, so that the security, integrity and correctness of loaded microcode are ensured, and the risk of breaking, modifying and replacing an existing microcode management mechanism is lowered.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
46.
Method for calibrating crystal frequency offset through internal loop of central processing unit
The invention provides a method for calibrating crystal frequency offset through an internal loop of a central processing unit (CPU), which comprises: outputting an oscillation exciting signal to a crystal circuit by the CPU; producing a clock signal by the crystal circuit; outputting the clock signal through an output port arranged on the CPU by the internal loop; and adopting and connecting a frequency meter to the output port, and receiving and testing the clock signal to obtain a testing result; determining whether a deviation of the clock signal is qualified; if it is qualified, the tester exits subsequently, otherwise the tester regulates the crystal circuit, and then turning to Step S4. The clock signal of the CPU is output at the output port through the internal loop, and then the frequency meter is used for measuring the clock without being influenced by a probe, and the measurement is more accurate.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
G06F 1/08 - Clock generators with changeable or programmable clock frequency
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/04 - Automatic control of frequency or phaseSynchronisation using a frequency discriminator comprising a passive frequency-determining element wherein the frequency-determining element comprises distributed inductance and capacitance
A switching regulator has a voltage reduction module, a first acquisition module, a second acquisition module, a third acquisition module, a comparison module and a pulse width modulation module, wherein the comparison module compares a superposed signal of a flat-wave signal or a ramp signal and a feedback signal with an acquisition signal, and outputs a comparison signal; the second acquisition module outputs the ramp signal when the acquired output signal is greater than a preset value, otherwise outputs the flat-wave signal; or when the working current obtained from the main circuit is greater than a preset value, a ratio of the feedback signal output from the third acquisition module to the working current of the main circuit is 1, otherwise the ratio is less than 1. The switching regulator has the advantages of excellent transient response, quick response, and high reliability.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A method for releasing memory allocated by a contiguous memory allocator that merges a to-be-released memory page with an adjacent free page to form a memory block that can be released more efficiently than would be the case when releasing a series of un-merged memory pages.
A time to digital converter includes a polarity detecting module and a time digital conversion module. The time digital conversion module includes a digital coding unit, a ring vibration enabling unit, multistage differential time delay units sequentially forming a closed loop in series and a plurality of trigger units. Each differential time delay unit includes a first input end, a second input end, a first output end and a second output end. The first output end and the second output end of each differential time delay unit outputs differential signals which are complementary to each other. Mismatching between the ascending and descending time of a phase inverter and sampling of a trigger can be improved to enable signals entering the trigger units to be phase-complementary signals, thus improving the linearity of digital conversion.
The PWM waveform generation device comprises a time-division multiplexing module, wherein the time-division multiplexing module is configured for receiving a first preprocessing signal and a second preprocessing signal output by two system clock sources, performing a first time-division processing on the first preprocessing signal to obtain a first time-division signal, and performing a second time-division processing on the second preprocessing signal to obtain a second time-division signal according to a preset strategy, performing multiplexing processing on the first time-division signal and the second time-division signal to obtain a PWM output signal, wherein an output frequency of the PWM output signal is a default standard clock frequency. The present invention has the advantages that the cycle length of one cycle of a PWM waveform depends on cycles of two preprocessing waveforms and the number of the cycles, such that the output waveform frequency may be calibrated to a desired frequency.
A method for calibrating crystal frequency offset through a radio frequency signal includes, in Step S1, a radio frequency port of a device is connected to one end of a radio frequency cable through a copper pipe connector and the other end of the radio frequency cable is connected to a Wireless Local Area Network (WLAN) tester which is connected with a control terminal. In Step S2, a user controls the WLAN tester to test the radio frequency signal of the device through the control terminal to obtain a test result, and determines whether a deviation of the radio frequency signal is qualified. If it is qualified, the user exits the test, otherwise the user regulates the crystal circuit of the device under test, and returns to Step S2. The method may not be affected by a probe, thus the measurement may be more accurate.
A memory/multi-core concurrent memory allocation method, which is applied to an embedded system, wherein a kernel module and a plurality of application programs are provided. The memory allocation method comprises: acquiring first memory allocation requests of the plurality of application programs; the kernel module determining whether preset screening marks exist in the first memory allocation requests; when screening marks exist in the first memory allocation requests, prohibiting allocating memory for the current application program managed by a contiguous memory allocator. By adopting the memory allocation method, the application programs which occupy contiguous memory allocated by the continuous memory allocator for a long time can be screened and removed, then contiguous memory allocation can be provided for the drivers in a shorter time, and the corresponding contiguous continuous memory can be allocated for the drivers through a plurality of processing units at the same time with a higher efficiency.
The invention relates to the field of power and electronic technologies, particularly to a power supply system with a stable loop comprising a PMOS transistor, a NMOS transistor, a first comparator and a voltage control circuit connected between a comparison terminal and the ground; wherein, a current-limiting acquisition port is configured to acquire on-state current of the PMOS transistor; and the current-limiting protection circuit outputs an voltage signal of the comparison result as the control signal of the pulse width modulation driver when the acquired on-current state of the PMOS transistor is less than a preset current value; and outputs a turn-off signal for turning off the pulse width modulation driver as the control signal when the acquired on-current state of the PMOS transistor is greater than a preset current value. The present invention has the advantages that relatively high loop stability can be ensured and high reliability is achieved.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
54.
Method for detecting memory leak based on linux kernel
A method for detecting a memory leak based on Linux kernel, applied to an detection of the memory leak, comprises: reading a node, acquiring the return addresses of the allocation functions of each of the plurality of memory pages and the number of the memory pages thereof; releasing the return addresses of the allocation functions and the number of the memory pages counted by the node; reading the node again, acquiring the return address of each of the allocation functions and the number of the memory pages thereof; comparing the number in each case to calculate a difference value, if the difference value is a positive value and monotonically increases, it's determined that the memory leak occurs in the memory pages allocated correspondingly by the allocation functions. During the detection of the memory leak, the detection method consumes less memory without affecting the efficiency in allocating and releasing the memory.
The invention relates to a data edge jumping method, applied to a memory system, wherein the memory system comprises a processor and a memory driven by the processor, and a plurality of groups of data lines are connected between the processor and the memory. The data edge jumping method comprising: coding data output by the processor to enable total current produced by data transmission through each of the plurality of groups of data lines at the same time to be zero; transmitting the coded data through the plurality of groups of data cables, and decoding the data before reaching the memory; and inputting the decoded data into the memory, and enabling the total current produced in the data lines to be close to 0 A, so that electromagnetic interference is hardly produced by signals transmitted through the data lines, and allowance of signal radiation is large enough.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
56.
Method and system for adjusting white balance, and display
The invention discloses a method and system for adjusting white balance, and a display, and belongs to the technical field of display. The method for adjusting the white balance is applied to the display, and comprises the following steps: identifying image information of a currently played frame image to be adjusted; obtaining a matched target color temperature value according to the image information; and adjusting a white balance parameter of the frame image to be adjusted according to the target color temperature value. According to the method disclosed by the invention, by identifying the image information of the currently played frame image to be adjusted, and obtaining the matched target color temperature value according to the image information, the white balance parameter of the frame image to be adjusted is automatically adjusted according to the target color temperature value, the purpose of correspondingly adjusting the white balance parameter of the currently played frame image contents in real time can be achieved, so that the sense of tableau of the image is more realistic, and the visual effect is enhanced.
The invention discloses a method for correcting screen display based on negative feedback. Correction of the G channel value, the B channel value and the R channel value in turn is marked as a correction of the working parameters of the screen. Measuring if the luminance, color temperature y-axis coordinate and color temperature x-axis coordinate of the screen display simultaneously reach the corresponding target values after correcting the working parameters for one time; if yes, the current gray scale correction is ended; otherwise, correcting the working parameters of the current gray scale again by starting from correction of the G channel value. The R channel value, the G channel value and the B channel value are corrected in a separate manner based on the feedback, and the correction process is simplified, such that the accuracy of a single correction is higher and the correction speed is improved.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
The present invention discloses a method of correcting screen brightness and color temperature, it relates to the field of display technology. The present invention is used for correcting the working parameters of the every m stages of gray-level pictures to adjust display of the screen to a maximum gray level, the correction is started from a gray level next to the maximum gray level, and only for correction of the first gray level, working parameters of the previous gray level are used as the initial values of working parameters of the current gray level correction; from correction of the second gray level, a correction estimated value of working parameters of a current gray level is estimated according to the working parameters and the local linearity relation of the two corrected gray levels, and the correction estimated value is taken as the initial working parameter of the current gray level correction. The method has the advantages that the method has higher reliability, thereby being capable of effectively correcting different screens or screens nonuniform in quality, and the method has higher accuracy and speed, thereby being capable of completing correction in fewer number of times of adjusting.
G09G 5/02 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
59.
METHOD AND SYSTEM FOR MEMORY INTERFACE TIMING ANALYSIS
The present invention relates to the technical field of communications. Provided are a method and system for memory interface timing analysis. The method comprises: acquiring a first signal eye pattern of a memory interface (S1); determining a step offset value according to a standard eye height corresponding to the memory interface (S2); causing the first signal eye pattern to respectively translate upward and downward according to the step offset value, and obtaining two signal eye patterns after the translation has been carried out (S3); superimposing the two signal eye patterns, and obtaining a second signal eye pattern from an overlapped region (S4); and acquiring optimal position information of the memory interface according to the second signal eye pattern (S5). The method and system can adapt to different eye patterns to accurately acquire optimal position information of a memory interface.
Provided are an internal memory interface write-leveling control method and device, belonging to the technical field of communications. In the internal memory interface write-leveling control method and device, during the process of controlling a sampling signal to be sent to an internal memory device at a preset delay step, on the basis of the effective level of the sampling signal corresponding to each delay step, sampling information of a first preset length is generated; the sampling information is analyzed, and a write-leveling phase value of the sampling signal is determined according to the location of the region where the sum of the effective levels in the sampling information is the largest, thus sampling errors caused by jitter, noise, and other interference in the sampling process are shielded, and the optimal delay position of the sampling signal is determined, and adaptability is strong.
Disclosed in the present invention are a de-interleaving method and device, belonging to the field of communications. In the present invention, a channel processing module divides first symbol information sent by a sending end into at least one subcarrier row data block, and sends the subcarrier row data blocks one by one to a de-interleaving module according to a preset order, and the de-interleaving module can perform de-interleaving processing on the received subcarrier data blocks one by one. The storage space of the de-interleaving module satisfies the requirements of two subcarrier row data blocks, so that the requirement for the storage space is low, the power consumption is low, and the de-interleaving rate and the real-time performance of the de-interleaving are improved.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
62.
CONTROL METHOD AND APPARATUS BASED ON MULTIMEDIA INTERFACE
Disclosed are a control method and apparatus based on a multimedia interface, wherein same fall within the technical field of communications. According to the present invention, real-time information received and sent by an intermediate device can be recorded in real time by means of an information form, and on the basis of the real-time information, a corresponding trusted message is generated for the identification of the credibility of the real-time information; and after the intermediate device collects event information, if an end message is not received, a corresponding switching message can be sent according to the type of the current trusted message in the information form, such that the intermediate device can maintain a transmission channel prior to the collection of the event information, thus ensuring the transmission states between the intermediate device and upstream and downstream devices, avoiding the situation in which the intermediate device makes a mistaken selection due to the collection of the event information by same, and improving the effective processing capability and compatibility of the intermediate device for the event information.
A construction apparatus and construction method for a self-learning speech recognition system. The construction apparatus is applied to a speech recognition system; the speech recognition system comprises a microphone and a speech recognition module using the construction apparatus; the microphone is connected to the speech recognition module; the construction apparatus comprises an analysis unit (1) configured to analyze an output signal of the microphone to obtain a plurality of signal parameters, and a recognition unit (2) connected to the analysis unit (1) and configured to determine, according to the signal parameters, whether the output signal is a preset activation speech. A wake up operation is implemented by means of an activation speech, so that a power supply module, an ADC, and a CPU in a standby process are enabled to sleep, thereby reducing energy consumption in the standby process.
The present invention belongs to the technical field of communications. Disclosed is an interface timing calibration method and apparatus. The interface timing calibration method of the present invention is applied to an interface coupled to an application layer and a physical layer. In said method, a step of a receipt clock signal of an application layer is adjusted, and the application layer sends a data packet to a physical layer, and acquires a data packet looped back by the physical layer, so as to determine the validity of the clock signal according to the data packet received by the application layer; and a phase of a receipt target clock is acquired according to a clock phase effective range of the clock signal, so that the optimal clock timing parameters are selected according to different chips, so as to maximize an effective window margin of an interface.
The present invention provides an implementation method of a memory test tool. A kernel test tool is provided; a processor provides a user interval and a system interval, the system interval being divided into a plurality of regions, the regions including a dynamic memory region, a module region, a kernel region and a fixed mapping region; the kernel region is provided with a kernel code region, and an address space between a tail address of the kernel code region and a head address of the module region is smaller than 32 MB; in the user interval, a continuous address space is partitioned as a kernel test region, the kernel test region is provided at a boundary between the user interval and the system interval; the kernel test region is set as a mapping region of the system interval; and according to a test flag in program codes currently running in a system, the memory test tool tests the position, in the kernel test region, corresponding to the memory address where the current program codes are located, so as to determine whether the current memory access is valid. The beneficial effect of the present invention is to enable a 32-bit ARM architecture to support a memory test tool.
A method for rapidly starting a memory of a system on chip, comprising the following steps of: determine whether the memory is in a first startup stage; if yes, after the memory is switched from a first initial stage to a second initial stage, a controller sends a first command to the memory so as to set a first relative address of the memory, and switches the memory from the second initial stage to a third initial stage; the controller sends a second command containing the first relative address to the memory, and switches the memory from the third initial stage to a fourth initial stage so as to complete a first startup stage; if not, determine whether the memory is in a second startup stage; if yes, after the first startup stage is completed, the controller directly sends a second command containing a virtual relative address to the memory, and the memory executes a first operation according to a first strategy to complete the second startup stage; and if not, completing a third startup stage with the operation above. The method can reduce the initialization time of the whole memory.
Disclosed in the present invention are a digital frequency generator and a state switching method therefor, which belong to the field of electronic testing. In the present invention, a control signal is generated according to a frequency control word, the control signal is used to perform frequency division processing on an inputted clock signal so as to generate a group of clock signals with a plurality of different phases, a sleep period is calculated according to a phase selection signal sent by a modulator, a state control signal is generated, and a working state and a sleep state of a phase error compensation module is controlled according to the control signal, so that when the phase error compensation module is in the working state, a pair of clock signals are selected from the group of clock signals to perform error compensation so as to generate a clock signal, and when the phase error compensation module is in the sleep state, the power consumption is reduced, thereby achieving the purpose of reducing the total power consumption of the digital frequency generator.
The present invention provides a passive crystal oscillator sharing circuit, comprising: a crystal oscillator circuit used for outputting a clock signal; a system-on-chip, wherein a crystal oscillator input pin and a crystal oscillator output pin of the system-on-chip both are connected to the crystal oscillator circuit and used for receiving the clock signal and then outputting same; and an integrated chip, wherein the crystal oscillator input pin of the integrated chip is selectively connected to one of the crystal oscillator input pin and the crystal oscillator output pin of the system-on-chip by means of a passive filter so as to receive the clock signal outputted by the system-on-chip. The present invention has the following beneficial effects: interference is reduced by means of the passive filter, so that the frequency of the clock signal of the system-on-chip is consistent with that of the clock signal of the integrated chip, thereby reducing the number of crystal oscillators.
Disclosed in the present invention are a method and system for obtaining a threshold voltage of a data interface, relating to the technical field of communications. By scanning a signal eye pattern to extract valid voltage pairs falling within a preset range, and then computing a threshold voltage of a data interface according to the valid voltage pairs, the interference of a "top-clipped" (or "bottom-clipped") voltage pair in the signal eye pattern can be avoided, and the accuracy of a computed valid threshold voltage is ensured, so that characteristics of the data interface, such as the signal amplitude, jittering, signal sampling stability and reliability, and interfering noise resistance capability, can be more precisely learnt about, thereby performing accurate determination on data interface performance.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
The present invention relates to the technical field of signal processing, and particularly relates to a switching analysis method for a signal source. A hardware interface and a hardware driver are provided, and the hardware driver starts the hardware interface. The switching analysis method specifically comprises: step S1, providing at least one signal source interface, and starting the signal source interface by the hardware driver; step S2, adding a printing mark to the signal source interface; step S3, switching the signal source interface, and generating, recording, and saving the debugging and printing report of the signal source interface; and step S4, exporting the debugging and printing report, and parsing the debugging and printing report to collect statistics about the average value output result of each stage of data. The technical solution of the present invention has the following beneficial effects: automatically collecting statistics about the interface switching data of the signal source interface, being capable of fast and accurately providing the signal source interface switching data, and greatly improving the efficiency of data statistics, thereby improving research and development efficiency.
The present invention relates to the technical field of televisions. Disclosed are a television channel presetting method and apparatus, a computer device, and a readable storage medium. According to the present invention, when a target television is started in a factory mode, a channel presetting configuration file in a software package is analyzed, channel information is stored in a channel list in a database of the target television, and the interface of the target television is updated according to the change of the channel list in the database, thereby facilitating broadcasting channels, and achieving the purpose that channel presetting takes effect on the premise that the application permission of a system is satisfied.
The present invention relates to the technical field of integrated circuits, in particular to a contactless serial port debugging circuit. The contactless serial port debugging circuit comprises: a gating unit capable of performing switching, and a test unit; a test platform, wherein the test platform is provided with a digital signal optical cable interface, and the gating unit uses the digital signal optical cable interface to transmit a digital signal and enables gating of a serial port signal, so as to realize switching between a digital signal transmission channel and a serial port signal transmission channel; and a test end provided with a serial port signal optical cable interface, wherein the serial port signal optical cable interface and the digital signal optical cable interface are converted and multiplexed, and the test unit transmits and tests the serial port signal by means of the serial port signal optical cable interface. The beneficial effects thereof lie in that a contactless debugging mode for a serial port signal is realized on an original digital signal channel, wherein same not only makes the cost low and the degree of complexity low, but can also effectively prevent the potential problem of static electricity damaging a device due to same being in a contact-type debugging mode, and can achieve economic benefits and practicability with no need for the workload of special software.
The present invention belongs to the technical field of computers. Disclosed are a version comparison method and system, a computer apparatus, and a readable storage medium. In the invention, code identifier data of respective pieces of module information in a target version file is compared with code identifier data of corresponding pieces of module information in a comparison version file, so as to obtain all pieces of module information containing modified code in the two version files, and to then obtain corresponding pieces of bug identifier data according to the module information, thereby quickly and accurately locating the modified code and corresponding bugs.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
The present invention relates to the technical field of OTG functions, in particular relates to a method for multiplexing an earphone seat and a USB OTG function. The method comprises: step S1, providing a multiplexing circuit, wherein the multiplexing circuit is respectively connected to an earphone seat and a control chip; and step S2, using the control chip to detect a level state of the earphone seat, and determining, by means of the multiplexing circuit, an external device which is inserted into the earphone seat. The technical solution of the present invention has the beneficial effects that the level state of the earphone seat is detected by using the control chip, and the external device which is inserted into the earphone seat is determined by means of the multiplexing circuit and can be respectively in communication connection with an earphone wire, a USB host device and a USB external device, such that multiplexing of an earphone function and an OTG function is realized, the circuit structure is simple, debugging performed by a software engineer is facilitated, and popularization is facilitated.
Disclosed is a method for testing a power amplifier, wherein same belongs to the field of hardware testing. In the present invention, a control end is used to control a test end to sequentially perform, according to a test rule, tests on a device to be tested, so as to check whether a power amplifier of the device to be tested is normal, thereby providing a guarantee for normal operation of a voice recognition function of the device to be tested, quickly and accurately locating a fault position of the device to be tested, and improving the detection effect.
A method and a device for obtaining voice signals. The method for obtaining voice signals comprises: analyzing collected audio signals to obtain the average amplitude of each voice signal in the audio signals; and filtering noise signals in the audio signals according to the average amplitude to obtain nearest voice signals, such that the accuracy of voice signal recognition in a voice recognition stage is improved.
A method for realizing a USB OTG function. The method comprises: step S1, providing a detection circuit, wherein the detection circuit is respectively connected to a USB socket (J) and a USB control chip (U); and step S2, identifying a working mode of the USB socket (J) by using the detection circuit, and setting, by means of the USB control chip (U), the working mode of the USB socket (J) to be a working mode adaptive to an external device. By using a detection circuit, an external device mode and a host mode of a USB socket (J) are identified, such that the USB socket (J) is switched between the external device mode and the host mode and respectively communicates with a host device or an external device to realize an OTG function; moreover, the structure of the circuit is simple, a test function can be displayed, and popularization is facilitated.
The present invention provides a method for measuring an internal Phase Locked Loop of a Central Processing Unit (CPU) by a frequency meter, wherein the method comprises following steps: the (CPU) outputting an oscillation excitation signal to a crystal circuit; the crystal signal generating a clock signal; the internal loop respectively outputting the clock signals that does not pass through and passes through the phase locked loop; adopting a frequency meter to receive the clock signals and perform a clock precision test to correspondingly obtain a first test result and a second result; comparing the first test result and the second result to obtain a result of the stability of the phase locked loop. The beneficial effects of the invention: the operation is simple and it does not need to buy an expensive oscilloscope, the accurate precision of the PLL can be measured without the influence of the crystal.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
79.
HDCP KEY-BASED SIGNAL TRANSMISSION METHOD AND SYSTEM
Disclosed are an HDCP key-based signal transmission method and system, relating the technical field of data transmission. A sending end accumulates a number of consecutive times of an abnormal message, and in the case that the number of consecutive times of the abnormal message does not reach a preset number, can continuously send a video signal to a receiving end, thereby effectively avoiding interference on the transmitted video signal due to a single check failure.
H04N 21/6334 - Control signals issued by server directed to the network components or client directed to client for authorisation, e.g. by transmitting a key
H04L 29/06 - Communication control; Communication processing characterised by a protocol
80.
DISPLAY APPARATUS V-BY-ONE SIGNAL CONTROL METHOD AND SYSTEM
A display apparatus V-by-One signal control method and system, relating to the technical field of video transmission. Using a control unit (1) to detect the duration of an abnormal signal; when the duration does not reach a preset time, the control unit (1) can continuously send V-by-One signals to a display unit (2), thereby effectively avoiding the short-term black screen phenomenon caused by static electricity, suppressing the interference of electrostatic signals on the V-by-One signal, and improving the user viewing experience effects.
A port processing method, used to enhance an electrostatic discharge protection capability and an over-stress protection capability. The method comprises: step S1, providing a cable having a plurality of terminal contact cores leading out of the cable, the plurality of terminal contact cores comprising contact cores (31, 33, 34, 36, 51, 53, 54, 56, 91, 93, 94, 96) disposed at two sides of the cable, and signal cores (32, 35, 52, 55, 92, 95) disposed within the cable; and step S2, changing a signal layout of the contact cores (31, 33, 34, 36, 51, 53, 54, 56, 91, 93, 94, 96) and the signal cores (32, 35, 52, 55, 92, 95), so as to enhance the electrostatic discharge protection capability and the over-stress protection capability. The method for changing the signal layout comprises: using the contact cores (31, 33, 34, 36) as a signal ground, and disposing a contact spring plate (37) at a middle portion of each of the contact cores (31, 33, 34, 36) and each of the signal cores (32, 35); and extending lengths of the contact cores (51, 53, 54, 56) outward, such that each of the contact cores (51, 53, 54, 56) has a length greater than that of each of the signal cores (52, 55), or increasing a signal spacing of the contact cores (91, 93, 94, 96) with respect to an adjacent signal cores (92, 95) thereof.
A frequency demultiplication adjustment method of PLL comprises obtaining a plurality of corresponding frequency demultiplication frequency points according to a default frequency demultiplication value of a phase-locked loop; obtaining a load state of the processor within a predetermined sampling period, and obtaining a target frequency point of the processor by the processor frequency adjustor; determining a frequency range of a virtual frequency point to be added according to the position of the target frequency point; performing calculation within the frequency range to obtain equivalent frequencies corresponding to virtual frequency points; judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to the virtual frequency points; if not, switching the processor frequency adjustor to the corresponding frequency demultiplication frequency point; and adjusting the frequency demultiplication value of the phase-locked loop which outputs a clock source signal corresponding to the virtual frequency points to the processor.
The present invention provides a method for collecting system logs, applied to an intelligent device with an Android system, wherein providing a daemon process for log collecting, and the daemon process is started when the system of an Android device is started; providing an application process for log processing; providing an external storage device for accessing the intelligent device; the method comprises the following steps: the daemon process collects the application framework layer and logs of the Linux kernel, and saves the logs in a first storage path of the Android system; the application process creating a second storage path in the external storage device after identifying the accessed external storage device; and the application process obtaining the logs from the first storage path and saving the logs in the second storage path.
The invention provides a method for realizing multi-channel recording based on an Android system and an audio system, wherein the audio system sequentially comprises a recording application module, an audio framework module, an audio library, a hardware abstraction module and an audio driver module in a kernel, wherein the method comprises: the hardware abstraction module calling an audio recording interface, so that the audio framework executes a multi-channel recording operation through the audio interface; the audio framework module being configured to support a multi-channel recording function; and the recording application module being configured to support transmission of multi-channel recording parameters. The requirement of a user for achieving the multi-track recording function in the Android system can be met, and the defect that in the prior art, the intelligent device, based on the Android system only supports a single-channel or double-channel recording function is overcome.
The present invention relates to processor testing technology, specifically relating to a method for automatically testing a processor, the method comprising: S1, carrying out test preparation; S2, setting an operation voltage and a clock frequency of a processor to be tested; S3, carrying out load testing at the current operation voltage and clock frequency; S4, determining whether the processor is normal during current load testing; if yes, then turning to step S5; if no, then raising the current operation voltage by a first growth value and returning to step S2; and S5, recording an operation voltage, subject to load testing, which corresponds to the current clock frequency as a test result and determining whether the current clock frequency reaches an upper limit; if yes, then ending the operation; if no, then raising the current clock frequency by a second growth value and returning to step S2. The described method is capable of implementing the automatic testing of processors and rapidly and effectively obtaining operation voltages corresponding to clock frequencies when the processors are operating normally, and is thus suitable for a plurality of platforms.
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
A hardware device debugging method and apparatus, a computer device, and a storage medium, relating to the field of electronic testing. By means of testing a data interface of a device to be tested, reading the current state of the data interface and the value of a register corresponding to the data interface and, by means of adjusting the value of the register, reducing the debugging time of the maximum active window of the data interface, thereby enhancing the system stability of the device to be tested and reducing labour costs.
Disclosed by the present application are a method and system for debugging a composite synchronous video broadcast signal, belonging to the field of television. In the present application, a composite synchronous video broadcast signal wire is connected to a device to be debugged, thereby obtaining test parameters of the composite synchronous video broadcast signal of the to-be-debugged device during operation; according to the test parameters, the values in the register corresponding to the respective parameter of the to-be-debugged device are adjusted such that the test parameters meet preset test indicators, reducing debugging time and achieving the objectives of rapid debugging and reducing labor costs.
The present invention relates to the technical field of integrated chips, and more particularly, to a system-level test method for a flash memory. The method comprises: step S1, providing a test flag file, and storing a test number parameter in the test flag file; step S2, determining whether a value of the test number parameter reaches a pre-set value; if not, turning to step S3; if yes, ending and counting a verification result; step S3, performing one partition mirror data check on all partitions of the flash memory, and performing one file data check on a current system file of the flash memory; and step S4, restarting a test device, subtracting one from the value of the test number parameter, and returning to step S2.
The invention provides a method for automatically adjusting the gain of a multi-stage equalizer of a serial data receiver, the serial data receiver provides a gain circuit, the gain circuit comprises a multi-stage equalization circuit, and each stage of equalization circuit is arranged in series; the method comprises: Step S1, setting corresponding serial numbers for each stage of equalization circuit in sequence; Step S2, selecting an equalization circuit corresponding to the serial number from the gain circuit according to a preset rule; Step S3, sequentially adjusting the selected equalization circuits of each stage according to the sequence of the serial numbers to obtain corresponding standard adjustment values; and Step S4, adjusting the equalization circuit greater than or equal to the corresponding serial number according to the standard adjustment value. The method has the benefits that the optimal compensation for the signal is realized.
The invention comprises a method for controlling a gain of a multi-stage equalizer of a serial data receiver, applied to the serial data receiver, the serial data receiver comprising the multi-stage equalizer, wherein the method comprises the steps of: Step S1, enabling the serial data receiver to receive a set of serial data; Step S2, selecting a continuous first data sequence from the set of serial data according to a preset first rule; Step S3, selecting a continuous second data sequence from the first data sequence according to a preset second rule; Step S4, extracting a predetermined bit from the second data sequence; Step S5, calculating an equalization gain identifier of the data sequence by using each predetermined bit; and Step S6, controlling the gain value of the multi-stage equalizer according to the equalization gain identifier.
The invention comprises a method for controlling a gain of a multi-stage equalizer of a serial data receiver, applied to the serial data receiver comprising the multi-stage equalizer, wherein the method comprises: Step S1, enabling the serial data receiver to receive a set of serial data; Step S2, selecting a plurality of continuous data sequences from the set of serial data according to a preset first rule; Step S3, extracting a predetermined bit from each of the plurality of continuous data sequences; Step S4, calculating an equalization gain identifier corresponding to each of the plurality of continuous data sequences according to a predetermined bit in each of the plurality of continuous data sequences; Step S5, obtaining an optimized equalization gain identifier through calculation according to each of the equalization gain identifiers; and Step S6, controlling a gain value of the multi-stage equalizer according to the optimized equalization gain identifier.
A synchronous modulation method based on an embedded player. The method comprises the steps of: Step S1, acquiring a current timestamp adopted by a current synchronous audio signal and a current synchronous video signal; Step S2, acquiring a jump difference value of the current timestamp; Step S3, determining whether the jump difference value is less than a first preset time, if yes, synchronously playing, by the player, the audio signal and the video signal through a first timestamp, and exiting; and Step S4, determining whether the jump difference value is greater than a second preset time, if yes, synchronously playing, by the player, the audio signal and the video signal through a second timestamp, and exiting.
H04N 5/05 - Synchronising circuits with arrangements for extending range of synchronisation, e.g. by using switching between several time constants
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
H04N 21/6587 - Control parameters, e.g. trick play commands or viewpoint selection
H04N 21/845 - Structuring of content, e.g. decomposing content into time segments
93.
Phase difference generator error compensation method of digital frequency generator
The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.
G06F 1/06 - Clock generators producing several clock signals
H03K 5/26 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
The invention relates to a high-speed decision device that comprises a first branch and a second branch that are connected in parallel between a power supply end and a clock signal input end; wherein the first branch is used for providing a normal-phase input end, and the second branch is used for providing an inverted-phase input end; a first adjusting point and a second adjusting point are arranged; and an adjusting branch is arranged between the first adjusting point and the second adjusting point, and the adjusting branch is used for adjusting the response speed when the clock signal changes. The benefit of the invention is that the response time of the circuit is further improved, the resolution of the high-speed decision device is improved, and the clock and data recovery performance of the high-speed decision device is further improved.
A phase interpolator includes a phase adjusting circuit. The phase adjusting circuit includes a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputs a first clock signal, and the second phase adjusting module outputs a second clock signal; the first phase adjustment module and the second phase adjustment module are connected in parallel to output an interpolation signal. Through the first phase adjustment module and the second phase adjustment module the first clock signal and the second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
The present invention relates to the field of voice activity detection technologies, and more particularly, to a voice activity detection method. The method comprises: providing an acquisition unit for acquiring an external sound signal; providing a judgment unit for judging whether the sound signal is a voice signal; if the sound signal is a voice signal, starting a voice processing unit for processing the sound signal; if the sound signal is not a voice signal, the voice processing unit is kept in a sleep state. With the voice activity detection method, the voice processing unit with large power consumption is made to be in a sleep state for a long time, and therefore, the entire system can be kept in a low-power consumption state; the voice activity detection method is low in implementation cost and can obtain better performance with a small amount of calculation and less resource consumption.
G10L 25/78 - Detection of presence or absence of voice signals
G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
G10L 25/21 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being power information
G10L 25/24 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being the cepstrum
G10L 21/0364 - Speech enhancement, e.g. noise reduction or echo cancellation by changing the amplitude for improving intelligibility
97.
Live time-shifted video play-continuing method and IPTV player
The invention provides a live time-shifted video play-continuing method during disconnection and an IPTV player. The method comprises: connecting to a network to obtain a data stream of a video; playing the data stream through a player to obtain a play starting time of the video; acquiring a played duration of the video when the network is disconnected; acquiring a time point of playing interruption of the video according to the play starting time and the played duration when the network is connected again; and returning to the time point through the player, and continuing to play the video at the time point. The beneficial effects of the invention are as follows: directly performing the breakpoint continuous playing of the live time-shifted video from the network disconnection time point after the network is reconnected.
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
The invention provides a network outage continued playing method of an on-demand video, and an IPTV playing device, wherein the method comprises: connecting a network to acquire a data stream of the video; playing, by a player, the data stream, and obtaining a start playing time of the video; in the case of network outage, obtaining the playing time length of playing the video; when network is connected again, obtaining a time point according to the start playing time and the playing time length; searching for, by the player, according to the time point, and starting to continue to play the video at the display time label of the key frame. The present invention has the beneficial effects of directly performing the breakpoint continued playing of the on-demand video from the network outage time point when the network is connected again.
H04N 21/647 - Control signaling between network components and server or clientsNetwork processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load or bridging between two different networks, e.g. between IP and wireless
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
The invention comprises a playing memory management method, comprising: Step S1, creating a contiguous memory area: Step S2, dividing a contiguous first memory range from the memory area when digital rights management playing information is received; Step S3, setting, by a secure operating system, an access permission for the first memory range; Step S4, performing, by the secure operating system, a decoding operation in the first memory range until the decoding operation is completed; and Step S5, clearing, by the secure operating system, data in the first memory range, releasing the access permission for the first memory range, and releasing the first memory range. The present invention has the beneficial effects that the memory sharing is realized by creating one memory area, setting the access permission during use and clearing data and releasing the access permission after use, so that the manufacturing cost is reduced.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
The invention relates to the technical field of software systems, and more particularly, to a time division multiplexing method for decoding hardware. The method comprises: Step S1, providing a decoding hardware; Step S2, instantiating the decoding hardware into a first decoder and a second decoder; and Step S3, decoding a first data stream through the first decoder, and decoding a second data stream through the second decoder. Compared to the prior art, the present invention has the advantages that the efficiency of the decoder is improved, and the detect that the efficiency is insufficient due to the fact that the decoder runs under high-load decoding through software when the decoder is insufficient in video call application is overcome, and meanwhile, under the condition that multiple hardware decoders exist, the hardware resources are saved, and a new idea is provided for the running cost.
