Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/39 - Circuit design at the physical level
• G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G01R 31/3181 - Functional testing
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/39 - Circuit design at the physical level
• G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 17/50 - Computer-aided design
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/39 - Circuit design at the physical level
• G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two module representations of the plurality of module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the plurality of module representations, and the one or more connections. The test scenario model includes a path from the input via the plurality of module representations and the one or more connections to the desired output.

IPC Classes  ?

• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 17/50 - Computer-aided design
• G01R 31/3181 - Functional testing
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 17/50 - Computer-aided design
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/39 - Circuit design at the physical level
• G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 11/25 - Testing of logic operation, e.g. by logic analysers

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3181 - Functional testing
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 17/50 - Computer-aided design
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06T 11/20 - Drawing from basic elements, e.g. lines or circles

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G06F 17/50 - Computer-aided design
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

IPC Classes  ?

• G01R 31/3181 - Functional testing
• G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 17/50 - Computer-aided design
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers