MIPS Tech, LLC

United States of America

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IPC Class
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode 59
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead 59
G06F 9/46 - Multiprogramming arrangements 18
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems 13
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1.

Implicit Global Pointer Relative Addressing for Global Memory Access

      
Application Number 18990578
Status Pending
Filing Date 2024-12-20
First Publication Date 2025-04-24
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Taylor, Morgyn
  • Fortune, Matthew
  • Fuhler, Richard
  • Patel, Sanjay

Abstract

Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 9/34 - Addressing or accessing the instruction operand or the result
  • G06F 9/355 - Indexed addressing
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

2.

MIPS

      
Application Number 1825271
Status Registered
Filing Date 2024-10-02
Registration Date 2024-10-02
Owner MIPS TECH, LLC (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Microprocessors; integrated circuits; computer central processing units. Computer system design services; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; development of computer platforms.

3.

Neural network data computation using mixed-precision

      
Application Number 18650612
Grant Number 12307370
Status In Force
Filing Date 2024-04-30
First Publication Date 2024-11-07
Grant Date 2025-05-20
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Patel, Sanjay

Abstract

Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.

IPC Classes  ?

  • G06N 3/08 - Learning methods
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 5/022 - Knowledge engineeringKnowledge acquisition

4.

MIPS

      
Application Number 236513800
Status Pending
Filing Date 2024-10-02
Owner MIPS TECH, LLC (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

(1) Microprocessors; integrated circuits; computer central processing units. (1) Computer system design services; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; development of computer platforms.

5.

VIRTUALIZED-IN-HARDWARE INPUT OUTPUT MEMORY MANAGEMENT

      
Application Number 18409141
Status Pending
Filing Date 2024-01-10
First Publication Date 2024-05-16
Owner MIPS Tech, LLC (USA)
Inventor
  • Patel, Sanjay
  • Rozario, Ranjit J.

Abstract

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

6.

Neural network processing using specialized data representation

      
Application Number 18540669
Grant Number 12327170
Status In Force
Filing Date 2023-12-14
First Publication Date 2024-04-18
Grant Date 2025-06-10
Owner MIPS Tech, LLC (USA)
Inventor Patel, Sanjay

Abstract

Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06F 1/16 - Constructional details or arrangements
  • G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
  • G06F 17/16 - Matrix or vector computation
  • G06N 3/08 - Learning methods

7.

Translating virtual memory addresses to physical memory addresses

      
Application Number 17960006
Grant Number 12265475
Status In Force
Filing Date 2022-10-04
First Publication Date 2024-04-04
Grant Date 2025-04-01
Owner MIPS Tech, LLC (USA)
Inventor Robinson, James

Abstract

In one embodiment, a method includes accessing a virtual address from a request to access a memory of the computing device, where virtual addresses are translated to physical addresses of physical memory in the computing device using an N-level page table, and the lowest level of the page table contains page-table entries specifying the physical address of a frame of physical memory. The method includes searching, using the virtual address, a translation lookaside buffer (TLB) including a plurality of TLB entries, each TLB entry including (1) a tag identifying a virtual address associated with the entry and (2) a page-table entry specifying the physical address of a lower-level page table or of a frame of physical memory associated with the virtual address identified in the tag; and iteratively performing, until the virtual address is translated to a physical address, an address-translation procedure that depends on the cached TLB entries.

IPC Classes  ?

  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

8.

MIPS

      
Serial Number 98482145
Status Pending
Filing Date 2024-04-03
Owner MIPS TECH, LLC ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Microprocessors; Integrated circuits; Computer central processing units Computer system design services; Consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; Development of computer platforms

9.

Miscellaneous Design

      
Serial Number 98482205
Status Pending
Filing Date 2024-04-03
Owner MIPS TECH, LLC ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Microprocessors; Integrated circuits; Computer central processing units Computer system design services; Consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; Development of computer platforms

10.

Neural network data computation using mixed-precision

      
Application Number 18114044
Grant Number 12001953
Status In Force
Filing Date 2023-02-24
First Publication Date 2023-07-27
Grant Date 2024-06-04
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Patel, Sanjay

Abstract

Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.

IPC Classes  ?

  • G06N 3/08 - Learning methods
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

11.

Address manipulation using indices and tags

      
Application Number 18118580
Grant Number 11829764
Status In Force
Filing Date 2023-03-07
First Publication Date 2023-06-29
Grant Date 2023-11-28
Owner MIPS Tech, LLC (USA)
Inventor
  • Pota, Parthiv
  • Patel, Sanjay
  • Singh Parihar, Raj Kumar

Abstract

Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

12.

Virtualized-in-hardware input output memory management

      
Application Number 18078495
Grant Number 11907542
Status In Force
Filing Date 2022-12-09
First Publication Date 2023-04-06
Grant Date 2024-02-20
Owner MIPS Tech, LLC (USA)
Inventor
  • Patel, Sanjay
  • Rozario, Ranjit J.

Abstract

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

13.

Address manipulation using indices and tags

      
Application Number 17364718
Grant Number 11635963
Status In Force
Filing Date 2021-06-30
First Publication Date 2021-12-02
Grant Date 2023-04-25
Owner MIPS Tech, LLC (USA)
Inventor
  • Pota, Parthiv
  • Patel, Sanjay
  • Singh Parihar, Raj Kumar

Abstract

Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

14.

Neural network data computation using mixed-precision

      
Application Number 16985307
Grant Number 11615307
Status In Force
Filing Date 2020-08-05
First Publication Date 2021-02-04
Grant Date 2023-03-28
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Patel, Sanjay

Abstract

Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.

IPC Classes  ?

  • G06N 3/08 - Learning methods
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

15.

Virtualized-in-hardware input output memory management

      
Application Number 16865851
Grant Number 11599270
Status In Force
Filing Date 2020-05-04
First Publication Date 2020-08-20
Grant Date 2023-03-07
Owner MIPS Tech, LLC (USA)
Inventor
  • Patel, Sanjay
  • Rozario, Ranjit J

Abstract

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

16.

Address manipulation using indices and tags

      
Application Number 16739540
Grant Number 11080062
Status In Force
Filing Date 2020-01-10
First Publication Date 2020-07-16
Grant Date 2021-08-03
Owner MIPS Tech, LLC (USA)
Inventor
  • Pota, Parthiv
  • Patel, Sanjay
  • Singh Parihar, Raj Kumar

Abstract

Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N−1), and the branch history in table T(N−1) is of greater length than the branch history of table T(N−2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

17.

ADDRESS MANIPULATION USING INDICES AND TAGS

      
Application Number US2020013075
Publication Number 2020/146724
Status In Force
Filing Date 2020-01-10
Publication Date 2020-07-16
Owner MIPS TECH, LLC (USA)
Inventor
  • Pota, Parthiv
  • Patel, Sanjay
  • Parihar, Raj Kumar, Singh

Abstract

Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

IPC Classes  ?

  • G06F 9/355 - Indexed addressing
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter

18.

NEURAL NETWORK PROCESSING USING MIXED-PRECISION DATA REPRESENTATION

      
Application Number 16778258
Status Pending
Filing Date 2020-01-31
First Publication Date 2020-06-25
Owner MIPS Tech, LLC (USA)
Inventor Patel, Sanjay

Abstract

Techniques for neural network processing using mixed-precision data representation are disclosed. Access to a processor that supports single-precision operations is obtained, where the processor is used for neural network calculations. A first input data element and a second input data element are presented for manipulation on the processor, where the manipulation supports the neural network calculations. The first input data element is manipulated with the second input data element using the processor, where the first input data element comprises a 16-bit reduced floating point representation. A result of the manipulation is output, where the result comprises a single-precision data representation element. The result is forwarded to a next layer of the neural network, based on the outputting.

IPC Classes  ?

19.

Neural network processing using specialized data representation

      
Application Number 16704263
Grant Number 11893470
Status In Force
Filing Date 2019-12-05
First Publication Date 2020-06-11
Grant Date 2024-02-06
Owner MIPS TECH, LLC (USA)
Inventor Patel, Sanjay

Abstract

Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.

IPC Classes  ?

  • G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/08 - Learning methods
  • G06F 1/16 - Constructional details or arrangements
  • G06F 17/16 - Matrix or vector computation

20.

NEURAL NETWORK PROCESSING USING SPECIALIZED DATA REPRESENTATION

      
Application Number US2019064677
Publication Number 2020/118051
Status In Force
Filing Date 2019-12-05
Publication Date 2020-06-11
Owner MIPS TECH, LLC (USA)
Inventor Patel, Sanjay

Abstract

Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloatl6 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add- accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.

IPC Classes  ?

  • G06N 3/08 - Learning methods
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

21.

Hardware virtualized input output memory management unit

      
Application Number 14589693
Grant Number 10642501
Status In Force
Filing Date 2015-01-05
First Publication Date 2020-05-05
Grant Date 2020-05-05
Owner MIPS Tech, LLC (USA)
Inventor
  • Patel, Sanjay
  • Rozario, Ranjit J

Abstract

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

22.

UNALIGNED MEMORY ACCESSES

      
Application Number US2018050999
Publication Number 2019/055738
Status In Force
Filing Date 2018-09-14
Publication Date 2019-03-21
Owner MIPS TECH, LLC (USA)
Inventor
  • Robinson, James, Hippisley
  • Taylor, Morgyn
  • Fuhler, Richard
  • Patel, Sanjay

Abstract

A processor is configured to implement an instruction set architecture for accessing data that includes loading data elements from a memory containing data blocks separated by block boundaries. The instruction set architecture includes a first type of data load instruction for loading an aligned data structure from the memory and a second type of data load instruction for loading an unaligned data structure from the memory. The loading includes fetching a data load instruction of the second type and loading from the memory according to the data load instruction of the second type. The resulting data structure formed of n consecutive data elements is determined from the data load instruction. The data structure loaded from memory is formed of n consecutive unaligned data elements. The processor is similarly configured to implement storing data elements from a set of registers to a memory containing data blocks separated by block boundaries.

IPC Classes  ?

  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

23.

SAVING AND RESTORING NON-CONTIGUOUS BLOCKS OF PRESERVED REGISTERS

      
Application Number US2018049128
Publication Number 2019/046742
Status In Force
Filing Date 2018-08-31
Publication Date 2019-03-07
Owner MIPS TECH, LLC (USA)
Inventor
  • Robinson, James, Hippisley
  • Taylor, Morgyn
  • Fortune, Matthew

Abstract

Described herein are instruction set architectures (ISAs), and related data processing apparatuses and methods, with two or more non-contiguous blocks of preserved registers wherein the registers to be saved or restored are identified in a save or restore instruction via a number of registers to be saved/restored (Num_Reg) and a starting register (rStart). Specifically, in the ISAs, apparatuses, and methods described herein, the registers to be saved or restored are identified as the Num_Reg registers in a predetermined sequence starting with rStart wherein, in the predetermined sequence, each register is followed by the next highest numbered register except the highest numbered preserved register, which is followed by the lowest numbered preserved register.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

24.

Fault detecting and fault tolerant multi-threaded processors

      
Application Number 16100706
Grant Number 10782977
Status In Force
Filing Date 2018-08-10
First Publication Date 2019-03-07
Grant Date 2020-09-22
Owner MIPS Tech, LLC (USA)
Inventor
  • Mace, Timothy Charles
  • Kinter, Ryan C

Abstract

Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

25.

UNIFIED LOGIC FOR ALIASED PROCESSOR INSTRUCTIONS

      
Application Number US2018049080
Publication Number 2019/046710
Status In Force
Filing Date 2018-08-31
Publication Date 2019-03-07
Owner MIPS TECH, LLC (USA)
Inventor
  • Robinson, James, Hippisley
  • Taylor, Morgyn

Abstract

A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

26.

POINTER-SIZE CONTROLLED INSTRUCTION PROCESSING

      
Application Number US2018049089
Publication Number 2019/046716
Status In Force
Filing Date 2018-08-31
Publication Date 2019-03-07
Owner MIPS TECH, LLC (USA)
Inventor
  • Robinson, James, Hippisley
  • Taylor, Morgyn

Abstract

Instruction set architectures (ISAs) and apparatus and methods related thereto comprise a variable length instruction set that includes one or more pointer-size controlled memory access instructions of a smaller length (e.g. 16 bits) wherein the size of the data accessed by such an instruction is dynamically determined based on the size of the pointer. Specifically, when a pointer-size controlled memory access instruction is received at a decode unit, the decode unit outputs one or more control signals to cause an execution unit to perform a memory access of a first size (e.g. 32 bits) when the pointer size is the first size (e.g. 32 bits), and output one or more control signals to cause the execution unit to perform a memory access of a second size (e.g. 64 bits) when the pointer size is the second size (e.g. 64 bits).

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

27.

IMPLICIT GLOBAL POINTER RELATIVE ADDRESSING FOR GLOBAL MEMORY ACCESS

      
Application Number US2018049099
Publication Number 2019/046723
Status In Force
Filing Date 2018-08-31
Publication Date 2019-03-07
Owner MIPS TECH, LLC (USA)
Inventor
  • Robinson, James, Hippisley
  • Taylor, Morgyn
  • Fortune, Matthew
  • Fuhler, Richard
  • Patel, Sanjay

Abstract

Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

28.

Implicit global pointer relative addressing for global memory access

      
Application Number 16119291
Grant Number 12210876
Status In Force
Filing Date 2018-08-31
First Publication Date 2019-02-28
Grant Date 2025-01-28
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Taylor, Morgyn
  • Fortune, Matthew
  • Fuhler, Richard
  • Patel, Sanjay

Abstract

Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 9/34 - Addressing or accessing the instruction operand or the result
  • G06F 9/355 - Indexed addressing
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

29.

Unified logic for aliased processor instructions

      
Application Number 16119487
Grant Number 10846089
Status In Force
Filing Date 2018-08-31
First Publication Date 2019-02-28
Grant Date 2020-11-24
Owner MIPS Tech, LLC (USA)
Inventor
  • Robinson, James Hippisley
  • Taylor, Morgyn

Abstract

A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

IPC Classes  ?

  • G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 9/34 - Addressing or accessing the instruction operand or the result
  • G06F 9/355 - Indexed addressing
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

30.

FAULT DETECTING AND FAULT TOLERANT MULTI-THREADED PROCESSORS

      
Application Number US2018046246
Publication Number 2019/032980
Status In Force
Filing Date 2018-08-10
Publication Date 2019-02-14
Owner MIPS TECH, LLC (USA)
Inventor
  • Mace, Timothy, Charles
  • Kinter, Ryan, C.

Abstract

Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.

IPC Classes  ?

  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

31.

Check pointing a shift register with a circular buffer

      
Application Number 16036104
Grant Number 10642527
Status In Force
Filing Date 2018-07-16
First Publication Date 2018-11-08
Grant Date 2020-05-05
Owner MIPS Tech, LLC (USA)
Inventor
  • Day, Philip
  • Bailey, Julian

Abstract

Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

32.

Decoding instructions that are modified by one or more other instructions

      
Application Number 15874724
Grant Number 10379861
Status In Force
Filing Date 2018-01-18
First Publication Date 2018-05-24
Grant Date 2019-08-13
Owner MIPS Tech, LLC (USA)
Inventor Whittaker, James Robert

Abstract

Methods and apparatus are provided for decoding instructions in a computer program wherein the instructions include one or more base instructions that are subject to modification by one or more other instructions. A decoder determines whether a first received instruction was arrived at by a non-incremental change to a program counter (i.e. a jump in the program). If the first instruction was arrived at by a non-incremental change to the program counter the decoder decodes the immediately preceding instruction to determine if the original instruction is a base instruction subject to modification by one or more other instructions. If the preceding instruction indicates that the original instruction is a base instruction an error has occurred and exception handling code is invoked.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

33.

Migration of data to register file cache

      
Application Number 15833555
Grant Number 10678695
Status In Force
Filing Date 2017-12-06
First Publication Date 2018-04-05
Grant Date 2020-06-09
Owner MIPS Tech, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

IPC Classes  ?

  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

34.

Translation lookaside buffer

      
Application Number 15824613
Grant Number 10185665
Status In Force
Filing Date 2017-11-28
First Publication Date 2018-03-29
Grant Date 2019-01-22
Owner MIPS Tech, LLC (USA)
Inventor
  • Rozario, Ranjit J.
  • Patel, Sanjay

Abstract

Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

IPC Classes  ?

  • G06F 12/10 - Address translation
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/0844 - Multiple simultaneous or quasi-simultaneous cache accessing
  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

35.

Indirect branch prediction

      
Application Number 15707059
Grant Number 10261798
Status In Force
Filing Date 2017-09-18
First Publication Date 2018-01-04
Grant Date 2019-04-16
Owner MIPS Tech, LLC (USA)
Inventor Manoukian, Manouk

Abstract

Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. When a new indirect branch instruction is received for prediction, the indirect path history and the taken/not-taken history are combined to generate an index for the indirect branch instruction. The generated index is then used to identify a predicted target address in the table. If the identified predicted target address is valid, then the target address of the indirect branch instruction is predicted to be the predicted target address.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

36.

Fetching instructions in an instruction fetch unit

      
Application Number 15624121
Grant Number 10372453
Status In Force
Filing Date 2017-06-15
First Publication Date 2017-12-21
Grant Date 2019-08-06
Owner MIPS Tech, LLC (USA)
Inventor
  • Webber, Andrew David
  • Martínez, Daniel Ángel Chaver
  • Algarabel, Enrique Sedano

Abstract

A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

37.

Processors supporting atomic writes to multiword memory locations and methods

      
Application Number 15092915
Grant Number 10649773
Status In Force
Filing Date 2016-04-07
First Publication Date 2017-10-12
Grant Date 2020-05-12
Owner MIPS Tech, LLC (USA)
Inventor
  • Rozario, Ranjit J.
  • Glew, Andrew F.
  • Patel, Sanjay
  • Robinson, James
  • Ranganathan, Sudhakar

Abstract

A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

38.

Control of pre-fetch traffic

      
Application Number 15488649
Grant Number 10754778
Status In Force
Filing Date 2017-04-17
First Publication Date 2017-08-03
Grant Date 2020-08-25
Owner MIPS Tech, LLC (USA)
Inventor Meredith, Jason

Abstract

Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. This identifier flags the request as a pre-fetch request rather than a non-pre-fetch request, such as a time-critical request. Based on this identifier, the memory hierarchy can then issue an abort response at times of high traffic which suppresses the pre-fetch traffic, as the pre-fetch traffic is not fulfilled by the memory hierarchy. On receipt of an abort response, the device deletes at least a part of any record of the pre-fetch request and if the data/instruction is later required, a new request is issued at a higher priority than the original pre-fetch request.

IPC Classes  ?

  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • H04L 12/851 - Traffic type related actions, e.g. QoS or priority
  • H04L 12/911 - Network admission control and resource allocation, e.g. bandwidth allocation or in-call renegotiation
  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels

39.

Execution of load instructions in a processor

      
Application Number 15001628
Grant Number 10459725
Status In Force
Filing Date 2016-01-20
First Publication Date 2017-07-20
Grant Date 2019-10-29
Owner MIPS Tech, LLC (USA)
Inventor
  • Modi, Harit
  • Yamamoto, Wayne

Abstract

Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. Load instructions having a nonzero offset can be executed in an address generation stage as is conventional. To avoid conflicts between a current load instruction with zero offset and a previous load instruction with nonzero offset, the current instruction can be rescheduled or sent through a separate dedicated load pipe. An alternative technique permits a load instruction with zero offset to be issued one cycle earlier than it would need to be if it had a nonzero offset, thus reducing load latency.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

40.

Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

      
Application Number 15467073
Grant Number 10318296
Status In Force
Filing Date 2017-03-23
First Publication Date 2017-07-06
Grant Date 2019-06-11
Owner MIPS Tech, LLC (USA)
Inventor Webber, Andrew

Abstract

A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

41.

Migration of data to register file cache

      
Application Number 15438000
Grant Number 09858194
Status In Force
Filing Date 2017-02-21
First Publication Date 2017-06-15
Grant Date 2018-01-02
Owner MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

IPC Classes  ?

  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

42.

Fetch ahead branch target buffer

      
Application Number 14935579
Grant Number 10664280
Status In Force
Filing Date 2015-11-09
First Publication Date 2017-05-11
Grant Date 2020-05-26
Owner MIPS Tech, LLC (USA)
Inventor
  • Pota, Parthiv
  • Patel, Sanjay
  • Ranganathan, Sudhakar

Abstract

A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

43.

Resource sharing using process delay

      
Application Number 15404743
Grant Number 09940168
Status In Force
Filing Date 2017-01-12
First Publication Date 2017-05-04
Grant Date 2018-04-10
Owner MIPS Tech, LLC (USA)
Inventor Chandra, Debasish

Abstract

Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

44.

Prioritizing instructions based on type

      
Application Number 15387394
Grant Number 10001997
Status In Force
Filing Date 2016-12-21
First Publication Date 2017-04-13
Grant Date 2018-06-19
Owner MIPS Tech, LLC (USA)
Inventor
  • Khot, Anand
  • Jackson, Hugh

Abstract

Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

45.

Fetch unit for predicting target for subroutine return instructions

      
Application Number 15281661
Grant Number 10360037
Status In Force
Filing Date 2016-09-30
First Publication Date 2017-03-30
Grant Date 2019-07-23
Owner MIPS Tech, LLC (USA)
Inventor Day, Philip

Abstract

A fetch unit configured to, in response to detecting a subroutine call and link instruction, calculate and store a predicted target address for the corresponding subroutine return instruction in a prediction stack, and if certain conditions are met, also cause to be stored in the prediction stack a predicted target instruction bundle. The fetch unit is also configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and if certain conditions are met, cause any valid predicted target instruction bundle in the prediction stack to be the next bundle to be decoded.

IPC Classes  ?

  • G06F 9/34 - Addressing or accessing the instruction operand or the result
  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

46.

Check pointing a shift register using a circular buffer

      
Application Number 15205555
Grant Number 10025527
Status In Force
Filing Date 2016-07-08
First Publication Date 2017-01-12
Grant Date 2018-07-17
Owner MIPS Tech, LLC (USA)
Inventor
  • Day, Philip
  • Bailey, Julian

Abstract

Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

47.

Translation lookaside buffer

      
Application Number 14715117
Grant Number 09830275
Status In Force
Filing Date 2015-05-18
First Publication Date 2016-11-24
Grant Date 2017-11-28
Owner MIPS TECH, LLC (USA)
Inventor
  • Rozario, Ranjit J.
  • Patel, Sanjay

Abstract

Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support virtualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.

IPC Classes  ?

  • G06F 12/10 - Address translation
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F 12/0844 - Multiple simultaneous or quasi-simultaneous cache accessing
  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

48.

Fault tolerant processor for real-time systems

      
Application Number 14741738
Grant Number 10423417
Status In Force
Filing Date 2015-06-17
First Publication Date 2016-11-03
Grant Date 2019-09-24
Owner MIPS Tech, LLC (USA)
Inventor Bailey, Julian

Abstract

A fault tolerant multi-threaded processor uses the temporal and/or spatial separation of instructions running in two or more different threads. An instruction is fetched, decoded and executed by each of two or more threads to generate a result for each of the two or more threads. These results are then compared using comparison hardware logic and if there is a mismatch between the results obtained, then an error or event is raised. The comparison is performed on an instruction by instruction basis so that errors are identified (and hence can be resolved) quickly.

IPC Classes  ?

  • G06F 11/00 - Error detectionError correctionMonitoring
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

49.

Cache operation in a multi-threaded processor

      
Application Number 14873027
Grant Number 10318172
Status In Force
Filing Date 2015-10-01
First Publication Date 2016-10-13
Grant Date 2019-06-11
Owner MIPS Tech, LLC (USA)
Inventor Day, Philip

Abstract

Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

50.

Speculative load issue

      
Application Number 15183365
Grant Number 09910672
Status In Force
Filing Date 2016-06-15
First Publication Date 2016-10-06
Grant Date 2018-03-06
Owner MIPS Tech, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

51.

Crossing pipelined data between circuitry in different clock domains

      
Application Number 15150177
Grant Number 09740454
Status In Force
Filing Date 2016-05-09
First Publication Date 2016-09-01
Grant Date 2017-08-22
Owner MIPS TECH, LLC (USA)
Inventor Rozario, Ranjit J.

Abstract

An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter
  • G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
  • G06F 15/00 - Digital computers in generalData processing equipment in general

52.

Register file having a plurality of sub-register files

      
Application Number 14842983
Grant Number 09672039
Status In Force
Filing Date 2015-09-02
First Publication Date 2016-09-01
Grant Date 2017-06-06
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

53.

Prioritising of instruction fetching in microprocessor systems

      
Application Number 15134510
Grant Number 09870228
Status In Force
Filing Date 2016-04-21
First Publication Date 2016-08-11
Grant Date 2018-01-16
Owner MIPS TECH, LLC (USA)
Inventor Webber, Andrew

Abstract

A method and a system are provided for prioritising the fetching of instructions for each of a plurality of executing instruction threads in a multi-threaded processor. Instructions come from at least one source of instructions. Each thread has a number of threads buffered for execution in an instruction buffer. A first metric for each thread is determined based on the number of instructions currently buffered. A second metric is then determined for each thread, this being an execution based metric. A priority order for the threads is determined from the first and second metrics, and an instruction is fetched from the source for the thread with the highest determined priority which is requesting an instruction.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 1/10 - Distribution of clock signals

54.

Migration of data to register file cache

      
Application Number 15019132
Grant Number 09612968
Status In Force
Filing Date 2016-02-09
First Publication Date 2016-06-02
Grant Date 2017-04-04
Owner
  • MIPS TECH, LLC (USA)
  • MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

55.

Method and apparatus for scheduling the issue of instructions in a multithreaded processor

      
Application Number 14930913
Grant Number 10360038
Status In Force
Filing Date 2015-11-03
First Publication Date 2016-02-25
Grant Date 2019-07-23
Owner MIPS Tech, LLC (USA)
Inventor Webber, Andrew

Abstract

A method to dynamically determine which instructions from a plurality of available instructions to issue in each clock cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle, comprises the steps of: determining a highest priority instruction from the plurality of available instructions; determining the compatibility of the highest priority instruction with each of the remaining available instructions; and issuing the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle; wherein the highest priority instruction cannot be a speculative instruction. The effect of this is that speculative instructions are only ever issued together with at least one non-speculative instruction.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

56.

Processors and methods for cache sparing stores

      
Application Number 14829458
Grant Number 10108548
Status In Force
Filing Date 2015-08-18
First Publication Date 2016-02-25
Grant Date 2018-10-23
Owner MIPS Tech, LLC (USA)
Inventor
  • Rozario, Ranjit J.
  • Nangia, Era
  • Chandra, Debasish
  • Sudhakar, Ranganathan

Abstract

In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0815 - Cache consistency protocols
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

57.

Method and apparatus for ensuring data cache coherency

      
Application Number 14791699
Grant Number 09703709
Status In Force
Filing Date 2015-07-06
First Publication Date 2016-02-04
Grant Date 2017-07-11
Owner MIPS TECH, LLC (USA)
Inventor
  • Isherwood, Robert Graham
  • Ko, Yin Nam

Abstract

A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 12/0815 - Cache consistency protocols
  • G06F 9/45 - Compilation or interpretation of high level programme languages
  • G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

58.

Conditional branch prediction using a long history

      
Application Number 14809187
Grant Number 10318304
Status In Force
Filing Date 2015-07-25
First Publication Date 2016-01-28
Grant Date 2019-06-11
Owner MIPS Tech, LLC (USA)
Inventor Manoukian, Manouk Vartan

Abstract

Methods and conditional branch predictors for predicting an outcome of a conditional branch instruction in a program executed by a processor using a long conditional branch history include generating a first index from a first portion of the conditional branch history and a second index from a second portion of the conditional branch history. The first index is then used to identify an entry in a first pattern history table including first prediction information; and the second index is used to identify an entry in a second pattern history table including second prediction information. The outcome of the conditional branch is predicted based on the first and second prediction information.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

59.

Processor arranged to operate as a single-threaded (nX)-bit processor and as an n-threaded X-bit processor in different modes of operation

      
Application Number 14798841
Grant Number 10048967
Status In Force
Filing Date 2015-07-14
First Publication Date 2016-01-14
Grant Date 2018-08-14
Owner MIPS Tech, LLC (USA)
Inventor Jackson, Hugh

Abstract

Methods of running a 32-bit operating system on a 64-bit processor are described. In an embodiment, the processor comprises 64-bit hardware and when running a 64-bit operating system operates as a single-threaded processor. However, when running a 32-bit operating system (which may be a guest operating system running on a virtual machine), the processor operates as a two-threaded core. The register file is logically divided into two portions, one for each thread, and logic within a functional unit may be split between threads, shared between threads or duplicated to provide an instance of the logic for each thread. Configuration bits may be set to indicate whether the processor should operate as a single-threaded or multi-threaded device.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines

60.

Resource sharing using process delay

      
Application Number 14837109
Grant Number 09563476
Status In Force
Filing Date 2015-08-27
First Publication Date 2015-12-24
Grant Date 2017-02-07
Owner
  • MIPS TECH, LLC (USA)
  • MIPS TECH, LLC (USA)
Inventor Chandra, Debasish

Abstract

Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

61.

Decoding instructions that are modified by one or more other instructions

      
Application Number 14722292
Grant Number 09898293
Status In Force
Filing Date 2015-05-27
First Publication Date 2015-12-03
Grant Date 2018-02-20
Owner MIPS Tech, LLC (USA)
Inventor Whittaker, James Robert

Abstract

Methods and apparatus are provided for decoding instructions in a computer program wherein the instructions include one or more base instructions that are subject to modification by one or more other instructions. A decoder determines whether a first received instruction was arrived at by a non-incremental change to a program counter (i.e. a jump in the program). If the first instruction was arrived at by a non-incremental change to the program counter the decoder decodes the immediately preceding instruction to determine if the original instruction is a base instruction subject to modification by one or more other instructions. If the preceding instruction indicates that the original instruction is a base instruction an error has occurred and exception handling code is invoked.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

62.

Restoring a register renaming map

      
Application Number 14816651
Grant Number 09436470
Status In Force
Filing Date 2015-08-03
First Publication Date 2015-11-26
Grant Date 2016-09-06
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer whilst the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.

IPC Classes  ?

  • G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F 15/76 - Architectures of general purpose stored program computers
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

63.

Allocating resources to threads based on speculation metric

      
Application Number 14754436
Grant Number 09606834
Status In Force
Filing Date 2015-06-29
First Publication Date 2015-10-22
Grant Date 2017-03-28
Owner MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Rowland, Paul

Abstract

Methods, reservation stations and processors for allocating resources to a plurality of threads based on the extent to which the instructions associated with each of the threads are speculative. The method comprises receiving a speculation metric for each thread at a reservation station. Each speculation metric represents the extent to which the instructions associated with a particular thread are speculative. The more speculative an instruction, the more likely the instruction has been incorrectly predicted by a branch predictor. The reservation station then allocates functional unit resources (e.g. pipelines) to the threads based on the speculation metrics and selects a number of instructions from one or more of the threads based on the allocation. The selected instructions are then issued to the functional unit resources.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/00 - Arrangements for program control, e.g. control units
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
  • G06F 9/52 - Program synchronisationMutual exclusion, e.g. by means of semaphores

64.

Pipelined ECC-protected memory access

      
Application Number 14612084
Grant Number 09740557
Status In Force
Filing Date 2015-02-02
First Publication Date 2015-08-27
Grant Date 2017-08-22
Owner MIPS TECH, LLC (USA)
Inventor
  • Rozario, Ranjit J
  • Sudhakar, Ranganathan

Abstract

In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

65.

Modeless instruction execution with 64/32-bit addressing

      
Application Number 14612090
Grant Number 10671391
Status In Force
Filing Date 2015-02-02
First Publication Date 2015-08-27
Grant Date 2020-06-02
Owner MIPS Tech, LLC (USA)
Inventor
  • Sudhakar, Ranganathan
  • Rozario, Ranjit J

Abstract

In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/34 - Addressing or accessing the instruction operand or the result

66.

Processor supporting arithmetic instructions with branch on overflow and methods

      
Application Number 14612104
Grant Number 10768930
Status In Force
Filing Date 2015-02-02
First Publication Date 2015-08-13
Grant Date 2020-09-08
Owner MIPS Tech, LLC (USA)
Inventor Sudhakar, Ranganathan

Abstract

A method provides for decoding, in a microprocessor, an instruction into data identifying a first register, a second register, an immediate value, and an opcode identifier. The opcode identifier is interpreted as indicating that an arithmetic operation is to be performed on the first register and the second register, and that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow or underflow. The change of control operation is to a location in a program determined based on the immediate value. A processor can be provided with a decoder and other supporting circuitry to implement such method. Overflow/underflow can be checked on word boundaries of a double-word operation.

IPC Classes  ?

  • G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
  • G06F 9/302 - Controlling the executing of arithmetic operations
  • G06F 9/40 - Arrangements for executing subprogrammes, i.e. combinations of several instructions
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/355 - Indexed addressing
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 7/505 - AddingSubtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

67.

Return stack buffer having multiple address slots per stack entry

      
Application Number 14608630
Grant Number 09361242
Status In Force
Filing Date 2015-01-29
First Publication Date 2015-08-06
Grant Date 2016-06-07
Owner MIPS TECH, LLC (USA)
Inventor
  • Manoukian, Manouk Vartan
  • Jackson, Hugh

Abstract

A return stack buffer (RSB) is modified such that each entry comprises two or more address slots. When a function is called, the address following the function call is pushed to the RSB and stored in a selected one of the address slots in a top entry in the RSB. One or more pointer bits within the entry are set to indicate which slot the address was stored in.

IPC Classes  ?

  • G06F 12/12 - Replacement control
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

68.

Storing look-up table indexes in a return stack buffer

      
Application Number 14608745
Grant Number 09424203
Status In Force
Filing Date 2015-01-29
First Publication Date 2015-08-06
Grant Date 2016-08-23
Owner MIPS TECH, LLC (USA)
Inventor
  • Manoukian, Manouk Vartan
  • Jackson, Hugh

Abstract

A return stack buffers (RSB) is modified to store index values instead of addresses. When a function is called, the address following the function call is stored in a look-up table and the index at which the address is stored is pushed to the RSB. When a function returns, an index is popped from the RSB and used to identify an address in the look-up table. In another embodiment, the RSB is modified such that each entry comprises two or more address slots. When a function is called, the address following the function call is pushed to the RSB and stored in a selected one of the address slots in a top entry in the RSB. One or more pointer bits within the entry are set to indicate which slot the address was stored in.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/12 - Replacement control

69.

Stack saved variable pointer value prediction

      
Application Number 14598415
Grant Number 09934039
Status In Force
Filing Date 2015-01-16
First Publication Date 2015-07-23
Grant Date 2018-04-03
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

Methods of predicting stack pointer values of variables stored in a stack are described. When an instruction is seen which stores a variable in the stack in a position offset from the stack pointer, an entry is added to a data structure which identifies the physical register which currently stores the stack pointer, the physical register which stores the value of the variable and the offset value. Subsequently when an instruction to load a variable from the stack from a position which is identified by reference to the stack pointer is seen, the data structure is searched to see if there is a corresponding entry which includes the same offset and the same physical register storing the stack pointer as the load instruction. If a corresponding entry is found the architectural register in the load instruction is mapped to the physical register storing the value of the variable from the entry.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/44 - Arrangements for executing specific programs

70.

Stack pointer value prediction

      
Application Number 14596407
Grant Number 09652240
Status In Force
Filing Date 2015-01-14
First Publication Date 2015-07-23
Grant Date 2017-05-16
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter which indicates by how much the stack is grown and one or both of: the register ID currently holding the stack pointer value or the current stack pointer value. When a subsequent instruction shrinking the stack is seen, the stored data is searched for one or more entries which has a corresponding size parameter. If such an entry is identified, the other information stored in that entry is used to predict the value of the stack pointer instead of using the instruction to calculate the new stack pointer value. Where register renaming is used, the information in the entry is used to remap the stack pointer to a different physical register.

IPC Classes  ?

  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/312 - Controlling loading, storing or clearing operations
  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

71.

Processor with virtualized instruction set architecture and methods

      
Application Number 14572186
Grant Number 09870225
Status In Force
Filing Date 2014-12-16
First Publication Date 2015-06-25
Grant Date 2018-01-16
Owner MIPS TECH, LLC (USA)
Inventor Sudhakar, Ranganathan

Abstract

A processor comprises a decoder for decoding an instruction based both on an explicit opcode identifier and on metadata encoded in the instruction. For example, a relative order of source register names may be used to decode the instruction. As an example, an instruction set may have a Branch Equal (BEQ) specifying two registers (r1 and r2) that store values that are compared for equality. An instruction set can provide a single opcode identifier for BEQ and a processor can determine whether to decode a particular instance of that opcode identifier as BEQ or another instruction, in dependence on an order of appearance of the source registers in that instance. For example, the BEQ opcode can be interpreted as a branch not equal, if a higher numbered register appears before a lower numbered register. Additional forms of metadata can include interpreting a constant included in an instruction, as well as determining equality of source registers, among other forms of metadata.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

72.

User interface for facilitation of high level generation of processor extensions

      
Application Number 11388484
Grant Number 09064076
Status In Force
Filing Date 2006-03-23
First Publication Date 2015-06-23
Grant Date 2015-06-23
Owner MIPS TECH, LLC (USA)
Inventor
  • Braun, Gunnar
  • Fiedler, Frank
  • Hoffmann, Andreas
  • Intrater, Gideon
  • Lüthje, Olaf
  • Nohl, Achim
  • Rieder, Ludwig

Abstract

Systems and methods of user interface for facilitation of high level generation of processor extensions. In accordance with a method embodiment of the present invention, an instruction format is accessed at a graphical user interface. A programming language description of a computation element for an execution unit of the processor extension is accessed. A representation of a hardware design for the processor extension comprising the instruction format and the computation element is generated.

IPC Classes  ?

73.

Global register protection in a multi-threaded processor

      
Application Number 14625895
Grant Number 09727380
Status In Force
Filing Date 2015-02-19
First Publication Date 2015-06-11
Grant Date 2017-08-08
Owner MIPS TECH, LLC (USA)
Inventor
  • Wang, Guixin
  • Jackson, Hugh
  • Isherwood, Robert Graham

Abstract

Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

74.

Prioritizing instructions based on type

      
Application Number 14340932
Grant Number 09558001
Status In Force
Filing Date 2014-07-25
First Publication Date 2015-04-16
Grant Date 2017-01-31
Owner MIPS TECH, LLC (USA)
Inventor
  • Khot, Anand
  • Jackson, Hugh

Abstract

Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

75.

Crossing pipelined data between circuitry in different clock domains

      
Application Number 14451279
Grant Number 09367286
Status In Force
Filing Date 2014-08-04
First Publication Date 2015-03-05
Grant Date 2016-06-14
Owner MIPS TECH, LLC (USA)
Inventor Rozario, Ranjit J.

Abstract

An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.

IPC Classes  ?

  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter
  • G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
  • G06F 15/00 - Digital computers in generalData processing equipment in general

76.

System for providing trace data in a data processor having a pipelined architecture

      
Application Number 14271886
Grant Number 09720695
Status In Force
Filing Date 2014-05-07
First Publication Date 2015-01-08
Grant Date 2017-08-01
Owner MIPS TECH, LLC (USA)
Inventor
  • Isherwood, Robert Graham
  • Oliver, Ian
  • Webber, Andrew David

Abstract

The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

77.

Control of pre-fetch traffic

      
Application Number 14153223
Grant Number 09658962
Status In Force
Filing Date 2014-01-13
First Publication Date 2014-10-30
Grant Date 2017-05-23
Owner MIPS TECH, LLC (USA)
Inventor Meredith, Jason

Abstract

Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. This identifier flags the request as a pre-fetch request rather than a non-pre-fetch request, such as a time-critical request. Based on this identifier, the memory hierarchy can then issue an abort response at times of high traffic which suppresses the pre-fetch traffic, as the pre-fetch traffic is not fulfilled by the memory hierarchy. On receipt of an abort response, the device deletes at least a part of any record of the pre-fetch request and if the data/instruction is later required, a new request is issued at a higher priority than the original pre-fetch request.

IPC Classes  ?

  • G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels

78.

Indirect branch prediction

      
Application Number 14169771
Grant Number 09792123
Status In Force
Filing Date 2014-01-31
First Publication Date 2014-09-18
Grant Date 2017-10-17
Owner MIPS TECH, LLC (USA)
Inventor Manoukian, Manouk

Abstract

Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. When a new indirect branch instruction is received for prediction, the indirect path history and the taken/not-taken history are combined to generate an index for the indirect branch instruction. The generated index is then used to identify a predicted target address in the table. If the identified predicted target address is valid, then the target address of the indirect branch instruction is predicted to be the predicted target address.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

79.

Apparatus and method for bonding branch instruction with architectural delay slot

      
Application Number 13789467
Grant Number 10540179
Status In Force
Filing Date 2013-03-07
First Publication Date 2014-09-11
Grant Date 2020-01-21
Owner MIPS Tech, LLC (USA)
Inventor
  • Sudhakar, Ranganathan
  • Pota, Parthiv

Abstract

A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

80.

Mechanism for copying data in memory

      
Application Number 14169886
Grant Number 09886212
Status In Force
Filing Date 2014-01-31
First Publication Date 2014-09-11
Grant Date 2018-02-06
Owner MIPS TECH, LLC (USA)
Inventor
  • Meredith, Jason
  • Jackson, Hugh

Abstract

An improved mechanism for copying data in memory is described which uses aliasing. In an embodiment, data is accessed from a first location in a memory and stored in a cache line associated with a second, different location in the memory. In response to a subsequent request for data from the second location in the memory, the cache returns the data stored in the cache line associated with the second location in the memory. The method may be implemented using additional hardware logic in the cache which is arranged to receive an aliasing request from a processor which identifies both the first and second locations in memory and triggers the accessing of data from the first location for storing in a cache line associated with the second location.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 12/10 - Address translation
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

81.

Migration of data to register file cache

      
Application Number 14189719
Grant Number 09292450
Status In Force
Filing Date 2014-02-25
First Publication Date 2014-09-11
Grant Date 2016-03-22
Owner MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

82.

Apparatus and method for operating a processor with an operation cache

      
Application Number 13789443
Grant Number 09189412
Status In Force
Filing Date 2013-03-07
First Publication Date 2014-09-11
Grant Date 2015-11-17
Owner MIPS TECH, LLC (USA)
Inventor Sudhakar, Ranganathan

Abstract

A processor includes a computation engine to produce a computed value for a set of operands. A cache stores the set of operands and the computed value. The cache is configured to selectively identify a match and a miss for a new set of operands. In the event of a match the computed value is supplied by the cache and a computation engine operation is aborted. In the event of a miss a new computed value for the new set of operands is computed by the computation engine and is stored in the cache.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

83.

Resource sharing using process delay

      
Application Number 13780197
Grant Number 09135067
Status In Force
Filing Date 2013-02-28
First Publication Date 2014-08-28
Grant Date 2015-09-15
Owner
  • MIPS TECH, LLC (USA)
  • MIPS TECH, LLC (USA)
Inventor Chandra, Debasish

Abstract

Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

84.

Way lookahead

      
Application Number 13781319
Grant Number 09720840
Status In Force
Filing Date 2013-02-28
First Publication Date 2014-08-28
Grant Date 2017-08-01
Owner MIPS TECH, LLC (USA)
Inventor
  • Sudhakar, Ranganathan
  • Pota, Parthiv

Abstract

Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
  • G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocationRelocation

85.

Speculative load issue

      
Application Number 14169601
Grant Number 09395991
Status In Force
Filing Date 2014-01-31
First Publication Date 2014-08-14
Grant Date 2016-07-19
Owner MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Khot, Anand

Abstract

A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

86.

Allocating resources to threads based on speculation metric

      
Application Number 14157764
Grant Number 09086721
Status In Force
Filing Date 2014-01-17
First Publication Date 2014-08-07
Grant Date 2015-07-21
Owner MIPS TECH, LLC (USA)
Inventor
  • Jackson, Hugh
  • Rowland, Paul

Abstract

Methods, reservation stations and processors for allocating resources to a plurality of threads based on the extent to which the instructions associated with each of the threads are speculative. The method comprises receiving a speculation metric for each thread at a reservation station. Each speculation metric represents the extent to which the instructions associated with a particular thread are speculative. The more speculative an instruction, the more likely the instruction has been incorrectly predicted by a branch predictor. The reservation station then allocates functional unit resources (e.g. pipelines) to the threads based on the speculation metrics and selects a number of instructions from one or more of the threads based on the allocation. The selected instructions are then issued to the functional unit resources.

IPC Classes  ?

  • H03M 1/34 - Analogue value compared with reference values
  • G06F 9/00 - Arrangements for program control, e.g. control units
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

87.

Register file having a plurality of sub-register files

      
Application Number 14157805
Grant Number 09304934
Status In Force
Filing Date 2014-01-17
First Publication Date 2014-08-07
Grant Date 2016-04-05
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

88.

Fill partitioning of a shared cache

      
Application Number 14153240
Grant Number 09645945
Status In Force
Filing Date 2014-01-13
First Publication Date 2014-07-17
Grant Date 2017-05-09
Owner MIPS TECH, LLC (USA)
Inventor Meredith, Jason

Abstract

Fill partitioning of a shared cache is described. In an embodiment, all threads running in a processor are able to access any data stored in the shared cache; however, in the event of a cache miss, a thread may be restricted such that it can only store data in a portion of the shared cache. The restrictions to storing data may be implemented for all cache miss events or for only a subset of those events. For example, the restrictions may be implemented only when the shared cache is full and/or only for particular threads. The restrictions may also be applied dynamically, for example, based on conditions associated with the cache. Different portions may be defined for different threads (e.g. in a multi-threaded processor) and these different portions may, for example, be separate and non-overlapping. Fill partitioning may be applied to any on-chip cache, for example, a L1 cache.

IPC Classes  ?

  • G06F 12/12 - Replacement control
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 12/127 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

89.

Switch statement prediction

      
Application Number 14153188
Grant Number 09298467
Status In Force
Filing Date 2014-01-13
First Publication Date 2014-07-17
Grant Date 2016-03-29
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

Methods and branch predictors for predicting a target location of a jump table switch statement in a program. The method includes continuously monitoring instructions at the branch predictor to determine if they write to registers used to store an input variable to a jump table switch statement. Any update to a monitored register is stored in a register table maintained by the branch predictor. Then when it comes time to make a prediction for a jump table switch statement instruction the branch predictor uses the register value stored in the table is used to predict where the jump table switch statement will branch to.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

90.

Dynamically resizable circular buffers

      
Application Number 13964257
Grant Number 09824003
Status In Force
Filing Date 2013-08-12
First Publication Date 2014-03-13
Grant Date 2017-11-21
Owner MIPS TECH, LLC (USA)
Inventor
  • Sanders, Daniel
  • Jackson, Hugh

Abstract

Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays. The method comprises receiving either a request to add data to a circular buffer or to remove data from a circular buffer. If the request is an addition request and the circular buffer is full, an array from the pool is allocated to the circular buffer. If, however, the request is a removal request and removal of the data creates an empty array, an array is de-allocated from the circular buffer and returned to the pool. Any arrays that are not allocated to a circular buffer may be disabled to conserve power.

IPC Classes  ?

  • G06F 13/14 - Handling requests for interconnection or transfer
  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

91.

Global register protection in a multi-threaded processor

      
Application Number 13780115
Grant Number 08996847
Status In Force
Filing Date 2013-02-28
First Publication Date 2014-03-06
Grant Date 2015-03-31
Owner MIPS TECH, LLC (USA)
Inventor
  • Wang, Guixin
  • Jackson, Hugh
  • Isherwood, Robert Graham

Abstract

Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/46 - Multiprogramming arrangements

92.

Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool

      
Application Number 13491781
Grant Number 10534614
Status In Force
Filing Date 2012-06-08
First Publication Date 2013-12-12
Grant Date 2020-01-14
Owner MIPS Tech, LLC (USA)
Inventor Garbacea, Ilie

Abstract

A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

93.

Apparatus and method for guest and root register sharing in a virtual machine

      
Application Number 13436654
Grant Number 09086906
Status In Force
Filing Date 2012-03-30
First Publication Date 2013-10-03
Grant Date 2015-07-21
Owner MIPS TECH, LLC (USA)
Inventor
  • Patel, Sanjay
  • Rozario, Ranjit Joseph

Abstract

A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

IPC Classes  ?

  • G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines

94.

Restoring a register renaming map

      
Application Number 13563025
Grant Number 09128700
Status In Force
Filing Date 2012-07-31
First Publication Date 2013-07-11
Grant Date 2015-09-08
Owner MIPS TECH, LLC (USA)
Inventor Jackson, Hugh

Abstract

A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer while the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

95.

Processor with kernel mode access to user space virtual addresses

      
Application Number 13683875
Grant Number 09235510
Status In Force
Filing Date 2012-11-21
First Publication Date 2013-05-23
Grant Date 2016-01-12
Owner MIPS TECH, LLC (USA)
Inventor
  • Patel, Sanjay
  • Dearman, Chris
  • Sudhakar, Ranganathan

Abstract

A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F 12/10 - Address translation
  • G06F 12/14 - Protection against unauthorised use of memory

96.

Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

      
Application Number 13138176
Grant Number 09612844
Status In Force
Filing Date 2010-01-18
First Publication Date 2012-05-17
Grant Date 2017-04-04
Owner MIPS TECH, LLC (USA)
Inventor Webber, Andrew

Abstract

A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads (32, 34) with differing hardware resources comprising the steps of receiving a plurality of streams of instructions (38, 44) and determining which hardware threads are able to receive instructions for execution (40, 46), determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions (36) and executing the instruction in dependence on the result of the determination (50).

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

97.

Microprocessor with dual-level address translation

      
Application Number 12891503
Grant Number 08239620
Status In Force
Filing Date 2010-09-27
First Publication Date 2012-03-29
Grant Date 2012-08-07
Owner MIPS TECH, LLC (USA)
Inventor Hakewill, James Robert Howard

Abstract

A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.

IPC Classes  ?

  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

98.

Microprocessor system for virtual machine execution

      
Application Number 12891530
Grant Number 08789042
Status In Force
Filing Date 2010-09-27
First Publication Date 2012-03-29
Grant Date 2014-07-22
Owner MIPS TECH, LLC (USA)
Inventor Hakewill, James Robert Howard

Abstract

A processor includes guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The guest context and the root context are simultaneously active to support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

IPC Classes  ?

  • G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F 7/38 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F 9/00 - Arrangements for program control, e.g. control units
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 15/00 - Digital computers in generalData processing equipment in general
  • G06F 21/00 - Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity

99.

Horizontally-shared cache victims in multiple core processors

      
Application Number 12828056
Grant Number 08725950
Status In Force
Filing Date 2010-06-30
First Publication Date 2011-03-03
Grant Date 2014-05-13
Owner
  • MIPS TECH, LLC (USA)
  • MIPS TECH, LLC (USA)
Inventor Vishin, Sanjay

Abstract

A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems

100.

Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor

      
Application Number 12584759
Grant Number 09189241
Status In Force
Filing Date 2009-09-11
First Publication Date 2010-10-28
Grant Date 2015-11-17
Owner MIPS TECH, LLC (USA)
Inventor Webber, Andrew

Abstract

A method is provided for dynamically determining which instructions from a plurality of available instructions to issue in each clock cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle. The method includes the steps of: determining a highest priority instruction from the plurality of available instructions; determining the compatibility of the highest priority instruction with each of the remaining available instructions; and issuing the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle. The highest priority instruction cannot be a speculative instruction. The effect of this method is that speculative instructions are only ever issued together with at least one non-speculative instruction.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
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