A sensing device includes a transmitter configured to emit a sequence of light pulses toward a target, and a first sequence of time values being indicative of respective times of emitting the light pulses (310); a detector configured to receive optical radiation reflected and to output a second sequence of time values indicative of respective arrival times (320); and a controller. The controller is configured for selecting a part of the second sequence of time values based on comparing a modified first sequence of time values with the second sequence of time values (340), and upon determining that a difference between a total number of the selected part and a total number of the first sequence of time values does not exceed a threshold, using the selected part of the second sequence of time values to calculate a common time of flight (350).
A laser pulse sampling and detecting circuit includes: a laser driver which is driven by a triggering signal for generating laser pulse signal; a photoelectric converter for converting the laser pulse signal into current pulse signal; an amplifier for amplifying and converting the current pulse signal into voltage pulse signal; an ADC which is driven by a sampling clock signal for sampling the voltage pulse signal and performing analog-to-digital conversion on the voltage pulse signal, so as to obtain output signal of the ADC; a detector for detecting the output signal of the ADC, so as to obtain peak power and FWHM of the laser pulse signal; and a clock generator for generating the sampling clock signal. Phase of the sampling clock signal consecutively changes with respect to the triggering signal.
A pulsed laser driver (1) utilizes a high-voltage switch transistor (102) to support a high output voltage for a laser (106), and a low-voltage switch transistor (104) that switches between an ON state and an OFF state to generate a pulsed current that is supplied to the laser (106) to generate an output pulsed laser signal. The pulsed laser driver (1) switches the low-voltage switch transistor (104) between the ON state and the OFF state according to an input pulsed signal such that the output pulsed laser signal is modulated according to the input pulsed signal. The pulsed laser driver (1) also utilizes a feedback control module to control the gate terminal voltage of the high-voltage switch transistor (102) to improve the precision of the output pulsed laser signal.
The disclosure relates to a pulsed laser driver that utilizes a high-voltage switch transistor to support a high output voltage for a laser, and a low-voltage switch transistor that switches between an ON state and an OFF state to generate a pulsed current that is supplied to the laser to generate an output pulsed laser signal. The pulsed laser driver switches the low-voltage switch transistor between the ON state and the OFF state according to an input pulsed signal such that the output pulsed laser signal is modulated according to the input pulsed signal. The pulsed laser driver also utilizes a feedback control module to control the gate terminal voltage of the high-voltage switch transistor to improve the precision of the output pulsed laser signal.
H01S 3/00 - Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
H01S 3/09 - Processes or apparatus for excitation, e.g. pumping
H01S 3/11 - Mode lockingQ-switchingOther giant-pulse techniques, e.g. cavity dumping
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
The present disclosure provides a non-linear receiver, an asymmetric decision feedback equalization circuit and method, including: converting an optical signal emitted by a laser device into an electrical signal; obtaining a compensation amplitude of a current data in the electrical signal by obtaining an actual amplitude of the current data, and compensating the current data based on a logic value of k prior data of the current data and a feedback coefficient corresponding to the prior data; comparing the compensation amplitude of the current data with a decision threshold to determine the logic value of the current data; the feedback coefficient is an absolute value of an influence amount of the prior data on an amplitude of the current data, and k is a positive integer. The present disclosure can overcome the bit error problem of the receiver and reduce jitter of the clock recovered by the clock recovery circuit.
A laser power calibration method includes: receiving a first power fed back by a transmitter end; comparing a difference of the first power against a second power predefined at the transmitter end; and when the difference exceeds a predefined range, controlling an output power of the transmitter end to be a third power, wherein the third power is an average power of the first power and the second power.
The present disclosure provides a pulse generation module, and an optical communication transmitter system and a non-linear equalizing method thereof, the pulse generation module includes: a mode detector that outputs a corresponding effective detection signal after detecting a preset mode, a controller that generates a corresponding selection signal according to a jump mode, and an equalizing pulse generator that generates a corresponding equalizing pulse signal according to the effective detection signal and the selection signal. A jump mode of each piece of data in a data stream is detected, and a corresponding equalizing pulse signal is generated based on the detected jump mode, to compensate for nonlinearity of a laser driving signal. Information about a rising edge and a falling edge is determined by detecting a jump mode of data, a balanced current is provided for a particular purpose, and nonlinearity of a laser is compensated by current output.
H04B 10/588 - Compensation for non-linear transmitter output in external modulation systems
H01S 3/09 - Processes or apparatus for excitation, e.g. pumping
H01S 3/13 - Stabilisation of laser output parameters, e.g. frequency or amplitude
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
8.
Hybrid-mode laser drive circuit and optical emitting system
The present disclosure provides a hybrid-mode laser drive circuit and an optical emitting system. An equalizer circuit is configured to generate, according to a data signal and a clock signal, an equalization signal for compensating a hybrid-mode laser drive circuit; the hybrid-mode laser drive circuit is connected to an output end of the equalizer circuit, and is configured to generate a corresponding drive signal according to an output signal of the equalizer circuit, so as to drive a light emitting diode to generate a corresponding optical signal; a third current source is connected between a power supply voltage and an output end of the hybrid-mode laser drive circuit; an anode of the light emitting diode is connected to the output end of the hybrid-mode laser drive circuit and a cathode of the light emitting diode is connected to a power supply ground.
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
10.
Frequency detector, and clock and data recovery circuit including the frequency detector
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
13.
Non-transitory machine readable medium for clock recovery
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
14.
Apparatus and method for clock recovery based on non-non return to zero (non-NRZ) data signals
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04B 10/25 - Arrangements specific to fibre transmission
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor chip sets; Semiconductor chips; Semiconductor chip sets for use in optical communications; Multiprocessor chips; Integrated circuits, integrated circuit chips, and integrated circuit modules for encoding and decoding digital video; Sensor chips for scientific use; Sensor chips for mobile phone and wireless internet devices
An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.
