A micro-isolator is described. The micro-isolator may include a first isolator element, a second isolator element, and a first dielectric material separating the first isolator element from the second isolator element. A second dielectric material may completely or partly encapsulate the second isolator element, or may be present at outer corners of the second isolator element. The second dielectric material may have a larger bandgap than the first dielectric material, and its configuration may reduce electrostatic charge injection into the first dielectric material. The micro-isolator may be formed using microfabrication techniques.
A micro-isolator is described. The micro-isolator may include a first isolator element, a second isolator element, and a first dielectric material separating the first isolator element from the second isolator element. A second dielectric material may completely or partly encapsulate the second isolator element, or may be present at outer corners of the second isolator element. The second dielectric material may have a larger bandgap than the first dielectric material, and its configuration may reduce electrostatic charge injection into the first dielectric material. The micro-isolator may be formed using microfabrication techniques.
H01G 2/00 - Details of capacitors not covered by a single one of groups
3.
System comprising a package having optically isolated micromachined (MEMS) switches with a conduit to route optical signal to an optical receiver and related methods
Optically isolated micromachined (MEMS) switches and related methods are described. The optically isolated MEMS switches described herein may be used to provide isolation between electronic devices. For example, the optically isolated MEMS switches of the types described herein can enable the use of separate grounds between the receiving electronic device and the control circuitry. Isolation of high-voltage signals and high-voltage power supplies can be achieved by using an optical isolator and a MEMS switch, where the optical isolator controls the state of the MEMS switch. In some embodiments, utilizing optical isolators to provide high voltages, the need for electric high-voltage sources such as high-voltage power supplies and charge pumps may be removed, thus removing the cause of potential damage to the receiving electronic device. In one example, the optical isolator and the MEMS switch may be co-packaged on the same substrate.
H03K 17/94 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the way in which the control signals are generated
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Disclosed herein are systems and techniques for content protection over synchronous data networks. For example, a method of communicating content protected data may include providing link synchronization information over a link of a synchronous bus, and providing content protected data over the link of the synchronous bus. The content protected data may be protected in accordance with the High-Bandwidth Digital Content Protection (HDCP) specification or the Digital Transmission Content Protection (DTCP) specification, for example.
Disclosed herein are systems and methods for performing DC offset correction of a video signal received over an AC-coupled video link. In one aspect, a transmitter is configured to compute, and provide to a receiver, metadata indicative of a statistical characteristic (e.g., an average or a sum of values) for a group of active pixels of a video signal acquired by a camera. The receiver is configured to compute an analogous statistical characteristic on the video signal received over an AC-coupled video link, and to perform DC offset correction by modifying one or more values of the received video signal based on a comparison of the statistical characteristic computed by the receiver and the one computed by the transmitter and indicated by the received metadata.
H04N 7/08 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band
H04N 11/08 - Transmission systems characterised by the manner in which the individual colour picture signal components are combined using sequential signals only
H04N 9/81 - Transformation of the television signal for recording, e.g. modulation, frequency changingInverse transformation for playback the individual colour picture signal components being recorded sequentially only
H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
6.
Transimpedance amplifiers for ultrasonic sensing applications
Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H03F 1/48 - Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
H01L 41/113 - Piezo-electric or electrostrictive elements with mechanical input and electrical output
B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
7.
Amplifier systems for driving a wide range of loads
Amplifier systems for driving a wide range of loads are provided herein. In certain embodiments, an amplifier system includes a voltage output amplifier and a current output amplifier that are electrically coupled in parallel with one another between an input terminal and an output terminal. The amplifier system further includes a control circuit operable to control whether or not the voltage output amplifier and/or current output amplifier drive the output terminal.
Amplifier systems for measuring a wide range of current are provided herein. In certain embodiments, an amplifier system includes a controllable sensing circuit, a first amplifier including an output configured to drive a device under test (DUT) through the controllable sensing circuit, and a second amplifier including an input coupled to the controllable sensing circuit and operable to generate a measurement signal indicating an amount of measured current of the DUT. The amplifier system further includes a control circuit operable to control a configuration or mode of the controllable sensing circuit suitable for a particular type of DUT.
G01R 15/08 - Circuits for altering the measuring range
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
9.
Wake-up control circuit for power-gated integrated circuits
A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.
G06F 1/26 - Power supply means, e.g. regulation thereof
10.
AN APPARATUS AND METHOD FOR REMOVING PERTURBATION SIGNAL FROM A SERIAL DATA STREAM, AND TO MEASURMENT AND/OR PROTECTION APPARATUS INCLUDING SUCH A SIGNAL REMOVING APPARATUS
An apparatus is provided which substantially removes a perturbation signal from a pulse density modulated signal representing a combination of a signal to be measured and a perturbation applied to the signal to be measured. The removal of the perturbation is done by subtracting a correcting signal from the pulse density modulated signal. This approach introduces very little delay as it can be implemented by simple logic gates. It also provided enhanced immunity from the effects of bit errors.
The subject disclosure provides for utilizing pulse width modulation (PWM) signaling to influence a closed loop of a shunt boost controller and reduce an imbalance of a load. The imbalance reduction helps reduce remanence of a current transformer (CT) and thereby prevent saturation of the CT. A shunt boost controller provides the control signal to control flow of current to the load. A feedback network provides a feedback signal to the shunt boost controller based on a direct current (DC) voltage and causes a power switch circuit to turn on when a magnitude of the feedback signal exceeds a threshold magnitude. The PWM generator supplies a PWM signal to cause the control signal to be provided more symmetrical to the power switch circuit and causes the power switch circuit to turn on more frequently with the control signal to reduce the imbalance of the load.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H01F 27/40 - Structural association with built-in electric component, e.g. fuse
H02M 7/06 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
H02M 1/40 - Means for preventing magnetic saturation
There is provided an active-pixel image sensor that uses a method of offsetting and interleaving to increase its resolution. In a basic configuration of the active-pixel image sensor, light from one optical transmitter is diffracted to create one diffraction pattern, and then light from another optical transmitter is diffracted to create another diffraction pattern. Light from further optical transmitters may also be diffracted to create further diffraction patterns sequentially after that. These diffraction patterns are offset from one another and then interleaved using time division multiplexing so as to create a single pixel output that has higher resolution than is feasible with an active-pixel image sensor that only utilizes one optical transmitter per pixel or that does not use diffraction patterns to create a larger field of view.
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
Power isolators with multiple selectable feedback modes are described. The power isolators may transfer a power signal from a primary side to a second side. A feedback signal may be provided from the secondary side to the primary side to control generation of the power signal on the primary side. In this manner, the power signal provided to the secondary side may be maintained within desired levels. The feedback signal may be generated by feedback circuitry configurable to operate in different modes, such that the feedback signal may be of differing types depending on which feedback mode is implemented.
H02M 1/092 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.
Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
Systems and methods for detecting, isolating, and diagnosing machine faults are discussed. An exemplary system includes a network of sensor nodes deployed at machines or machine components to sense information of machine characteristics, and to generate physical or statistical features using the sensed machine characteristics. A cloud-computing device, communicatively coupled to the sensor network, can provide cloud-based services including detecting a machine fault, diagnosing a fault type, or estimating time to machine failure. A user interface associated with a client device can alert a user of the detected fault, such that the user can take preventive actions to minimize machine downtime.
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
ANALONG DEVICES GLOBAL UNLIMITED COMPANY (Bermuda)
Inventor
Esmael, Mohamed Moussa Ramadan
Abstract
Systems, methods, and apparatuses for improving reliability and/or reducing or preventing breakdown of an amplifier, specifically breakdown of a transistor of an amplifier, are disclosed. A protection circuit can be electrically coupled to the amplifier, and can be configured to reduce a voltage swing at the amplifier. The amplifier can include a first transistor, and the protection circuit can include a second transistor electrically coupled to a control terminal of the first transistor of the amplifier. When a power at a control terminal of the second transistor of the protection circuit satisfies a threshold power, the protection circuit can be configured to reduce a power at a power terminal of the first transistor the amplifier. By reducing the voltage at the power terminal of the first transistor the amplifier, the protection circuit can allow the amplifier to operate safely, without breakdown.
A61B 5/00 - Measuring for diagnostic purposes Identification of persons
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
21.
Bias circuit for high efficiency complimentary metal oxide semiconductor (CMOS) power amplifiers
Aspects of this disclosure relate to an adaptive biasing circuit for a power amplifier. The adaptive biasing circuit can include a shunt resistor arrangement and/or a floating gate linearizer arrangement.
Input stages for an analog to digital converter wherein charge for charging parasitic capacitances in the input stage, and particularly in the input switch is sourced from a node which means that it does not have to pass through the input RC filter. This has the effect that the input RC filter can be of lower bandwidth, and/or have a larger resistor value, with the consequent result that there is lower power dissipation in the ADC drive circuitry. In one example this effect is realized by providing a separate input into which charge to charge the parasitic capacitances can be fed from external circuitry. In another example an operational amplifier having high (ideally infinite) input impedance can be used to feed charge to the input switch from the input to the RC filter, or from the node between the resistor and capacitor of the filter, again without unsettling the filter.
Disclosed herein are systems and methods for communicating video signals and control data over a HD, wired, AC-coupled video and control link. In one aspect, an example system includes a scheduler that is configured to allocate time slots for exchange of data between a transmitter and a receiver over such a link. The scheduler is configured to, for each of at least one or more video lines of a video frame of a video signal acquired by a camera, allocate a plurality of time slots for transmitting a plurality of video components of said video line from the transmitter to the receiver, allocate one or more time slots for transmitting transmitter control data from the transmitter to the receiver, and allocate one or more time slots for transmitting receiver control data from the receiver to the transmitter.
G05D 1/02 - Control of position or course in two dimensions
B60R 1/00 - Optical viewing arrangementsReal-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
24.
Reducing motion-related artifacts in optical measurements for vital signs monitoring
Vital sign monitors are plagued by noisy photoplethysmography (PPG) data, making it difficult for the monitors to output consistently accurate readings. Noise in PPG signals is often caused by motion. The present disclosure provides improved techniques for reducing motion-related artifacts in optical/PPG measurements for vital signs monitoring. In general, techniques described herein are based on using measurements of reference sensors that include sensors other than optical sensors used for the optical measurements, e.g., biopotential sensors, bioimpedance sensors, and/or capacitive sensors. In particular, techniques described herein aim to filter PPG signals using substantially only the noise components of signals generated by reference sensors, by attenuating or altogether eliminating components of the signals generated by reference sensors which are indicative of the parameter the reference sensors are designed to measure. Implementing the techniques described herein may lead to more accurate vital sign evaluation using optical/PPG measurements.
Disclosed herein are systems and methods for performing SAG effect compensation on a video signal received over an AC-coupled video link. In one aspect, a method for performing SAF effect compensation includes applying a filter to the received video signal to generate a corrected video signal, where a transfer function of the filter is dependent on a transmission parameter that is based on a plurality of parameters of the AC-coupled link. The method further includes extracting predefined content from the corrected video signal, and adjusting the transmission parameter based on a comparison of the extracted predefined content with certain expected content, so that adjusted transmission parameter can be used for one or more subsequent applications of the filter, thereby realizing an adaptive filter.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04N 7/10 - Adaptations for transmission by electrical cable
H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
H04N 7/083 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the vertical and the horizontal blanking interval
A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
The subject disclosure includes paralleling of monolithic embedded low drop-out (LDO) linear regulator power rails to provide additional load current, while maintaining accurate current sharing and balancing between the paralleled LDOs without additional power consumption for different load current requirements. Lossless current sensing is used to sense the current for each channel. An offset generator compares the voltages for a master channel and one or more slave channels, and generates an offset voltage according to the sensed error. The offset voltage is added between an input reference voltage and an output regulated voltage to cancel the offset of each channel, so the current of each channel is substantially the same. The lossless current sensing can be realized with equivalent series resistance compensation or current limit sensing. The offset generator can be realized with a resistor and current mirror topology or an input pair added to an error amplifier input.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
The present disclosure provides a pulse generator which generates a pulse train by mixing pulses of a first clock having a first frequency, with pulses of a second clock having a second frequency. Over a predefined time period, the combination of pulses results in a pulse train having an effective frequency which is between the first and second frequencies. A multiplexer is used to select which of the first and second clocks should be provided to the output. Depending on the desired target frequency, the multiplexer is controlled to mix differing amounts of pulses from the first and second clocks. A multiplexer is controlled by a control signal, which is generated using combinatorial logic using the first clock as an input. The pulse generator may be used, for example, as a clock for a charge pump.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Techniques for supplying a bias current to a load are provided. In certain examples, a circuit can include a level-shift capacitance, a current source, and a load configured to receive a bias current in a first state of the circuit. The current source and the level-shift capacitance can be coupled in series between the load and a supply voltage in the first state. In some examples, during a second state of the circuit, the level-shift capacitance can receive charge, and can be isolated from one of the load or the current source.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Aspects of this disclosure relate to detecting a header of a packet. A receive signal path can provide a receive signal that includes packets and a guard preamble between successive packets of the packets. A receiver control circuit can trigger a timer that sets a time for detecting a header of a packet in response to detecting an end of a preamble of the packet.
H04L 12/741 - Header address processing for routing, e.g. table lookup
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
RF communication systems that provide combined demodulation and despreading are provided herein. In certain embodiments, an RF communication system generates an in-phase (I) signal and a quadrature-phase (Q) signal based on processing a received spread spectrum signal carrying a sequence of data symbols. The data symbols each have a symbol period and are coded by one or more multi-bit spreading codes. The RF communication system includes a symbol correlator that delays the I signal and the Q signal by an integer number of symbol periods to thereby generate a delayed I signal and a delayed Q signal, respectively. Additionally, the symbol correlator generates a correlation signal based on correlating the delayed I signal to the I signal and correlating the delayed Q signal to the Q signal. The RF communication system processes the correlation signal to recover the sequence of data symbols.
Apparatus and methods for timing offset compensation of frequency synthesizers are provided herein. In certain embodiments, an electronic system includes a frequency synthesizer, such as a fractional-N phase-locked loop (PLL), which generates an output clock signal based on timing of a reference clock signal. Additionally, the electronic system includes an integer PLL configured to compensate for a timing offset, such as a phase offset and/or frequency offset, of the frequency synthesizer based on timing of the output clock signal.
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.
Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
A low-noise, low-power reference voltage circuit can include an operational transconductance amplifier (OTA) with inputs coupled to a temperature-compensated voltage, such as can be provided by source-coupled first and second field-effect transistors (FETs) having different threshold voltages. A capacitive voltage divider can feed back a portion of a reference voltage output by the OTA to the inputs of the OTA to help establish or maintain the temperature-compensated voltage across the inputs of the OTA. A switching network can be used, such as initialize the capacitive voltage divider or other capacitive feedback circuit, such as during power-down cycles, or when resuming powered-on cycles. A switch can interrupt current to the OTA during the power-down cycles to save power. The cycled voltage reference circuit can provide a reference voltage to an ADC reservoir capacitor. Powering down can occur during analog input signal sampling, during successive approximation routine (SAR) conversion, or both.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A charge pump circuit comprises a first charge transfer circuit path coupled including a first boost capacitor coupled to a first clock input, a first charge switch coupled to a circuit input, and a first discharge switch coupled to a circuit output; a second charge transfer circuit path including a second boost capacitor coupled to a second clock input, a second charge switch coupled to the circuit input, and a second discharge switch coupled to the circuit output; a first charge control circuit including a first gate switch coupled to a gate input of the first charge switch, and a first gate-drive capacitor coupled to the gate input of the second charge switch; and a second charge control circuit including a second gate switch coupled to a gate input of the second charge switch, and a second gate-drive capacitor coupled to the gate input of the first charge switch.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
Various examples are directed to a variable speed comparator circuit comprising a first comparator, a second comparator, and a third comparator and a logic circuit. The first comparator may be configured to generate a first comparator output using a first input and a second input. The second comparator may be configured to generate a second comparator output using the first input and the second input. The third comparator may be configured to generate a third comparator output using the first input and the second input. A propagation delay of the second comparator may be less than a propagation delay of the first comparator. Also, a propagation delay of the third comparator may be less than the propagation delay of the second comparator. The second comparator may have an input offset relative to the third comparator. The logic circuit may be configured to determine that the second comparator output and the third comparator output are not equivalent and set a comparator circuit output to the first comparator output.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
39.
Low power half-VDD generation circuit with high driving capability
A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.
H02M 3/16 - Conversion of DC power input into DC power output without intermediate conversion into AC by dynamic converters
G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.
An “all-digital” operational amplifier architecture, that does not have the constraint of maintaining devices in their saturation region, can leverage the high speed achievable by deeply scaled technology to replace traditional linear current referenced continuous-time operational amplifier circuits with CMOS-like dynamic circuits that require no referencing structure, have no static power consumption, and are compatible with ultra-low supply voltages. Techniques are described to replace analog continuous-time linear operational amplifier input and output stages by a discrete-time comparator circuit, e.g., CMOS-style, and a switched capacitor charge pump circuit, respectively.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03M 3/00 - Conversion of analogue values to or from differential modulation
42.
SPARK GAP STRUCTURES FOR DETECTION AND PROTECTION AGAINST ELECTRICAL OVERSTRESS EVENTS
The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.The two conductive structures have facing surfaces that have different shapes;
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
43.
Oversampled continuous-time pipeline ADC with digital signal reconstruction
Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
44.
Biasing of radio frequency switches for fast switching
Apparatus and methods for biasing radio frequency (RF) switches to achieve fast switching are disclosed herein. In certain configurations, a switch bias circuit generates a switch control voltage for turning on or off a switch that handles RF signals. The switch bias circuit provides the switch control voltage to a control input of the switch by way of a resistor. Additionally, the switch bias circuit pulses the switch control voltage when turning on or off the switch to thereby shorten switching time. Thus, the switch can be turned on or off quickly, which allows the switch to be available for use soon after the state of the switch has been changed.
Aspects of the present disclosure relate to decoding the output of a multi-turn magnetic sensor using a successive approximation technique to detect a number of turns of a magnetic target. A decoder circuit can decode a turn count of the multi-turn magnetic sensor by obtaining measurements at nodes that are determined from values of previous measurements.
G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures
G01D 5/16 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
46.
Current measurement using magnetic sensors and contour intervals
Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
A package (23) includes a carrier (42) that comprises a first conductive layer (51) on a first side and a second conductive layer (52) on a second side opposite the first side. The first conductive layer (51) comprises wire bonding pads (55). The package (23) also includes a semiconductor die (21) that is flip chip mounted on the first side of the carrier (42). The carrier (42) may comprise vias (54) from the first side to the second side, wherein the vias (54) receive electrical ground from the second conductive layer (52). The first conductive layer (51) may comprise traces electrically connecting the semiconductor die (21) and the wire bonding pads (55). The semiconductor die (21) may be a high frequency radio frequency (RF) die and the first conductive layer (51) may carry RF signals. The semiconductor die (21) may be a silicon-on-insulator (SOI) die. Copper pillars (24) may be placed between the semiconductor die (21) and the carrier (42). Molding material (27) may be disposed around the semiconductor die (21). The carrier (42) may comprise a laminated substrate, a ceramic substrate, or a semiconductor substrate, the semiconductor substrate comprising electronic components and semiconductor device elements or not including any such components or devices fabricated thereon. The package (23) may be attached to a board, such as a printed circuit board (PCB) (62) comprising a first conductive layer (71) and a second conductive layer (72) separated by dielectric (73), wherein the first conductive layer (71) is on a first side of the PCB (62). The PCB (62) may include a recess (65) on the first side and extending through the first conductive layer (71) and the dielectric (73) to the second conductive layer (72), wherein the carrier (42) is positioned in the recess (65) of the PCB (62), and wherein the second conductive layer (52) of the carrier (42) is electrically connected to the second conductive layer (72) of the PCB (62) in the recess (65) by an epoxy (63) that is both thermally and electrically conductive. The semiconductor die (21) may receive electrical ground from the second conductive layer (72) of the PCB (62) by way of the carrier (42). Pads (71a) on the first conductive layer (71) of the PCB (62) may be connected to corresponding pads (55) on the first conductive layer (51) of the carrier (42) by wires or ribbons (67, 68).
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
48.
CONTACTLESS CURRENT MEASUREMENT USING MAGNETIC SENSORS
Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
The present disclosure relates to a gate driver system suitable for driving the gate voltage of one or more transistors. The gate driver system is configured to operate in a first state when the current conducted by the transistor is relatively low and in a second state when the current conducted by the transistor is relatively high. In the second state, the gate voltage is set such that the source voltage at the transistor establishes a lower voltage across a source-driven load than is the case when operating the first state, thereby reducing the level of power consumption in the load during second state operation.
H03K 17/30 - Modifications for providing a predetermined threshold before switching
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G01R 31/26 - Testing of individual semiconductor devices
H03K 17/06 - Modifications for ensuring a fully conducting state
50.
Optically isolated micromachined (MEMS) switches and related methods comprising a light transmitting adhesive layer between an optical receiver and a light source
Optically isolated micromachined (MEMS) switches and related methods are described. The optically isolated MEMS switches described herein may be used to provide isolation between electronic devices. For example, the optically isolated MEMS switches of the types described herein can enable the use of separate grounds between the receiving electronic device and the control circuitry. Isolation of high-voltage signals and high-voltage power supplies can be achieved by using an optical isolator and a MEMS switch, where the optical isolator controls the state of the MEMS switch. In some embodiments, utilizing optical isolators to provide high voltages, the need for electric high-voltage sources such as high-voltage power supplies and charge pumps may be removed, thus removing the cause of potential damage to the receiving electronic device. In one example, the optical isolator and the MEMS switch may be co-packaged on the same substrate.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H03K 17/94 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the way in which the control signals are generated
A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.
A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/42 - Sequential comparisons in series-connected stages with no change in value of analogue signal
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/80 - Simultaneous conversion using weighted impedances
53.
Method of applying a dither, and analog to digital converter operating in accordance with the method
A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.
H03M 1/34 - Analogue value compared with reference values
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering
54.
Phase-locked loop with filtered quantization noise
This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03C 3/09 - Modifications of modulator for regulating the mean frequency
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.
G05F 3/30 - Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
Techniques are described tocancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/80 - Simultaneous conversion using weighted impedances
A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively "holds" or provides the input signal value at the output for further processing without requiring switched- capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the frontend sampler in a variety of analog-to-digital converters.
A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.
Aspects of this disclosure relate to a receiver for a light detection and ranging system. The receiver includes a transimpedance amplifier that is operable in a linear mode for a range of power of light received by the receiver. The receiver can provide information about amplitude of the light outside of the range of power of the light for which the transimpedance amplifier operates in the linear mode. This information can be useful, for example, in identifying an object from which light received by the receiver was reflected.
H03G 1/00 - Details of arrangements for controlling amplification
G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
A cap for use with devices, such as sensors. The cap includes protrusions on its underside, to restrict the movement of a liquid or a gel placed under cap. The protrusions may take the form of walls or pillars, depending on the application. As such, the cap retains the liquid or gel in a specified position on the device. For example, an electrochemical sensor may require a liquid electrolyte to remain in place over one or more electrodes. The protrusions may not extend far enough to touch the device, but rather leave a small gap. However, because of the surface tension of the liquid, the liquid generally stays within the protrusions.
G01N 27/404 - Cells with anode, cathode and cell electrolyte on the same side of a permeable membrane which separates them from the sample fluid
61.
Method of and apparatus for detecting open circuit conditions at an input to a signal chain and for detecting channel imbalance in a differential signal chain
It is often desirable to distinguish between an open circuit condition and a no signal condition. In both cases an input signal may be absent, but only one of these events represents a failure of the equipment. The present disclosure provides a way to use a difference amplifier to check for open circuit events, without requiring additional circuitry at the input of the amplifier.
Residue generation systems for use in continuous-time and hybrid ADCs are disclosed. An example residue generation system includes at least one stub filter, configured to generate a modified analog input based on an analog input, and a quantizer, configured to generate a digital input to a feedforward DAC based on the modified analog input generated by the filter. The feedforward DAC is configured to generate a feedforward path analog output based on the digital input generated by the quantizer, and the system may further be configured to generate a residue signal based on the feedforward path analog output. Providing one or more stub filters that filter the analog input before it is quantized by the quantizer advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer.
An optical device package is disclosed. The optical device package includes a substrate that passes light at an optical wavelength. The optical device package also includes an optical device assembly that is mounted to the substrate. The optical device assembly comprises an optical device die. The optical device die has a first surface that is mounted to and facing the substrate and a second surface that is opposite the first surface. The optical device package further includes a molding compound that is disposed at least partially over the second surface of the integrated device die.
Techniques to use reservoir capacitors in ADC to supply most of the charge to bit-trial capacitors as bit-trials are performed. An accurate reference voltage source, e.g., a reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC is ready to sample onto the residue amplifier. These techniques can ease the demands on the reference buffer circuit and requirement of external decoupling capacitors, for example.
Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.
Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.
H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
67.
Interleaved boost converter with holdup time extension
A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.
H02M 7/04 - Conversion of AC power input into DC power output without possibility of reversal by static converters
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
G05F 1/70 - Regulating power factorRegulating reactive current or power
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
H02M 3/337 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
68.
Analog-to-digital converters for phase-detection autofocus image sensors
Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
Various examples are directed to a digital predistortion (DPD) circuit comprising a DPD actuator circuit, a DPD feedback frequency-shaping filter, a basis matrix generator circuit, a basis matrix frequency-shaping filter, and a DPD adaption circuit. The DPD actuator circuit may generate a predistorted signal based at least in part on an input signal and a set of frequency-shaped DPD parameters. The DPD feedback frequency-shaping filter may filter a DPD feedback signal to generate a frequency-shaped DPD feedback signal. A passband of the DPD feedback frequency-shaping filter may include substantially all of a bandwidth of the input signal and exclude a distortion term outside the bandwidth of the input signal. The basis matrix generator may generate a basis matrix based at least in part on a power amplifier feedback signal The basis matrix frequency-shaping filter may generate a frequency-shaped basis matrix based at least in part on the basis matrix. The DPD adaption circuit may be configured to generate the set of frequency-shaped DPD parameters based at least in part on the frequency-shaped basis matrix and the frequency-shaped DPD feedback signal.
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.
Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient.
Magnetic sensors may be positioned around an opening for a wire to measure the current flowing through the wire. A non-symmetric positioning of the sensors around the target measurement zone can enable an expanded measurement zone compared to conventional current measurement devices. Further, some sensors may be paired such that a hypothetical line connecting the sensors is tangential to the target measurement zone. Other sensors may be paired such that a hypothetical line between the sensors crosses the target measurement zone. The different pairs of the sensors can enable a reduction in the impact of stray field interference on the measurement of the current flowing through the wire.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
Magnetic sensors may be positioned around an opening for a wire to measure the current flowing through the wire. A non-symmetric positioning of the sensors around the target measurement zone can enable an expanded measurement zone compared to conventional current measurement devices. Further, some sensors may be paired such that a hypothetical line connecting the sensors is tangential to the target measurement zone. Other sensors may be paired such that a hypothetical line between the sensors crosses the target measurement zone. The different pairs of the sensors can enable a reduction in the impact of stray field interference on the measurement of the current flowing through the wire.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a filed effect transistor.
Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.
A gas sensor package is disclosed. The gas sensor package can include a housing defining a first chamber and a second chamber. An electrolyte can be provided in the first chamber. A gas inlet can provide fluid communication between the second chamber and the outside environs. The gas inlet can be configured to permit gas to enter the second chamber from the outside environs. An integrated device die can be mounted to the housing. The integrated device die can comprise a sensing element configured to detect the gas. The integrated device die can have a first side exposed to the first chamber and a second side exposed to the second chamber, with the first side opposite the second side.
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
G01N 27/404 - Cells with anode, cathode and cell electrolyte on the same side of a permeable membrane which separates them from the sample fluid
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
H01L 23/055 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads having a passage through the base
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
The noise power of an amplifier or buffer can increase towards the unity gain cross- over frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.
A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feed forward DAC, based on which the DAC can generate a feed forward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feed forward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
H03M 3/00 - Conversion of analogue values to or from differential modulation
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
Apparatus and methods provide predistortion for a phased array. Radio frequency (RF) sample signals from phased array elements are provided along return paths and are combined by a hardware RF combiner. Phase shifters are adjusted such that the RF sample signals are phase-aligned when combined. Adaptive adjustment of predistortion for the amplifiers of the phased array can be based on a signal derived from the combined RF sample signals.
H01Q 3/28 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the amplitude
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
82.
Method to improve latency in an ethernet PHY device
This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.
In a communication receiver circuit, an amplifier circuit can include an adjustable gain. A signal corresponding to a portion of a transmitted frame can be received, and a gain of the receiver circuit can be adjusted such as automatically, and such adjustment can be referred to as automatic gain control (AGC). An offset correction can be performed to adjust for an error in a received representation of a transmitted carrier, and such offset correction can be referred to as carrier frequency offset (CFO) correction. A portion of the received signal can be dynamically allocated between AGC and CFO correction, such as allocating a longer duration to CFO correction when AGC results in a relatively higher receiver gain, and allocating a shorter duration to CFO correction when AGC results in a relatively lower receiver gain.
Embodiments of the disclosure provide various nanogap sensor designs (e.g., horizontal nanogap sensors (200), vertical nanogap sensors (), arrays of multiple nanogap sensors, various arrangements for making electrical connections to the electrodes of nanogap sensors, etc.), as well as various methods which may be used to fabricate at least some of the proposed sensors. The nanogap sensors (200) proposed herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes (V1, V2) separated by a nanogap (206).
Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.
Aspects of this disclosure relate to transmitting and/or receiving a frequency-shift keying signal including a packet that includes a preamble and a payload. The preamble has a first modulation index that has a smaller magnitude than a second modulation index of the payload. This can enhance frequency correction in a receive device that receives the packet.
Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.
A measurement circuit is arranged to make several measurements, either at different times or in respect of different frequency components of currents measured by current sensors in respective phases of a multiphase supply system. The measurments are then used to correct for discrepencies in the transfer function of the sensors.
G01R 35/04 - Testing or calibrating of apparatus covered by the other groups of this subclass of instruments for measuring time integral of power or current
G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique
G01R 35/02 - Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
Differential sampling circuits may be adversely affected by changes in common mode voltage. Changes in the common mode voltage may alter the on resistance of transistor switches which it turn may mean that small signal changes are not correctly observed against a bigger common mode signal. The present disclosure relates to a way of improving the ability to resolve small differential signal changes by varying the supply or drive voltage to a component to compensate for common mode voltage changes.
G01L 9/02 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers
G01R 17/00 - Measuring arrangements involving comparison with a reference value, e.g. bridge
91.
MANAGING THE DETERMINATION OF A TRANSFER FUNCTION OF A MEASUREMENT SENSOR
The present disclosure provides a system and method for the management of a monitor module in an electrical measurement system to determine an estimate of a transfer function of a first measurement sensor in the measurement system. The management comprises outputting a first control instruction for instructing the monitor module to determine an estimate of the transfer function of the first measurement sensor over a first individual run length of time, obtaining a first monitor result from the monitor module, the monitor result comprising the estimate of the transfer function of the first measurement sensor and generating a report based at least in part on the first monitor result.
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G01R 11/25 - Arrangements for indicating or signalling faults
G01R 35/04 - Testing or calibrating of apparatus covered by the other groups of this subclass of instruments for measuring time integral of power or current
G01R 21/00 - Arrangements for measuring electric power or power factor
G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique
The present disclosure relates to the control of an operation of a monitor module of an electrical measurement system, where the monitor module has a plurality of operating states, including a) monitor at least a first measurement sensor of the utility meter to determine a first monitor result comprising an estimate of a transfer function of the first measurement sensor and a corresponding certainty value indicative of the accuracy of the estimate of the transfer function of the first measurement sensor, wherein the first measurement sensor is for measuring a first electrical property, and b) do not monitor any measurement sensor of the electrical measurement system.
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique
G01R 11/25 - Arrangements for indicating or signalling faults
G01R 35/04 - Testing or calibrating of apparatus covered by the other groups of this subclass of instruments for measuring time integral of power or current
The present disclosure relates to a voltage reference circuit and a method of providing a voltage reference. The voltage reference circuit uses a switched capacitor arrangement to move charge between capacitors during different phases of operation of the circuit to which the voltage reference is being provided. The circuit being provided with a voltage reference may be an analog-to-digital converter (ADC). A reservoir capacitor is used to supply the reference voltage. During a phase in which no voltage reference is required, charge is shared between the capacitors of the switched capacitor arrangement, in order to boost the charge on the reservoir capacitor. After charge sharing, the reservoir capacitor is topped up with an output from a reference buffer. The reservoir capacitor may then be used again in the next conversion phase.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
94.
Blocker tolerance in continuous-time residue generating analog-to-digital converters
Residue generation systems for use in continuous-time and hybrid ADCs are described. An exemplary system includes a filter, e.g. a FIR filter, for generating a filtered analog output based on an analog input, a quantizer for generating a digital input to a feedforward DAC based on the filtered analog output generated by the filter, a feedforward DAC for generating a feedforward path analog output based on the digital input generated by the quantizer, and a subtractor for generating a residue signal based on the feedforward path analog output. Providing a filter that filters the analog input before it is quantized advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer. At least some of the residue generation systems described herein may be implemented with relatively small design and power dissipation overheads.
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
95.
Adaptive use of multiple power supplies in communication systems
Disclosed herein are systems and techniques for adaptive use of multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver to couple to an upstream link of a bus of a communication system; and circuitry to couple to the upstream link of the bus and to a local power supply, wherein the circuitry is to switch from providing the local power supply to power the slave device to providing bus power supplied by the upstream link of the bus to power the slave device.
Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.
An microelectromechanical switch uses electrostatic attraction to draw a beam toward a contact and electromagnetic repulsion to disengage and repel the beam from the contact. The electrostatic attraction is generated by a gate electrode. The electromagnetic repulsion is generated between the beam and a magnetic coil positioned on the same side of the beam as the contact. The magnetic coil produces a magnetic field, which induces a current in the beam that repels the magnetic coil. The gate electrode and the magnetic coil may be co-planar or in different planes. A circuit may also operate a coil-shaped structure act as the gate electrode and the magnetic coil, depending on the configuration.
A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.
A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.
A temperature shock monitor includes a solvent material and a diffusion material. An energy barrier between the solvent material and the diffusion material is selected to be lower than is would conventionally be used in semiconductor devices such that the diffusion material diffuses into the solvent material when exposed to a temperature above a designated temperature threshold. At a later time, electrical parameters of the temperature shock monitor that change based on the amount of diffusion of the diffusion material into the solvent material allows one to determine whether the temperature shock monitor was exposed to a temperature above the temperature threshold.
G01K 3/00 - Thermometers giving results other than momentary value of temperature
G01K 3/04 - Thermometers giving results other than momentary value of temperature giving mean valuesThermometers giving results other than momentary value of temperature giving integrated values in respect of time
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
patents
