Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.
This interface circuit comprises: a transmission/reception circuit (121) that transmits/receives serial data, has multiple internal states, and operates by transitioning between the multiple internal states; a control circuit (122) that outputs time-series internal state signals each indicating a current internal state among the multiple internal states; and a monitor circuit (112) that includes a storage circuit (123) having multiple storage regions for holding the time-series internal state signals, and monitors the internal state of the transmission/reception circuit. The monitor circuit sequentially receives the internal state signals from the control circuit, and writes the received internal state signals to the multiple storage regions in chronological order.
A semiconductor integrated circuit device includes a plurality of standard cells including a first standard cell, arranged in line in a first direction. A first buried power rail supplying a first power supply voltage is laid in a first impurity region supplied with the first power supply voltage, and extends in the first direction. A second buried power rail supplying a second power supply voltage is laid in a second impurity region supplied with the second power supply voltage, and extends in the first direction. The first standard cell includes a third buried power rail laid in the first impurity region and supplied with the second power supply voltage.
A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.
A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Multiple SRAM cells are commonly connected to write-bit lines extending in a Y-direction and a local read-bit line extending in the Y-direction. A local amplifier connected to the local read-bit line outputs a signal received from a selected SRAM cell through the local read-bit line to the global read-bit line. A buried interconnect corresponding to the global read-bit line is formed in a buried interconnect layer. An interconnect corresponding to the local read-bit line is formed in a first interconnect layer.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H01L 23/528 - Layout of the interconnection structure
H10B 10/00 - Static random access memory [SRAM] devices
A neural network generation method includes: decomposing a trained teacher neural network including M layers into N subnetworks to generate a trained teacher neural network including N subnetworks; and generating a trained student neural network by (i) inputting a data set into each of the trained teacher neural network and a student neural network including N layers and (ii) training the student neural network. The generating of the trained student neural network includes: associating N teacher outputs and N student outputs in order of processing from an input layer toward an output layer; and determining weight data for each of the N layers in order of association, the N teacher outputs corresponding one to one to the N subnetworks, the N student outputs corresponding one to one to the N layers of the student neural network.
A semiconductor device includes a first pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in the plan view; a second pad; a third wiring connected to the second pad in the first direction in the plan view; and a fourth wiring connected to the second pad in the second direction in the plan view. The second wiring is located between the third wiring and the first pad in the second direction, and the fourth wiring is located between the first wiring and the second pad in the second direction.
A computer-implemented image processing method of synthesizing a free viewpoint image on a display projection surface from plurality of captured images, the method including: acquiring the plurality of captured images with a plurality of respective cameras; estimating projection surface residual data by machine learning using the plurality of captured images and viewpoint data as inputs, the projection surface residual data representing a difference between a bowl-shaped predefined projection surface and the display projection surface; and acquiring the free viewpoint image by mapping the plurality of captured images onto the display projection surface using information about the predefined projection surface, the projection surface residual data, and the viewpoint data.
A power tap array (CRT) including a power tap (TAP) is provided adjacent to a plurality of cell rows (CR). A cell (C1) comprises: transistors overlapping in a plan view; VDD power supply wiring (21) formed in a BM0 layer; and VSS power supply wiring (11) formed in an M0 layer. The power tap (TAP) comprises: VSS power supply wiring (22) formed in the BM0 layer; VSS power supply wiring (12) formed in the M0 layer; and a connection structure for connecting between the VSS power supply wiring (12, 22). The size of the cell (C1) in an X-direction is larger than the arrangement pitch of VSS power supply wiring (24) formed in a BM1 layer.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Wires (71, 72) corresponding to bit lines BLB, BL are formed in a metal wiring layer. A SRAM cell is provided with: a power supply wiring (11) that is formed in a first back surface wiring layer on the back surface side of a transistor, overlaps with active regions (P1, P2) in plan view, and supplies a power supply voltage VDD; a power supply wiring (13) that is formed in the first back surface wiring layer, overlaps with an active region (N2) in plan view, and supplies a power supply voltage VSS; and a power supply wiring (12) that is formed in the first back surface wiring layer, overlaps with an active region (N1) in plan view, and supplies the power supply voltage VSS.
Wires (11, 12) respectively corresponding to bit lines BLB, BL are formed in a BM0 wiring layer, which is a wiring layer on the back surface of a transistor. Power supply wires (72, 73) for supplying a power supply voltage VSS are formed in a metal wiring layer. An SRAM cell is provided with: an active region (N1) that overlaps the wire (11) in a plan view and is connected to the wire (11); and an active region (N2) that overlaps the wire (12) in a plan view and is connected to the wire (12).
H10B 10/00 - Static random access memory [SRAM] devices
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
In this semiconductor memory device, a plurality of SRAM cells include a first SRAM cell (C1) and a second SRAM cell (C2) disposed side by side with the first SRAM cell (C1) in a first direction. In the first SRAM cell (C1), wires (72, 73) respectively corresponding to bit lines BLB, BL are formed in an M1 wiring layer, which is a metal wiring layer. In the second SRAM cell (C2), wires (212, 213) respectively corresponding to the bit lines BLB, BL are formed in a BM0 wiring layer, which is a wiring layer on the back surface of a transistor.
A 2-port SRAM cell includes load transistors, drive transistors, access transistors, a read drive transistor, and a read access transistor. Buried interconnects corresponding to write-bit lines, respectively are formed in a buried interconnect layer so as to extend in a first direction. Interconnects corresponding to a read-word line and a write-word line, respectively are formed in an interconnect layer above the buried interconnect layer so as to extend in a second direction.
H10B 10/00 - Static random access memory [SRAM] devices
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A first semiconductor chip includes a pad provided on a wiring layer and connected to a power supply for supplying a power supply voltage VSS, a power switch circuit provided between a VDD line and a VDDV line, a buried power supply line formed in a buried power supply wiring layer and connected to the power supply for supplying the power supply voltage VSS, and a via connected to the pad connected to the power supply for supplying the power supply voltage VSS and provided so as to penetrate a substrate and a wiring layer. A second semiconductor chip includes a line connected to the buried power supply line and the via.
H01L 23/528 - Layout of the interconnection structure
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
In an ESD protection circuit using a nanosheet device, a first device structure constituting one of the anode and the cathode is opposed to a second device structure constituting the other in the Y direction, and to a third device structure constituting the other in the X direction. The first device structure includes a pad group of a first conductivity type, and the second and third device structures each include a pad group of a second conductivity type. The length of a range in the X direction in which the pad group of the first device structure is opposed to the pad group of the second device structure in the Y direction is greater than the length of a range in the Y direction in which it is opposed to the pad group of the third device structure in the X direction.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
A display control device includes an insertion unit configured to insert a determination image into a static region of time-series images, the static region being a region in which a pixel value does not change over time, a processing unit configured to execute warping processing on an image into which the determination image is inserted, and a determination unit configured to determine whether or not a result of a CRC computation performed on the static region of the image after the warping processing matches first reference information.
A method of controlling a data processing system including a master, a slave, and a bus provided on a path connecting the master and the slave. The method of controlling the data processing system includes: performing normal processing and performing anomaly avoidance processing to avoid an anomalous state when the slave is anomalous. The performing of the anomaly avoidance processing includes: resetting the slave; and performing a first pseudo response which includes disconnecting communication between the bus and the slave, generating first pseudo response signals corresponding one to one to the plurality of command signals in place of the slave, and transmitting the first pseudo response signals to the master via the bus.
This semiconductor device has: a first power supply line, a second power supply line, and a first control line that are formed in a lower region than an upper surface of a substrate; a first transistor, which is formed in the lower region, is electrically provided between the first power supply line and the second power supply line and has a gate electrically connected to the first control line; a tap cell that has a semiconductor layer formed on the substrate, and a via that is formed on the substrate, is arranged at a position overlapping the semiconductor layer and the first control line when viewed in a plan view, and is connected to the semiconductor layer and the first control line; and a control circuit formed on the substrate and electrically connected to the via. This makes it possible to suppress an increase in circuit area when a power switch circuit is provided on a back surface of the substrate.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
20.
IMAGE DISPLAY CONTROL DEVICE, IMAGE DISPLAY SYSTEM, AND IMAGE DISPLAY CONTROL METHOD
An image display control device with a local dimming function includes: a brightness control unit to control brightness of a plurality of light sources based on first image information representing images to be displayed on a display unit, the light sources being included in a backlight; a pixel compensation unit to generate second image information by correcting pixel values included in the first image information based on the brightness of each light source; a first statistics obtaining unit to obtain first statistical data with respect to the pixel values included in the first image information; a second statistics obtaining unit to obtain second statistical with data respect to pixel values included in the second image information; and an anomaly detection unit to detect an anomaly of the brightness control unit or the pixel compensation unit based on the difference of the second statistical data from the first statistical data.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
This semiconductor device comprises: a first electric power supply line, a second electric power supply line, and a third electric power supply line that are formed below the upper surface of a substrate; a first transistor that is formed above the substrate and is disposed so as to overlap the first electric power supply line in a plan view; a second transistor that is formed above the substrate; and a first via that is formed in the substrate and connects a source of the first transistor and the first electric power supply line. As a result, it is possible to efficiently provide a buffer that includes a transistor in which the source and the drain are directly connected to the wiring below the upper surface of the substrate 9by means of the via.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
A 1-port SRAM cell includes: a load transistor, a load transistor, a drive transistor, a drive transistor, an access transistor having nodes, one of which is connected to a buried interconnect and a line; and an access transistor having nodes, one of which is connected to a buried interconnect and a line. The buried interconnects are formed in the buried interconnect layer so as to extend in the Y-direction, and the lines are formed in the first line layer located above the buried interconnect layer so as to extend in the Y-direction.
A semiconductor memory device includes: a word line extending in the X direction; a bit line extending in the Y direction, formed in a buried interconnect layer; and a ground power line extending in the Y direction. A memory cell includes a transistor provided between the bit line and the ground power line, and connected to the word line at its gate and to the bit line at its drain. The memory cell stores data depending on the presence or absence of connection between the source of the transistor and the ground power line.
H01L 23/528 - Layout of the interconnection structure
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 17/12 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
In an input/output circuit of a semiconductor integrated circuit device according to the present invention, an ESD protection diode (1a), which is connected between a power supply (VSS) and an external input/output terminal (PAD), comprises: an active region (3) that has a first conductivity type and constitutes an anode or a cathode; and an active region (4) that has a second conductivity type and constitutes a cathode or an anode. A power supply wiring line and an input/output wiring line are arranged in a wiring layer on the back surface side of the active regions (3, 4). The power supply wiring line overlaps the active region (3) in a plan view, and is connected to the active region (3) by way of a via. The input/output wiring line overlaps the active region (4) in a plan view, and is connected to the active region (4) by way of a via.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
This level shifting circuit comprises: first to sixth P-type transistors; first and second N-type transistors; and first and second resistors. The first P-type transistor and the first N-type transistor are provided between an input node and an output node. The second P-type transistor is provided between a third power supply and the output node. The third P-type transistor is provided between a first power supply and the output node. The first resistor is provided between a third node and the output node. The fourth P-type transistor and the second N-type transistor are provided between an inverting input node and an inverting output node. The fifth P-type transistor is provided between the third power supply and the inverting output node. The sixth P-type transistor is provided between the first power supply and the inverting output node. The second resistor is provided between a sixth node and the inverting output node.
An image processing apparatus performs a process including acquiring first image data, calculating a white balance value used for an automatic white balance adjustment according to the first image data, performing an automatic white balance adjustment on the first image data according to the white balance value to generate image data after a first correction, calculating a first luminance in the image data after the first correction by adding a color difference component to a luminance, and detecting a first region including a pixel having the first luminance higher than a first threshold value, calculating a correction degree of color information of a pixel included in the first region in the image data after the first correction, according to the first luminance, and correcting the color information of the pixel included in the first region in the image data after the first correction, according to the correction degree.
According to one embodiment, an image processing device includes an action plan formulation module and a projection shape determination module. The action plan formulation module generates, based on action plan information of a moving body, first information including planned self-position information of the moving body and position information of a peripheral three-dimensional object based on the planned self-position information. The projection shape determination module determines, based on the first information, a shape of a projection surface on which a first image acquired by an imaging device mounted on the moving body is projected to generate a bird's-eye view image.
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads 22c, 22d and a gate interconnect 36c, and VSS is supplied to a pair of pads 27c, 27d and a gate interconnect 31c. Capacitances are produced between nanosheets 21c and the gate interconnect 31c and between nanosheets 26c and the gate interconnect 36c. The faces of the nanosheets 21c closer to the nanosheets 26c are exposed from the gate interconnect 31c, and the faces of the nanosheets 26c closer to the nanosheets 21c are exposed from the gate interconnect 36c.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
In a semiconductor integrated circuit device using buried power lines, a standard cell includes: a first buried power line extending in the X direction and supplying a first power supply voltage; a second buried power line extending in the X direction and supplying a second power supply voltage; and a first transistor connected to the first power line. The first buried power line is spaced from the first transistor in planar view and located closer to the center of the standard cell than the first transistor in the Y direction.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
32.
REFERENCE VOLTAGE GENERATOR CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
A reference voltage generator circuit includes: a resistor circuit electrically connected between a first node and a second node and between the first node and a third node, the resistor circuit including a variable resistor whose resistance value varies according to a first control signal; a differential amplifier circuit in which one of a differential input pair is electrically connected to the second node and the other of the differential input pair is electrically connected to the third node, the differential amplifier circuit generating a reference voltage at an output node; a current source circuit electrically connected between the second node and a fourth node and between the third node and the fourth node; and an adjuster circuit configured to be electrically connected to the output node, the adjuster circuit configured to generate the first control signal by comparing at least two target voltages with the reference voltage.
42 - Scientific, technological and industrial services, research and design
Goods & Services
Design of semiconductors; advisory and consultancy services relating to design of semiconductor; Design of semiconductor chips; advisory and consultancy services relating to design of semiconductor chips; Design of electronic circuits, semiconductor elements, integrated circuits and large scale integrated circuits; advisory and consultancy services relating to design of electronic circuits, semiconductor elements, integrated circuits and large scale integrated circuits; Software design and development; testing or research on design of electronic circuits, semiconductor elements, integrated circuits and large scale integrated circuits; testing, inspection and research of semiconductor chips; Providing information in the field of design of semiconductors; rental of computers; providing computer programs for designing, controlling and using integrated circuits on data networks; designing of machines and parts therefor, apparatus and parts therefor, instruments and parts therefor, and systems composed of such machines, apparatus and instruments, all in the field of semiconductors; designing of machines and parts therefor, apparatus and parts therefor, instruments and parts therefor, and systems composed of such machines, apparatus and instruments, all for the purpose of creating semiconductor chips; computer programming of computer programs
34.
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE STRUCTURE
A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A memory circuit includes: a plurality of memory parts, each of which includes a plurality of first memory cells and a second memory cell that is accessed when one of the first memory cells is defective; a plurality of first memory control parts, each of which is configured to control access to a corresponding one of the plurality of memory parts based on a first access request addressing the corresponding memory part, during a first mode; and a second memory control part shared by the plurality of memory parts, and configured to control access to the plurality of memory parts based on a second access request during a second mode.
42 - Scientific, technological and industrial services, research and design
Goods & Services
Design of semiconductors; advisory and consultancy services relating to design of semiconductor; Design of semiconductor chips; advisory and consultancy services relating to design of semiconductor chips; Design of electronic circuits, semi-conductor elements, integrated circuits and large scale integrated circuits; advisory and consultancy services relating to design of electronic circuits, semi-conductor elements, integrated circuits and large scale integrated circuits; Software design and development; testing and research on design of electronic circuits, semi-conductor elements, integrated circuits and large scale integrated circuits; testing, inspection and research of semiconductor chips; Providing information in the field of design of semiconductor; rental of computers; providing computer programs on data networks; designing of machines, apparatus, instruments [including their parts] and systems composed of such machines, apparatus and instruments; programming of computer programs.
First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact has an overlap with the first power line in the Y direction and is at a position different from the positions of the first and second contacts in the X direction, in planar view.
H01L 23/528 - Layout of the interconnection structure
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
This semiconductor device comprises: first, second, and third power supply lines which are formed below a substrate having vias formed therein and which extend in a first direction; and a power supply switch circuit having first and second transistors formed above the substrate. The first transistor is provided between the first power supply line and the second power supply line, and a source of the first transistor is connected to a via connected to the first power supply line. The second transistor is disposed at a position overlapping with the second power supply line, and a source of the second transistor is connected to a source of the first transistor via a wiring formed above the substrate. Thus, in the power supply switch circuit, a source of a transistor which does not overlap with a power supply line below the semiconductor substrate in plan view can be connected to the power supply line below the semiconductor substrate.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
This semiconductor device comprises: first to fourth power supply lines that are formed below a substrate having vias formed therein and extend in a first direction; and a power supply switch circuit formed above the substrate and having a first transistor. The power switch circuit overlaps with the second power line in a plan view and is spaced apart from the fourth power line. The first transistor is disposed at a position overlapping the first power line in a plan view, and has a source connected to a via connected to the first power line. The second and fourth power lines are connected through wiring extending in a second direction. Therefore, the fourth power line disposed spaced apart from the power switch circuit can be connected to the power switch circuit formed at a position overlapping the first power line in a plan view.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
In this semiconductor integrated circuit device, an output transistor unit (30N) provided with a transistor (N1) connected between a VSS and an output terminal (PAD) is provided with an active region (31) having a nanosheet (32) as a channel. Power supply wiring (25) and output wiring (26) are disposed on a wiring layer on the reverse-surface side of the transistor (N1) so as to overlap with the active region (31) in plan view. The power supply wiring (25) is connected to the lower surface of a portion serving as the source of the active region (31) via a via, and the output wiring (26) is connected to the lower surface of a portion serving as the drain of the active region (31) via a via.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.
H10B 10/00 - Static random access memory [SRAM] devices
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A semiconductor integrated circuit design assistance method according to the present invention comprises: a conversion step for converting a hardware structure statement into a graph object; an inference step for inputting the graph object to a neural network that is trained via a GAT method and inferring inference physical metrics of a semiconductor integrated circuit; and an extraction step for extracting, on the basis of the inference physical metrics, an attention part of the hardware structure statement, wherein the graph object includes a node and an edge, the node includes a first node that includes description position information indicating the position of a corresponding description in the hardware structure statement, the neural network includes, as a weight, an attention coefficient indicating a degree of influence of the edge on the inference physical metrics, and in the extraction step, a first edge is identified on the basis of the attention coefficient and a part of the hardware structure statement is extracted as the attention part on the basis of the description position information of a first node corresponding to the first edge.
In an output circuit of a semiconductor integrated circuit device, an output transistor unit (11) provided with a transistor (N1) connected between VSS and an output terminal (OUT) is provided with active regions (31, 51) that overlap in plan view. Power supply wiring (21) and output wiring (23) are disposed on a wiring layer on the rear-surface side so as to overlap the active regions (31, 51) in plan view. The power supply wiring (21) is connected to the lower surface of a portion serving as the source of the active region (31) via a via, and the output wiring (23) is connected to the lower surface of a portion serving as the drain of the active region (31) via a via.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact is located between the first and second power lines in the Y direction, and at a position different from the positions of the first and second contacts in the X direction, in planar view.
Where a first bird's-eye-view image is generated by merging images obtained from multiple image capturing devices in a moving body together and an overlapping image is generated from accumulated images and overlaps the moving body, a second bird's-eye-view is generated by merging the first bird's-eye-view image and the overlapping image together. In the boundary portion formed between the first bird's-eye-view image and the overlapping image, a coefficient calculation part calculates adjustment coefficients for adjusting the property of the overlapping image based on property information of the first bird's-eye-view image and the accumulated images. An adjustment part adjusts the property of the overlapping image to be merged by the merging part based on the adjustment coefficients. By this means, it is possible to reduce the possibility that, when the first bird's-eye-view image and the overlapping image not included in the first bird's-eye-view image are merged together, the resulting image looks unnatural.
A memory access method includes: data storage instructing of issuing a data storage instruction instructing that, in accordance with a first logical address, one item of data be stored into a first memory or a second memory; and first storage path selecting of performing, in response to the data storage instruction, first selecting of selecting whether to execute first storing or second storing based on the first logical address included in the data storage instruction. In the first storage path selecting, the first selecting is performed based on a first interleave rule or a second interleave rule. The first selecting is performed based on the first interleave rule in response to one or more data storage instructions, and the first selecting is performed based on the second interleave rule in response to subsequent one or more data storage instructions.
A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 23/528 - Layout of the interconnection structure
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
According to one embodiment, an information processing device includes: a first determination module that determines first information concerning deformation of a projection surface on which a peripheral image of a moving body is projected; and a deformation module that deforms the projection surface based on the first information. The first determination module includes an information retaining module that accumulates second information in the past used for determining the first information, and determines the first information based on the second information in the past at an operation start time of the moving body.
A semiconductor memory device (MD) comprises a memory cell (11), and a write/read circuit (3). The memory cell (11) comprises: P-type drive transistors (TPM0, TPM1); N-type load transistors (TNM0, TNM1); and P-type access transistors (TPM2, TPM3) connected to a bit line pair (BL, BLB). A sense amplifier circuit (32) comprises P-type transistors (TP0, TP1, TP2), and N-type transistors (TN4, TN5). The semiconductor memory device (MD) further comprises: a first switch circuit (2) having a first switch element and a second switch element; and a second switch circuit (4) having a third switch element.
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
An ESD protection circuit includes: a protective element placed between VDD and VSS; an RC circuit; and an inverter connected to a node of the RC circuit at its input and to a node of the protective element at its output. The inverter includes a PMOS connected to VDD at its source and an NMOS connected to VSS at its source. The PMOS and the NMOS are connected in common to the node of the RC circuit at their gates and to the node of the protective element at their drains. The gate length of the PMOS is smaller than the gate length of the NMOS.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A current mirror circuit includes: a plurality of first transistors connected to a first power supply at their sources and to an input terminal at their gates and drains; and a second transistor connected to the first power supply at its source, to the input terminal at its gate, and to an output terminal at its drain. A switch circuit is provided between at least one of the first transistors and the input terminal. The switch circuit includes third and fourth transistors connected in series between the first transistor and the input terminal, an inverter circuit, and a fifth transistor connected between a middle node of the third and fourth transistors and an 10 output terminal of the inverter circuit. A switch control signal is given to the gates of the third to fifth transistors and to the input of the inverter circuit.
This semiconductor memory device (MD) includes memory cells (11) and a write circuit (2). The memory cell includes P-type drive transistors (TPM0, TPM1), N-type load transistors (TNM0, TNM1), and P-type access transistors (TPM2, TPM3) connected to a bit line pair (BL, BLB). The write circuit (2) includes a column selection circuit (5) having P-type transistors (TP0, TP1), and a pre-discharge circuit (4) having N-type transistors (TN0, TN1).
In a standard cell of a semiconductor integrated circuit device, a metal interconnect corresponding to an input node is connected to the gates of first and second transistors, and a metal interconnect corresponding to an output node is connected to the drains of third and fourth transistors. A metal interconnect corresponding to an intermediate node is connected to a gate interconnect corresponding to the gates of the third and fourth transistors through a gate contact. The gate contact is placed at a position overlapping the third transistor in planar view.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A semiconductor integrated circuit device (1) comprises a driver circuit (6) connected to a memory cell array (2) via a word line (WL), a clamp element (7) provided between the word line (WL) and a ground potential (VSS), and a control circuit (8) having a first circuit (81) that turns the clamp element (7) on or off and a second circuit (82) connected to an input of the first circuit (81). A first power source node (VDD) that supplies a first power source (VDD) is connected to the first circuit (81), and a second power source node (IVDD) connected to the first power source node (VDD) is connected via a switching element (4) to the driver circuit (6) and the second circuit (82).
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
This semiconductor storage device (MD) comprises memory cells (11) and a sense amplifier circuit (32). The memory cells each comprise: P-type drive transistors (TPM0, TPM1); N-type load transistors (TNM0, TNM1); and P-type access transistors (TPM2, TPM3) connected to a bit line pair (BL, BLB). The sense amplifier circuit (32) comprises P-type transistors (TP0, TP1, TP2) and N-type transistors (TN4, TN5).
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
A memory circuit includes memory groups each of which includes memory cells, and is configured to execute a write operation or a read operation in response to a request signal; memory group controllers each of which is provided for a corresponding one of the memory groups; and a first memory controller configured to output a request signal received from an outside to an adjacent memory group controller, wherein, in a case where an address signal included in the received request signal indicates the corresponding one of the memory groups, said each of the memory group controllers outputs the request signal to the corresponding one of the memory groups, and in a case where the address signal indicates a memory group other than the corresponding one of the memory groups, outputs the request signal to a memory group controller at a succeeding stage.
In a semiconductor integrated circuit device, a first semiconductor chip includes: a buried power rail that supplies first power; and a power line that is provided in a layer above the buried power rail and supplies second power. The buried power rail receives supply of the first power from the back face of the first semiconductor chip via a first through electrode, and the power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode. The cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
58.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT
According to one embodiment, an information processing device includes a buffer and a VSLAM processor. The buffer buffers image data of surroundings of a moving body obtained by an imaging unit of the moving body, and transmits extracted image data extracted based on extracted image determination information from among the buffered image data. The VSLAM processor executes a VSLAM process by using the extracted image data.
G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
G06V 10/40 - Extraction of image or video features
G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads
In this semiconductor integrated circuit device, a standard cell (C1) comprises an active area (2P) forming a channel, a source, and a drain of a transistor, and a power supply wiring (11) extending in the X direction. The power supply wiring (11) is formed on the back side of the transistor, and overlaps with the active area (2P) in a plan view. A power supply wiring (71) extending in the Y direction is formed in a wiring layer that is lower than the power supply wiring (11). The power supply wiring (71) is connected to the power supply wiring (11) through a via (81), and overlaps with the active area (2P) in a plan view.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
The present invention provides a layout structure of a standard cell that straddles standard cell rows of differing heights. A double-height cell (C3) is formed across cell rows (CR1, CR2). The height of the cell row (CR2) is greater than the height of the cell row (CR1). The double-height cell (C3) is provided with a first logic circuit that receives an input A and that outputs a signal to an internal node, and a second logic circuit that receives a signal of the internal node and that outputs an output Y. A transistor constituting the first logic circuit is formed in a region of the cell row (CR1). A transistor constituting the second logic circuit is formed in a region of the cell row (CR2).
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
A semiconductor device includes: a substrate; a circuit region provided on the substrate; a first power supply line and a second power supply line, positioned in the circuit region; a first fin and a second fin, each extending in a first direction in the circuit region, in plan view, and protruding from the substrate; a first power supply switching circuit, positioned in the circuit region and including a first transistor formed with the first fin, the first circuit electrically connecting the first and second power supply lines, and the first fin extending in the first power supply switching circuit without cutting; and a second power supply switching circuit, positioned in the circuit region and including a second transistor formed with the second fin, the second circuit electrically connecting the first and second power supply lines, and including a fin-cut part in which the second fin is cut.
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
In this semiconductor integrated circuit device, a plurality of cell rows each including standard cells disposed side by side in an X direction are arranged in a circuit block. The plurality of cell rows include a cell row (CR1) of height H1 and a cell row (CR2) of height H2 (H1
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
In this semiconductor integrated circuit device, a plurality of cell rows that include standard cells arrayed in the X-direction are arranged in a circuit block. The plurality of cell rows include a cell row (CR1) having a height H1, and a cell row (CR2) having a height H2 (H1
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
In this semiconductor integrated circuit device, a terminal cell (C11) is disposed at one end of a cell row. A cell (C1) with a logic function comprises an active region (2P) which includes a nanosheet (21) extending in the X-direction, and a power supply wire (11) formed on the back side of a transistor and extending in the X-direction. The terminal cell (C11) comprises an active region (2P1) which includes a nanosheet (121) extending in the X-direction, and a power supply wire (111) extending in the X-direction. The nanosheet (121) and the nanosheet (21) have the same width and position in the Y-direction. The power supply wire (111) and the power supply wire (11) have the same width and position in the Y-direction.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
65.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
In one aspect, an information processing device (10) comprises a VSLAM processing unit (24) as a map information generation unit and an own position updating unit (301) as an own position generation unit. The VSLAM processing unit (24) selectively executes: generation processing in a first mode of generating map information including information relating to the position of an object in a periphery of a moving body at a first frequency and generating first own position information indicating the own position of the moving body; and generation processing in a second mode of generating the map information at a second frequency lower than the first frequency. In the generation processing in the second mode by the map information generation unit, the own position updating unit (301) uses the first own position information and state information relating to the moving body to generate second own position information, which is information relating to the position of the moving body in the map information.
A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate; a third power supply line provided on a second surface of the substrate, and connected to the first power supply line through a via; a fourth power supply line; a first area including the second power supply line, the first ground line, the third power supply line; a second area including the fourth power supply line and the second ground line; a third area positioned between the first area and the second area in plan view; and a power switch circuit including a switch transistor connected between the first power supply line and the second power supply line.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
67.
SIGNAL PROCESSING METHOD, SIGNAL PROCESSING DEVICE, GESTURE RECOGNITION SYSTEM, AND SIGNAL PROCESSING PROGRAM
A signal processing method is executed by a signal processing device connected to a radio device that transmits radio waves in given periods and receives reflection waves, to process signals of the reflection waves. The signal processing method includes: obtaining positional information on a moving object at respective times based on the signals of the reflection waves; identifying a coordinate that is a coordinate in an axis in a transmission direction of the radio waves, and satisfies an end condition of a gesture from among the obtained positional information at the respective times; and extracting a group of consecutive coordinates including the identified coordinate as an end point.
An output circuit outputs an output signal having an amplitude VCCH responsive to an input signal having an amplitude VCCL. The output circuit includes: first and second p-type transistors connected in series between VCCH and an output terminal; a first n-type transistor grounded at its source and receiving a first signal at its gate; a third p-type transistor connected to VCCH at its source, connected to the gate of the first p-type transistor at its drain, and receiving a second signal at its gate; and a first diode connected between the drains of the first n-type transistor and the third p-type transistor.
An AD converter device includes: a plurality of AD converter circuit units which performs analog-to-digital conversion in a time-interleaved manner; and a multiplexer circuit which generates a digital signal from output signals of the AD converter circuit units. The multiplexer circuit includes logic circuits and intermediate connection wirings placed to be distributed in the AD converter circuit units, the logic circuits are connected in a tournament configuration. In each of the AD converter circuit units, an output circuit and a first element circuit part including the logic circuit are placed along a first outer periphery and the intermediate connection wirings are placed to cross in a first direction. The AD converter circuit units are placed along the first direction with two adjacent ones of the AD converter circuit units set as a pair and with the output circuits and the first element circuit parts facing each other for each pair.
A semiconductor integrated circuit device includes a ring oscillator having a plurality of stages of delay circuits. In each of the delay circuits, when the signal at the input terminal makes a first transition, the signal at the output terminal makes a transition by the operation of a first transistor that corresponds to a transistor in an SRAM cell. When the signal at the input terminal makes a second transition, the first transistor is electrically isolated from the output terminal, and the signal at the output terminal makes a transition by the operation of a second transistor.
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H10B 10/00 - Static random access memory [SRAM] devices
A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/528 - Layout of the interconnection structure
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
In a semiconductor integrated circuit device, a plurality of standard cells arranged in an X direction include a first standard cell having a logical function and including a transistor having a channel portion extending in the X direction, and a second standard cell including a signal line placed to extend in the X direction. The signal line is formed in a buried interconnect layer, and has an overlap with the channel portion at a position in a Y direction.
A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate, and third and fourth power supply lines provided on a second surface of the substrate. The second power supply line and the third power supply line are connected through vias provided in the substrate. The semiconductor device includes first and second areas arranged to have a third area sandwiched in-between, and a power switch circuit including switch transistors connected between the third and fourth power supply lines.
A semiconductor device includes a peripheral circuit area, a bit cell area, and a separating area positioned between the peripheral circuit area and the bit cell. A first power switch circuit for the peripheral circuit area is connected to a first power supply line, and a second power supply line and a first ground line provided on the substrate; and connects the first power supply line and the second power supply line. The second power switch circuit for the bit cell area is connected to a third power supply line, a fourth power supply line, and a second ground line provided on the substrate; and connects the third power supply line and the fourth power supply line.
H10B 10/00 - Static random access memory [SRAM] devices
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.
An IO cell includes an output circuit having an ESD protection diode, a protective resistance, and an output transistor. The protective resistance is constituted by a plurality of resistor elements formed in a first interconnect layer that is formed in an interconnect process (back end of line (BEOL)). The resistor elements are connected to interconnects formed in a second interconnect layer through vias. In the second interconnect layer, first power supply lines supplying first power are formed above the ESD protection diode. The first power supply lines have overlaps at positions in the X direction with the resistor elements.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
In this semiconductor integrated circuit device, a standard cell comprises an active region (2P) in which a channel, a source, and a drain of a transistor are configured, and a power supply wire (11) formed on the backside of the transistor. A region (2Ps) in the active region (2P) is connected to the power supply wire (11) through a via (61). A nano sheet (22a) continuous with the active region (2P) is formed in a cell boundary. A gate wire (32a), which is orthogonal to the nano sheet (22a) in plan view, is electrically connected to the region (2Ps).
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device includes a substrate; and a plurality of semiconductor elements each including a first terminal and a second terminal connected to the substrate, and an internal wiring connecting the first terminal and the second terminal to each other. A wiring path is provided to sequentially connect the plurality of semiconductor elements, by connecting the first terminal of each of the plurality of semiconductor elements to the second terminal of another one of the plurality of semiconductor elements via a substrate wiring provided in the substrate. One of the plurality of semiconductor elements includes a determination circuit provided on a path of the internal wiring. The determination circuit is configured to transmit a determination signal to the first terminal, and determine an abnormality of the wiring path based on the determination signal received by the second terminal via the wiring path.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
80.
IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND RECORDING MEDIUM
An image processing device includes a memory and a processor configured to calculate a reference black level and a reference illumination light component based on pixel values of peripheral pixels located around a target pixel for image processing using image data acquired by an imaging device, correct a black level of the target pixels based on the reference black level calculated by the processor, and perform a tone correction of the target pixels with the black level corrected based on the reference illumination light component calculated by the processor. Accordingly, even when a large gain is applied to a dark portion of an image in a local tone correction, it is possible to generate an image with high visibility in which an occurrence of raised black levels is suppressed.
In the present invention, a standard cell is formed to straddle a power supply wiring (12) between power supply wirings (11A, 11B). The gap between the power supply wirings (11A, 12) is greater than the gap between the power supply wirings (11B, 12). The standard cell comprises a first logic circuit that receives an input A, and outputs a signal to an internal node, and a second logic circuit that receives the signal of the internal node, and outputs an output Y. Transistors that constitute the first logic circuit are formed in a region between the power supply wirings (11B, 12), and the transistors that constitute the second logic circuit are formed in a region between the power supply wirings (11A, 12).
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
An image processing apparatus according to one aspect includes a hardware processor connected to a memory. The hardware processor performs a process including: acquiring a plurality of captured images whose capturing areas overlap with one another; determining whether an object is included in an overlap portion of adjacent ones of the plurality of captured images in a projected image, the projected image being obtained by projecting the plurality of captured images onto a reference projection plane, the reference projection plane being an image projection plane virtually disposed in a virtual space corresponding to a real space; and performing an adjustment process on an overlap area of the reference projection plane, the overlap area including the object on the reference projection plane and corresponding to the overlap portion including the object.
A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
According to the present invention, a capacitor cell includes an active region (2P) and a power supply wiring (11) that supplies VDD. The active region (2P) includes nanosheets (21b-21e) extending in the X direction as channels of transistors (P2-P5). The power supply wiring (11) extends in the X direction on the back side of the transistors (P2 to P5) and overlaps the active region (2P) in a plan view. The sources/drains of the transistors (P2 to P5) in the active region (2P) are connected to the power supply wiring (11) via vias (61). VSS is applied to the gate wirings (31b to 31e) of the transistors (P2 to P5).
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
An information processing device includes a VSLAM processing unit as an acquisition unit, a difference calculation unit and an offset processing unit as alignment processing units, and an integration unit as an integration processing unit. The VSLAM processing unit acquires first point cloud information based on first image data obtained from a first image capturing unit provided at a first position of a moving body, and acquires second point cloud information based on second image data obtained from a second image capturing unit provided at a second position different from the first position of the moving body. The difference calculation unit and offset processing unit perform alignment processing on the first and second point cloud information. The integration unit generates integrated point cloud information by using the first point cloud information and the second point cloud information on both of which the alignment processing has been performed.
A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
88.
COMPARISON CIRCUIT, ANALOG-TO-DIGITAL CONVERTER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
In an AD converter circuit, a comparison circuit includes: a differential comparison circuit configured to perform comparison determination of differential input signals based on an internal clock signal and generate first differential output signals indicating a determination result; a determination assist circuit configured to receive the first differential output signals and generate second differential output signals; a latch circuit configured to hold the second differential output signals and generate third differential output signals; and a clock generation circuit configured to generate the internal clock signal based on the third differential output signals. The determination assist circuit varies a value of the first differential output signals and generate the second differential output signals when a designed time has elapsed with values of the first differential output signals being unvaried from a reset value since the start of an operation of the comparison determination in the differential comparison circuit.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.
G11C 17/12 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
In one aspect, an image processing apparatus includes a determination unit and a deformation unit. The determination unit executes first distance stabilization processing of converting a measurement distance between a three-dimensional object around a moving object and the moving object into a first distance or a second distance smaller than the first distance as a stabilization distance based on the magnitude relation between the measurement distance and the first threshold. The deformation unit deforms a projection surface of a peripheral image of the moving object based on the stabilization distance.
In a semiconductor integrated circuit device, a first power line extends in an X direction in an IO region and is formed in a first interconnect layer. A second power line extends in the X direction in a core region. A third power line extends in a Y direction, is formed in a second interconnect layer located below the first interconnect layer, and is connected to the first and second power lines. The third power line overlaps an external connection pad in planar view and is placed between adjacent interconnects in the X direction.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/528 - Layout of the interconnection structure
93.
IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING PROGRAM
An image processing device is configured to generate a three-dimensional bird's eye view image by projecting captured images acquired from a plurality of imaging devices onto a three-dimensional projection surface, and includes: an acquiring part configured to acquire position information of a first area, on which an object is to be placed, in a three-dimensional space; a conversion part configured to convert the position information of the first area into position information in accordance with the three-dimensional projection surface; and an output part configured to output the three-dimensional bird's eye view image, on which the object is to be placed on a second area in the three-dimensional space, the second area being specified by the converted position information. By this means, when the three-dimensional bird's eye view image is generated from multiple images, it is possible to display the object naturally in the three-dimensional bird's eye view image.
G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads
H04N 5/74 - Projection arrangements for image reproduction, e.g. using eidophor
94.
DRIVER CIRCUIT, TRANSMITTER, AND COMMUNICATION SYSTEM
A first driver operates with a first power supply and outputs a signal in response to a first input signal. A regulator receives a second power supply lower in voltage than the first power supply and provides a third power supply lower in voltage than the second power supply. A second driver operates with the third power supply and outputs a signal in response to a second input signal. The output of the first driver and the output of the second driver are connected in common to an output terminal.
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
H04B 1/50 - Circuits using different frequencies for the two directions of communication
95.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
An information processing device (10) comprises, in one aspect, a map information generation unit (22). With regard to map information (23B) including first surrounding position information, which is information on the position of an object positioned in the surroundings of a moving body (2), the map information generation unit (22) initializes a range pertaining to detection by a sensor mounted on the moving body (2) and adds second surrounding position information acquired from the sensor to the range.
A detection circuit includes: a differential input circuit configured to receive differential input voltages and generate first differential detection currents corresponding to the differential input voltages; a detection current generation circuit configured to form a current mirror circuit with the differential input circuit and generate second differential detection currents corresponding to the first differential detection currents; a detection voltage generation circuit configured to receive the second differential detection currents and generate a detection voltage having a voltage corresponding to the second differential detection currents; and a comparator circuit configured to compare the detection voltage and a reference voltage and output a signal indicating whether or not the differential input voltages are in a voltage state representing a given idle mode.
A sample and hold circuit includes: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.
In an output circuit (11) included in IO cells (10), an M1 wiring line (32a) has been disposed between transistor arrays (24a, 24b) included in output transistors (P1), the M1 wiring line (32a) being connected to the gates of the transistors. M2 wiring lines (41) connected to the drains of the transistors have been provided to the transistor arrays (24a, 24b). The M1 wiring line (32a), in a plan view, is located between the M2 wiring lines (41) separated from each other. That is, in the plan view, the M2 wiring lines (41) connected to the drains of the transistors do not overlap the M1 wiring line (32a) connected to the gates of the transistors.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
A memory cell includes a power supply line extending in a Y-direction and configured to supply a power supply voltage. A well tap cell includes: a power supply line extending in the Y-direction, electrically connected to the power supply line, and configured to supply the power supply voltage; and a line formed in an M1 line layer, extending in an X-direction, electrically connected to the power supply line, and configured to supply the power supply voltage. The well tap cell supplies the power supply voltage to an N-well or a P-type substrate of the memory cell.
H10B 10/00 - Static random access memory [SRAM] devices
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
An image processing device includes a memory and a processor configured to separate first image data obtained by an image sensor having a Bayer arrangement, into second image data that includes brightness information, and third image data that includes color information and has a lower resolution than the first image data and the second image data, wherein a pixel arrangement of the third image data includes two pixels in each of a horizontal direction and a vertical direction, among which two pixels on one diagonal are of a same type, two pixels on another diagonal are of types different from each other, and the two pixels on said another diagonal are of the types different from the two pixels on the one diagonal.
H04N 9/78 - Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter
H04N 23/80 - Camera processing pipelinesComponents thereof
H04N 23/84 - Camera processing pipelinesComponents thereof for processing colour signals
