Abstract

A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

IPC Classes  ?

• H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details

Abstract

An amplification arrangement comprises a signal-processing element (SVE) with an integrator element (INT) that is coupled on the input side with a first input (E1) for feeding the input signal and with a second input (E2) for feeding a feedback signal. The signal-processing element (SVE) is designed to set a respective level of the input signal and/or the feedback signal as a function of a control signal. The amplifier arrangement furthermore comprises a pulse modulator (PM) that is designed to generate a pulse signal on a pulse output (POT) as a function of a signal applied on the output (SOT) of the signal-processing element (SVE). An output stage (OST) comprises a switching element (SW) that is designed to connect supply-voltage terminals (V1, V2, GND) to an output terminal (OOT) that is coupled with an amplifier output (AOT) and the second input (E2), and a control unit (CU) for driving the switching element (SW) that is coupled with the pulse output (POT). A level control unit (PSE) is designed to generate the control signal such that the respective level in the signal-processing element (SVE) is reduced as a function of an overshooting of a specified pulse-duty factor of the pulse signal.

IPC Classes  ?

• H03F 3/38 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers

Abstract

A method, computer readable medium, and system for controlling velocity of an at least partially resonant actuator system in accordance with embodiments of the present invention includes determining with an actuator controller computing device a sequence of full bridge and half bridge outputs to control an output velocity of an at least partially resonant actuator device. The actuator controller computing device controls a driver system to output a driving signal based on the determined sequence of full bridge and half bridge outputs. The driver system provides the driving signal to the at least one at least partially resonant actuator device.

IPC Classes  ?

• H01L 41/08 - Piezo-electric or electrostrictive elements
• H01L 41/09 - Piezo-electric or electrostrictive elements with electrical input and mechanical output

Abstract

In the high-voltage transistor, which is suitable for an ESD-protection circuit, there is no doped well or at most a portion of a second well (3) of a second conductivity type opposite a first conductivity type under a contact region (4) for the drain between a first well (2) and a semiconductor material of the substrate (1), said semiconductor material being undoped or being doped for the first conductivity type. Said portion has a lower thickness than a thickness which would provide a good insulation of the first well from the substrate and which would provide a high breakdown voltage.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

On a doped well (2) for a drift section, at least two additional dielectric regions (7, 9) having different thicknesses are present between a first contact region (4) for drain and a second contact region (5) for source on the upper face (10) of the substrate (1), and the gate electrode (11) or an electric conductor, which is electrically conductively connected to the gate electrode, covers each of said additional dielectric regions at least partially.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

A connection contact layer (4) is disposed between semiconductor bodies (1, 2). In the second semiconductor body (2), a recess is provided. A connection layer (7) on the top face extends as far as the recess, in which a metallization (10) is present that conductively connects the connection contact layer (4) to the connection layer (7) in an electrical manner. A polymer (8) or a further metallization is present in the recess.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A capacitor arrangement comprises a capacitor (16), a transistor (11) which is coupled in series to the capacitor (16), a resistor (15) and a switch arrangement (42). The switch arrangement (42) has a first terminal (17) for receiving a first voltage (V1), a second terminal (28) for receiving a second voltage (V2) and an output (45) which is coupled via the resistor (15) to a node (18) between the capacitor (16) and the transistor (11). The switch arrangement (42) is designed such that the first voltage (V1) is applied to the output (45) of the switch arrangement (42) during a first state of operation of the transistor (11) and the second voltage (V2) is applied to the output (45) of the switch arrangement (42) during a second state of operation of the transistor (11).

IPC Classes  ?

• H03J 1/00 - Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general

Abstract

A substrate (1) of semiconductor material is provided with a contact pad (7). An opening (9) is formed through the semiconductor material from an upper surface to the contact pad, the opening forming an edge (18) at or near the upper surface. A dielectric layer (10) is applied on the semiconductor material in the opening. A metallization (11) is applied, which contacts the contact pad and is separated from the substrate by the dielectric layer. A top-metal (12) is applied, which contacts the metallization at or near the edge. A protection layer (13) is applied, which covers the top-metal and/or the metallization at least at or near the edge, and a passivation (15) is applied.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

In one embodiment, a circuit arrangement with a column latch has a first terminal (A1) for connection to a bit line (BL) of a nonvolatile memory, a second terminal (A2) connected via a first switchable path (P1) to a reference-potential terminal (VSS) and via a second switchable path (P2) to a supply-potential terminal (VPP), and the column latch (100, 110), which is coupled to the second terminal (A2) and is adopted for storing a potential at the second terminal (A2). The first terminal (A1) is coupled to the second terminal (A2) via a first switchable connection (L1) and via a second switchable connection (L2). A method for operating a column latch is additionally disclosed.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store

Abstract

In a measurement method, a plurality of magnetic field sensors (MS0-MS15) that are arranged along a circular periphery (CIR) and are each configured to emit a sensor signal (H0-H15) as a function of a magnetic field intensity is provided. A diametrically magnetized magnetic source (MAG) seated rotatably on the circular periphery (CIR) about an axis of rotation (RA) is further provided. A first set of sensor signals from the magnetic field sensors (MS0-MS15) is received and a first orientation (AL1) of an axis (AX) defined by a reference value transition (RFD) is determined as a function the first set. After a rotation of the magnetic source (MAG) about the axis of rotation (RA), a second set of sensor signals is received and a second orientation (AL2) of the axis (AX) is determined as a function of the second set of sensor signals. A position (X0, Y0) of the axis of rotation (RA) is acquired as a function of the first and the second orientation (AL1, AL2).

IPC Classes  ?

• G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes

Abstract

A voltage transformer (10) comprises an inductor (11), a first and a second switch (15, 16), and a control unit (25). An input voltage (VIN) is fed to a first terminal (12) of the inductor. The first switch (15) is disposed between a second terminal (13) of the inductor (11) and a reference potential terminal (17). The second switch (16) is disposed between the second terminal (13) of the inductor (11) and an output (19) of the voltage transformer (10). The control unit (25) is designed to set the first switch (15) in a first and a second phase (A, B) of a first operating mode of the voltage transformer (10) into a blocking operating state and to set the second switch (16) in the first phase (A) into a conducting operating state and in the second phase (B) into an operating state having different conductivity.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Abstract

A multi-current-source comprises a voltage converter (VC), a first current source (CS1) with a first terminal (A1) which is adapted to be coupled to an output (OUT) of a voltage converter (VC) and with a second terminal (B1) which is adapted to be coupled to an input (IN) of the voltage converter (VC), at least a second current source (CS2) with a first terminal (A2) which is adapted to be coupled to the output (OUT) of the voltage converter (VC) and with a second terminal (B2) which is adapted to be coupled to the input (IN) of the voltage converter (VC), wherein the first current source (CS1) being adapted to provide a first load current (Il1) at its first terminal (A1) the first load current (Il1) being regulated to a first constant value and to provide a first unidirectional error current (Ierr1) at its second terminal (B1), wherein the at least one second current source (CS2) being adapted to provide a second load current (Il2) at its first terminal (A2), the second load current (Il2) being regulated to a second constant value and to provide a second unidirectional error current (Ierr2) at its second terminal (B2), such that a sum of the first unidirectional error current (Ierr1) and the second unidirectional error current (Ierr2) adjusts the first and the second load current (Il1, Il2).

IPC Classes  ?

• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
• G05F 3/26 - Current mirrors
• H05B 37/02 - Controlling

Abstract

A coupling circuit has a first and a second transistor (P1, P2) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P1) is connected to a signal input (1), source terminals of the first and the second transistor (P1, P2) are commonly connected to a signal output (2), bulk terminals of the first and the second transistor (P1, P2) are commonly connected to a drain terminal of the second transistor (P2), and a gate terminal of the first transistor (P1) is connected to a gate terminal of the second transistor (P2). The coupling circuit further comprises a gate control circuit (10) with a charge pump circuit (110) which is configured to generate a negative potential. The gate control circuit (10) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P1, P2) based on a negative potential.

IPC Classes  ?

• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage

Abstract

The invention relates to a semiconductor body comprising a first connection (VDD) for feeding an upper supply potential and a first and a second terminal cell (IO1, IO2), which are situated at a distance from each other. The semiconductor body further comprises an arrester structure (PCL), which is arranged between the first and second terminal cells (IO1, IO2) in a p-doped substrate (PSUB). The arrester structure (PCL) comprises a first and a second p-channel field effect transistor structure (PMOS3, PMOS4), each of which is set in a respective n-doped well (NW61, NW62) substantially parallel to the first and second terminal cells (IO1, IO2), and a diode structure (TRG) with a p-doped region set in a further n-doped well (NW63) between the n-doped wells (NW61, NW62) of the first and second p-channel field effect transistor structures (PMOS3, PMOS4). The diode structure (TRG) is designed to activate the first and second p-channel field effect transistor structure (PMOS3, PMOS4) as arrester elements during an electrostatic discharge in the semiconductor body.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A well (2) doped for a conductivity type and provided as the sensor region is formed in a substrate (1) made of semiconductor material. Contact regions (4), arranged spaced apart from one another and doped for the same conductivity type as the well (2), are formed in a cover layer (3) that delimits the region with the conductivity type of the well. The contact areas (4) are electroconductively connected to the well (2) and provided for terminal contacts (6).

IPC Classes  ?

• G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures

Abstract

A switched amplifier circuit arrangement comprises a main amplifier (Amp) having an input terminal (In) and an output terminal (Out) and a regulating amplifier (rAmp) to set an input and an output operating point of the main amplifier (Amp). The regulating amplifier (rAmp) exhibits an auxiliary amplifier (A) having a first input terminal coupled to a reference level (Vref), a second input terminal (Ain) coupled to the output terminal (Out), and an output terminal (Aout) which is connected via a first switch (S1) to the input terminal (In). Moreover, the switched amplifier circuit arrangement comprises a cancellation capacitor (Cc) coupled to the input terminal (In), a second switch (S2) which is coupled between the output terminal (Out) and the cancellation capacitor (Cc) at a first circuit node (n1), and a third switch (S3) connected between the circuit node (n1) and the reference level (Vref).

IPC Classes  ?

• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage

Abstract

In a measurement method, an array of magnetic field sensors (MS0-MS15) is provided, each emitting a sensor signal as a function of magnetic field intensity. A rotational value of a sector-wise magnetized magnetic source that is arranged movably with respect to the array is ascertained as a function of the emitted sensor signals. A set of sensor values is derived from the sensor signals. As a function of the ascertained rotational value, a number of sets of reference values is ascertained that corresponds to a number of predetermined positions of the magnetic source (MAG). The set of sensor values and the number of sets of reference values are compared to one another, and a position is selected from the number of predetermined positions as a function of the comparison.

IPC Classes  ?

• G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes

Abstract

The invention relates to an integrated circuit having a signal processing arrangement, comprising a counter (Cnt) for counting recursion steps, coupled to a generator (G) and a correction device (K), and providing a counter value (n) of recursion steps to the generator (G) and the correction device (K). The generator (G) recursively generates a recursion signal (f(n)) for each counter value and provides the same at an output. The correction device (K) is coupled to the output of the generator by means of an input, and generates a corrected recursion signal (g(n)) from the recursion signal (f(n)) as a function of the counter value (n), available at a first output of the correction device (K) and a second output (Out) for providing an output signal of the signal processing arrangement. The first output of the correction device (K) is coupled to the input of the generator (G).

IPC Classes  ?

• G06F 7/548 - Trigonometric functionsCo-ordinate transformations
• G06F 1/03 - Digital function generators working, at least partly, by table look-up
• G06F 1/035 - Reduction of table size

Abstract

An RFID tag comprising a private key of a product whereon the RFID is adhered communicates with a user interrogator and a professional interrogator. The professional interrogator determines two locations within the tag, which are accessible by the user interrogator, as the location of a URL address of an application providing for the authentication of a digital signature, which has been generated by the cryptographic algorithm implemented in the tag, and as the location of a URL address of the public key, which together with said private key has been generated by the cryptographic algorithm implemented in the tag. The method of the invention enables a potential end user of said product to acquire key data for authentication of said tag and then to authenticate it by means of a widely available user interrogator, e.g. an NFC portable telephone, both without any specific technical knowledge.

IPC Classes  ?

• G06F 21/35 - User authentication involving the use of external additional devices, e.g. dongles or smart cards communicating wirelessly

Abstract

A method for DC/DC conversion comprises operating in a Boost mode of operation or in a Buck-Boost mode of operation. Furthermore, the method comprises switching from the Boost mode of operation to the Buck-Boost mode of operation, if a desired value (VOUTR) of an output voltage (VOUT) which is generated from a supply voltage (VIN) by the DC/DC conversion is smaller than a first reference voltage (VR1). The method also comprises switching from the Buck-Boost mode of operation to the Boost mode of operation, if the desired value (VOUTR) is larger than a second reference voltage (VR2).

IPC Classes  ?

• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems

Abstract

An oscillator circuit comprises a charging block with a first terminal for feeding a first charging current, to which terminal a first capacitor and a series circuit of a first and a second switch are connected, and with a second terminal for feeding a second charging current, to which terminal a second capacitor and a series circuit of a third and a fourth switch are connected, as well as a comparison circuit with a first and a second comparator. The comparators are configured to compare voltages at the first and second terminals to a reference voltage, wherein their output is connected to control terminals of the third or first switch. The oscillator circuit further comprises a flipflop that is coupled on the input side to the outputs of the first and second comparators, and on the output side, to control terminals of the second and fourth switches, as well as to an oscillator output.

IPC Classes  ?

• H03K 3/26 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback

Abstract

The circuit arrangement for switching a capacitance comprises a full-bridge circuit, the shunt path of which contains the capacitance (C), and a switch apparatus and can be connected to a voltage source (Vdd). A switching element (S) controls the switch apparatus such that the switch apparatus shorts the capacitance (C) and, when a predetermined charge state of the capacitance (C) is reached, cancels the short.

IPC Classes  ?

• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources

Abstract

The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

Abstract

c) of the first transistor (T1). A capacitive element (C1) is coupled between the first connection (T11) of the first transistor (T1) and the second connection (T22) of the second transistor (T2) and a filter output (6) is coupled to the first connection (T11) of the first transistor (T1).

IPC Classes  ?

• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

The invention relates to a circuit arrangement (20) for a piezo transformer (22) comprising a driver circuit (23), to which the piezo transformer (22) can be connected, and a current sensor (21) for determining an incoming power signal (IM), which is subject to an incoming current (IE) flowing through the piezo transformer (22). The invention further relates to the circuit arrangement (20) of a control unit (24) for providing a control signal (ST), which is subject the incoming power signal (IM,) and an oscillator (25) having an oscillator output (43) for emitting an oscillator signal (SO) to a driver signal input (44) of the driver circuit (23) subject to the control signal (ST).

IPC Classes  ?

• H05B 41/282 - Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters with semiconductor devices

Abstract

A circuit arrangement for temperature measurement comprises an input for connecting a temperature-sensitive element (T) that is connected to a first input of a comparator (C). A reference voltage (Vref) is connected to a second input of the comparator (C). Furthermore, the arrangement comprises a sequential logic (SL) that is coupled to an output of the comparator (C) and that comprises a first output (A1) and a second output (A2). A digitally controllable switch element (DS) for providing a superposition signal is connected to the output (A1) of the sequential logic and the first input of the comparator (C).

IPC Classes  ?

• G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
• G01K 3/00 - Thermometers giving results other than momentary value of temperature
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

A voltage regulator (10) comprises a first transistor (13) which couples an input terminal (11) of the voltage regulator (10) to an output terminal (12) of the voltage regulator (10) and a second transistor (16). The first and the second transistors (13, 16) form a current mirror structure. Further on, the voltage regulator (10) comprises a control node (17) which is coupled to the input terminal (11) of the voltage regulator (10) via the second transistor (16) and which is coupled to the output terminal (12) of the voltage regulator (10) via a feedback circuit (28). Furthermore, the voltage regulator (10) comprises an amplifier (22) with an input terminal (23) which is coupled to the control node (17) and an output terminal (24) which is coupled to a control terminal (21) of the second transistor (16).

IPC Classes  ?

• G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices

Abstract

The channel region (16) of the transistor is located in a doped well (5, 6) on a side of the source facing away from the drain, said well forming a pn junction with a surrounding additional doped well (4). The drift region (17) extends from said pn junction through the semiconductor material of the additional doped well to the drain.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/40 - Electrodes
• H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

An antenna circuit (A) is fed with a signal, to whose frequency it should be tuned. Its reactance changes stepwise according to an algorithm implemented in a controller (C). A voltage phases at terminals (1, 2) of an element (c0, c1,..., en; co) having the reactance of one kind are determined and the difference of said phases is determined. The reactance changes so many times that said phase difference approaches to π/2 closer than a tiniest phase difference is as can be set by said changing of the reactance. The achieved setting is stored as the setting of the antenna circuit tuned to said frequency. Tuning is carried out automatically and time-efficiently especially according to the first embodiment also in a simple way since no analogue-to-digital conversion is needed.

IPC Classes  ?

• G06K 7/00 - Methods or arrangements for sensing record carriers
• G06K 7/08 - Methods or arrangements for sensing record carriers by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
• H03J 7/04 - Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
• H03J 1/00 - Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
• H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line

Abstract

A circuit arrangement for protection against electrostatic discharges comprises an shunt device, which is connected between a first and a second terminal of the circuit arrangement and has a control input, via which the conduction of the shunt device can be controlled. In addition there is a trigger element, which has a trigger output for issuing a trigger signal in dependence on a voltage between the first and the second terminal of the circuit arrangement. The circuit arrangement additionally comprises an interruption unit that can be controlled via a deactivation input by means of a sendable deactivation signal and which is connected on the input side to the trigger output and on the output side to the control input. In addition, a method for shunting electrostatic discharges is shown.

IPC Classes  ?

• H02H 3/22 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage of short duration, e.g. lightning

Abstract

The invention relates to a voltage converter comprising a step-down converter circuit (DCDC) provided with an inductive accumulator (LSW), a first capacitive accumulator (CDC) and a charge pump circuit (CP) having at least one second capacitive accumulator (CFLY, CFLY1, CFLY2). Said step-down converter circuit (DCDC), which can receive on the input side a supply voltage (VBAT), is designed in such a manner that the first capacitive accumulator (CDC) is charged with a first intermediate voltage in the switched state. Said charge pump circuit (CP) is designed to charge the at least one second capacitive accumulator (CFLY, CFLY1, CFLY2) with a second intermediate voltage using the supply voltage (VBAT) and an output voltage is produced from the first and the second intermediate voltage.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

Abstract

In one embodiment, a charging circuit for a charge accumulator comprises a first connection (A1) for supplying a charge voltage (UC) and for connecting the charge accumulator (SC) based on the reference potential connection (10), a second connection (A2) for providing a load voltage (UD) and for connecting an electrical load (D1), a control assembly (ST) which is coupled to the first and the second connections (A1, A2) and has a signal output (A3) for providing a first charge state signal (S1) and a test output (TA) for providing a test signal (on), and a power source (I1) that is coupled to the second connection (A2), wherein the first charge state signal (U12) is provided depending on a value of an additional voltage (U12) between the first and the second connections (A1, A2) and depending on the test signal (on), and wherein the charge voltage (UC) is supplied depending on the first charge state signal (S1). The invention also relates to a method for charging a charge accumulator.

IPC Classes  ?

• H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

An amplitude of a carrier signal at an output of an impedance matching block is measured as a first amplitude value. A value of the signal amplitude at the output of the impedance matching block is calculated as a second amplitude value that a signal resulting from amplitude modulation with said modulation factor from said carrier signal should assume, said carrying signal having an amplitude with the first amplitude value. A setting of a transmitter is changed to decrease the carrier signal amplitude at the output of the impedance matching block. An amplitude of a new carrier signal at the output of the impedance matching block is measured as a new amplitude value. The transmitter setting keeps changing so many times until the new amplitude value is equal to or lower than said second amplitude value or within a predetermined tolerance range around said second amplitude value. Parameters of the last new transmitter setting are stored as the parameters of the transmitter setting, by means of which the transmitter will generate a transmitted signal being amplitude-modulated in the specified manner. The setting of the amplitude modulation with the specified modulation factor is carried out automatically. The designing of the transmitter circuit is simplified.

IPC Classes  ?

• G06K 7/00 - Methods or arrangements for sensing record carriers
• G06K 7/08 - Methods or arrangements for sensing record carriers by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
• H03C 1/00 - Amplitude modulation
• H03K 7/02 - Amplitude modulation, i.e. PAM

Abstract

Through a main surface (10) of a semiconductor substrate (1) of a first type of conductivity, a doped well of a second type of conductivity is implanted to form a sensor region (3) extending perpendicularly to the main surface. The sensor region can be confined laterally by trenches (5) comprising an electrically insulating trench filling (6). The bottom of the sensor region is insulated by a pn-junction (20). Contacts (4) are applied to the main surface and provided for the application of an operation voltage and the measurement of a Hall voltage.

IPC Classes  ?

• H01L 43/04 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details of Hall-effect devices
• H01L 43/14 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof for Hall-effect devices

Abstract

A circuit to be protected is discharged with a discharging stage in the event of a surge. An actuating stage connected to the discharging stage triggers the discharge. The discharging stage comprises one or more bipolar transistors having an emitter (CE1), a base (B12), and a collector (CE2). The actuating stage formed by the base and the emitter, or by the base and the collector, is a trigger diode.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

TH) is a current comparator with two current branches (5, 6). One of these two current branches is used in the present case for guiding a charging or discharging current of the charge storage device (1). In this way, a current branch is eliminated, so that the proposed principle is preferably suitable for so-called ultra low power applications.

IPC Classes  ?

• H03K 3/26 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback

Abstract

A sensor system and method of operating such a sensor system for measuring an angle of rotation with an arrangement of at least four magnetic sensors (10, 11, 12, 13), at least four signal modulators (30, 31, 32, 33), each one connected to one of the magnetic sensors (10, 11, 12, 13) and having at least two control states, whereby, in a first state (+), a signal received from a sensor (10, 11, 12, 13) is output by the signal modulators (30, 31, 32, 33) and, in a second state (−), the inverse of the signal received from the sensor (10, 11, 12, 13) is output by the signal modulators (30, 31, 32, 33), a means (90) for adding the signals output by the signal modulators (30, 31, 32, 33) and a diametrically magnetized magnetic source (9). The sensor system further comprises a data output (82) and a control circuit (80) with at least one control input (81), allowing to switch the control circuit (80) into at least two different modes. In a normal mode of operation, the signal modulators (30, 31, 32, 33) are configured in such a way that a signal corresponding to the angular position of the diametrically magnetized magnetic source (9) is output to the data output. In an alignment mode of operation, the signal modulators (30, 31, 32, 33) are configured in such a way that a signal corresponding to the average magnetic field strength detected by the sensors (10, 11, 12, 13) is output to the data output (82).

IPC Classes  ?

• G01R 33/07 - Hall-effect devices

Abstract

A wake-up method for a multi-channel receiver comprises the following steps: checking for activity on every available channel by switching from one channel to the next thereby activating and subsequently deactivating one channel after the other;when activity is detected at least on one of the available channels,switching on all channels, measuring a respective received signal strength in every channel and performing a comparison of received signal strengths between all channels; and selecting the channel with the highest received signal strength. Further a multi-channel wake-up receiver is presented.

IPC Classes  ?

• H04W 72/02 - Selection of wireless resources by user or terminal
• H04W 52/02 - Power saving arrangements
• H04W 24/00 - Supervisory, monitoring or testing arrangements
• H04W 24/10 - Scheduling measurement reports

Abstract

A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto. A control circuit receives the respective first and second indication signal and provides the control signal to the controlled and clocked operated power source in response thereto.

IPC Classes  ?

• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources

Abstract

A DC/DC converter comprises an inductive element (L) having a first terminal connected to an input connection (1) and a second terminal (4) coupled to a reference potential connection (3) by a first switching element (N1). A second switching element (P1) being a p-channel field-effect transistor couples the second terminal (4) to an output connection (2). A control unit (CTL) comprises a detection unit which is configured to detect a first mode of operation in which an input voltage (VIN) is higher than a desired output voltage (VOUT). The control unit is configured, upon detection of the first mode of operation, during a first phase (PH1) to control the first switching element (N1) to a closed state and a second switching element (P1) to an open state, during a second phase (PH2) which comprises a first sub-phase (PH2A) and a second sub-phase (PH2B), to control the first switching element (N1) to an open state, during the first sub-phase (PH2A), to control the second switching element (P1) to a closed state, and, during the second sub-phase (PH2B), to provide a control voltage to a gate terminal of the second switching element (P1) which is higher than a difference between an output voltage (VOUT) and a threshold voltage of the second switching element (P1).

IPC Classes  ?

• G05F 1/10 - Regulating voltage or current
• G05F 1/40 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices

Abstract

The invention relates to a handling wafer having a metal layer (2) applied thereto and connected to the back side of an IC wafer (3) by means of a connecting layer (12). After etching a contact hole (7) in the IC wafer and applying a metallization (13) connecting the metal layer (2) to a top-side metal connection layer (14), the handling wafer is removed so that a back-side contact surface (17) of the metal layer is exposed. The interlayer connection so formed allows arbitrary positioning of the back-side contact without a complex back-side process.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

The invention relates to semiconductor components (S1, S2) connected to each other by means of a connecting layer (5). A connection contact layer (17) is connected to a connection metal layer (12) by means of a metallization (11) in contact hole (14). The connection contact layer and the connection metal layer can be connected to a wiring by means of a metal level (7), or to a contact surface for connecting to a further semiconductor component.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A voltage converter comprises a first, a second and a third capacitor (11, 12, 13) which are switched in series in at least one operating state, an input (1) for supplying an input voltage (VIN), an output (2) for providing an output voltage (VOUT), and a compensation circuit (5). The input (1) of the voltage converter is coupled to a capacitor from a group comprising the first, the second and the third capacitor (11, 12, 13). The output (2) of the voltage converter is coupled to a capacitor from the group comprising the first, the second and the third capacitor (11, 12, 13). The compensation circuit (5) is coupled to the first, the second and the third capacitor (11, 12, 13) and adapts a first voltage (V1) of the first capacitor (11), a second voltage (V2) of the second capacitor (12) and a third voltage (V3) of the third capacitor (13) to one another.

IPC Classes  ?

• H02M 3/18 - Conversion of DC power input into DC power output without intermediate conversion into AC by dynamic converters using capacitors or batteries which are alternately charged and discharged, e.g. charged in parallel and discharged in series

Abstract

An input circuit arrangement comprises an input, a comparator, and an evaluation circuit. The input is designed for coupling to a first terminal of an impedance and for feeding an input signal. The comparator is connected to the input of the input circuit arrangement and is designed for delivering an activation signal to an output as a function of a comparison of the input signal with an adjustable threshold. Furthermore, the evaluation circuit is connected to the input of the input circuit arrangement and for its activation to the output of the comparator and is designed for evaluating the value of the impedance that can be connected.

IPC Classes  ?

• H03K 17/16 - Modifications for eliminating interference voltages or currents

Abstract

The invention relates to a chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VDD) to the external supply connection (VBAT) and is arranged within the chip design (1).

IPC Classes  ?

• H01H 37/76 - Contact member actuated by melting of fusible material, actuated due to burning of combustible material or due to explosion of explosive material
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

An amplifier arrangement has an amplifier (3) with a signal input (31), a feedback input (32) and a signal output (33). A first coupling path (FB1), which has a first impedance element (R1), connects the feedback input (32) to the signal output (33). A second coupling path (FB2) has a filter device (4), a buffer circuit (5) and a second impedance element (R2) connected in series, and connects the feedback input (32) to the signal output (33) or to the signal input (31).

IPC Classes  ?

• H03F 1/36 - Negative-feedback-circuit arrangements with or without positive feedback in discharge-tube amplifiers

Abstract

A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from the semiconductor material; at least one recess in the gate electrode, a through-contact arranged in the recess of the gate electrode, the through-contact being electrically insulated from the gate electrode; a terminal contact on the semiconductor material; and a terminal conductor arranged on the side of the gate electrode that faces away from the substrate, wherein the through-contact electrically connects the terminal contact to the terminal conductor.

IPC Classes  ?

• H01L 21/8249 - Bipolar and MOS technology

Abstract

A microcontroller comprises a microprocessor (1), a test interface (4) and an internal non-erasable memory (2). First control means (6) are provided which are able to activate and deactivate the test interface (4), and second control means (7) are provided which are able to activate and deactivate the internal non-erasable memory (2). The microprocessor (1) of the microcontroller comprises control outputs (101) which are connected with the first and second control means (6, 7). With appropriate timing of activation and deactivation of the test interface (4) and the internal non-erasable memory (2), the microcontroller offers the possibility of preventing an unauthorized access to contents of the internal non-erasable memory (2) without limiting the usability of the test interface (4) for the development of application programs. The microcontroller further offers the possibility to entirely block access to data which are stored in the microcontroller or have been processed within the microcontroller via the test interface (4).

IPC Classes  ?

• G06F 11/30 - Monitoring

Abstract

A method, in which a first isolating trench, filled with a dielectric material, and a second conducting trench, filled with an electrically conductive material, can be produced. To this end, the first and second trenches are etched with different trench widths, so that the first trench is filled completely with the dielectric material after a deposition of a dielectric layer over the entire surface with the edges covered, whereas the wider second trench is covered by the dielectric layer only on the inside walls. By anisotropic back-etching of the dielectric layer, the semiconductor substrate is exposed at the bottom of the second trench. Subsequently, the second trench is filled with an electrically conductive material and then represents a low-ohmic connection from the substrate surface to the buried structure located below the second trench.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components

Abstract

An etch apparatus, especially for silicon nitride etch includes a control unit coupled to at least one component of the group of components comprising heater current sensors, a pump transducer sensor and a flow sensor provided for a diluting liquid. A malfunction of the apparatus is avoided and the etching process can be controlled for better performance.

IPC Classes  ?

• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

Abstract

A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A voltage converter is provided in which a first terminal (A) and a second terminal (B) are provided, each coupled to a switching means, the switching means is coupled to respective terminals for connecting a first capacitor (C1), a second capacitor (C2) and a third capacitor (C3), and the voltage converter is configured for being operated in first and second modes of operation each comprising at least three phases, and in which the three capacitors (C1, C2, C3) are inserted in series connection (S) between the first terminal (A) and a reference potential terminal (10) in one phase, and in each of the two other phases a first path and a second path (P1, P2) are provided in each case in parallel connection with at least one of the three capacitors (C1, C2, C3) related to the second terminal (B).

IPC Classes  ?

• H02M 3/18 - Conversion of DC power input into DC power output without intermediate conversion into AC by dynamic converters using capacitors or batteries which are alternately charged and discharged, e.g. charged in parallel and discharged in series

Abstract

A circuit arrangement including a fuse comprises a fuse path (SP) which is coupled to a control input (SE) and comprises the fuse (RS) and a first charge reservoir (C1) serially connected thereto for providing a first charge state (L1), a reference path (RP) which is coupled to the control input (SE) and comprises a comparison element (RV) and a second charge reservoir (C2) serially connected thereto for providing a second charge state (L2), and an evaluation unit (AE) comprising a first input (E1) connected to the fuse path (SP) in a switchable manner, a second input (E2) connected to the reference path (RP) in a switchable manner, and a data output (DA) for providing a condition of the fuse (RS) depending on a difference between the first and second charge states (L1, L2). Further, a method for determining the condition of a fuse is provided.

IPC Classes  ?

• H01H 85/30 - Means for indicating condition of fuse structurally associated with the fuse

Abstract

A semiconductor body (1) comprises a first contact pad (2), a second contact pad (3), an integrated circuit (5) and an impedance (4). The integrated circuit (5) comprises a first terminal (6) which is coupled to the first contact pad (2) and a second terminal (7) which is coupled to the second contact pad (3). The impedance (4) additionally couples the first contact pad (2) to the second contact pad (3).

IPC Classes  ?

• H02J 1/00 - Circuit arrangements for dc mains or dc distribution networks

Abstract

An active noise control arrangement has a signal input (SI), a microphone input (MI), a signal output (SO) and a digital interface (DI). A signal processing block (SP) coupled to the microphone input (MI) by means of an amplifier (MA) has a digitally adjustable gain and comprises combining means (CM) and a filter (TP). The signal processing block (SP) is configured to generate an output signal at the signal output (SO) as a function of an input signal at the signal input (SI) and an amplified microphone signal. A control block (CB) is coupled to the digital interface (DI) and configured to adjust the gain of the amplifier (MA).

IPC Classes  ?

• G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase

Abstract

A controlled charge pump (2) comprises a clock operated charge pump (20) having an output terminal (12) to provide an output voltage (Vo). A first sub-circuit (50) is coupled to the output terminal (12) of the clocked operated charge pump (20) and adapted to provide a first control signal in response to a comparison of the output voltage (Vo) with a first reference signal (Vref). A second sub-circuit (10, 40) is coupled to the clocked operated charge pump (20) and provides a second control signal in response to a comparison of a switch current within the clocked operated charge pump with a second reference signal (Iref). A clock skip controller (30) is adapted to control the mode of operation of the clocked operated charge pump (20) in response to that first and second control signals.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

Abstract

A semiconductor body comprises a protective structure. The protective structure (10) comprises a first and a second area (11, 12) of a first conductivity type, and a third area (13) of a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first and the second areas (11, 12) are disposed at a distance in the third area (13) so that a current flow from the first area (11) to the second area (12) is enabled for the purposes of limiting a voltage difference between the first and the second areas (11, 12). The protective structure comprises an insulator (14) disposed on the semiconductor body (9) and an electrode (16) designed with a floating potential, said electrode being disposed on the insulator (14).

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A circuit arrangement (1) comprises a current source (10), a comparator (50) and a control device (90). The current source (10) serves for supplying a light-emitting diode (41). The comparator (50) may be coupled to the light-emitting diode (41) at a first input (51) via a push-button (101). The comparator (50) may be fed with a reference voltage (VREF) at a second terminal (52). The control device (90) selectively puts the current source (10) into a first operational state (A) for polling a push-button position of the push-button (101) or into a second operational state (B) for emitting radiation by means of the light-emitting diode (41).

IPC Classes  ?

• H03M 11/00 - Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys

Abstract

An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (3, 4), and with the aid of the comparator (6) into a digital output signal.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters

Abstract

A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

IPC Classes  ?

• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array

Abstract

In one form of embodiment, a circuit for controlling a light source comprises an amplitude value detector (MD) having an inlet (E) for supplying a digital inlet signal (Sin) and an output (A1) for respectively providing determined amplitude values of the digital inlet signal (Sin) over a time interval, a filter (F) coupled to the outlet (A1) of the amplitude value detector (MD), and an outlet (A) for connecting to the light source. The invention also relates to a method for producing a control signal for a light source.

IPC Classes  ?

• A63J 17/00 - Apparatus for performing colour-music
• H05B 37/02 - Controlling

Abstract

In one form of embodiment, a central unit especially for using in a network comprises a memory (2) having at least one light pattern (L) suitable for reproducing on a terminal unit (5), a control logic system (3) connected to the memory (2), and a communication interface coupled to the control logic system (3), for providing the at least one light pattern (L) for the terminal unit (5). In another form of embodiment, a terminal unit especially for using in a network comprises a sequence control unit (10), a communication interface (11) connected to the sequence control unit (10) and set up to download at least one light pattern (L) from the network, and a memory (12) coupled to the sequence control unit (10), for storing the at least one light pattern (L). In a further form of embodiment, a system for downloading a light pattern comprises a central unit (1), a terminal unit (5), and a communication device (7) for transmitting at least one light pattern (L) from a communication interface (4) of the central unit to a communication interface (11) of the terminal unit (5).

IPC Classes  ?

• A63J 17/00 - Apparatus for performing colour-music
• H05B 37/02 - Controlling

Abstract

A connection pad (7) is arranged in the insulation layer (2) of an SOI substrate (1). A contact hole opening (9) over the connection pad is provided with a metalization (11) on side walls and on the connection pad. The metalization is contacted at the top with a top metal (12).

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A switch arrangement comprises a first and a second terminal (1, 2), a first switch (3), a current sensor (10), a first and a second control circuitry (20, 30). The first switch (3) comprises a control terminal (4), a first terminal (5) which is coupled to the first terminal (1) of the switch arrangement and a second terminal (6) which is coupled to the second terminal (2) of the switch arrangement. The current sensor (10) is realized for the measurement of a load current (Iload) flowing through the first switch (3). The first control circuitry (20) is coupled to an output terminal of the current sensor (10) and to the control terminal (4) of the first switch (3). The second control circuitry (30) is coupled to the control terminal (4) of the first switch (3).

IPC Classes  ?

• H01H 19/14 - Operating parts, e.g. turn knob

Abstract

A voltage conversion circuit comprises a first and a second output (O1, O2) which are configured to have an electric load (LD) connected in between, wherein an output signal between the first and a second output (O1, O2) is generated in response to a pulse-width modulated clock signal (PWM). The circuit further comprises a forward branch (FWD) being configured to generate an output voltage (VDC) at the first output (O1) depending on a control signal. A feedback branch (FBK) comprises a comparison circuit (CC) being configured to generate the control signal. The feedback branch (FBK) is configured to provide a first potential corresponding to a voltage (VSINK) at a second output (O2) to a comparison input (CI) of the comparison circuit (CC) during a first sensing period which corresponds to at least a part of a period of a first state of the clock signal (PWM) and to provide a second potential derived from the voltage (VSINK) at a second output (O2) by means of a first charge store (C1) to the comparison input (CI) during a second sensing period which corresponds to a part of a period of a second state of the clock signal (PWM).

IPC Classes  ?

• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Abstract

A control circuit for control of light-emitting diodes has a first LED string (50) with at least one LED (51, 52, 53) and a first supply device (1) for supply of current to the first LED string (50). The supply device (1) has a control input (10) for delivery of a first control signal (CTL) and is provided for delivery, as desired, of a first supply current (IV1) or a second supply current (IV2) in dependence on the first control signal (CTL). The first and the second control currents (IV1, IV2) are non-zero.

IPC Classes  ?

• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems

Abstract

An amplifier arrangement comprises a signal processing element (SVE) having an integrator element (INT), which is coupled on the input side to a first input (E1) for feeding the input signal and to a second input (E2) for feeding a feedback signal. The signal processing element (SVE) is designed to set a given level of the input signal and/or of the feedback signal as a function of a control signal. The amplifier arrangement furthermore comprises a pulse modulator (PM) designed to generate a pulse signal at a pulse output (POT) as a function of a signal present at the output (SOT) of the signal processing element (SVE). An output stage (OST) comprises a switch element (SW) that is designed to connect supply voltage connections (V1, V2, GND) to an output connection (OOT), which is coupled to an amplifier output (AOT) and to the second input (E2), and a control unit (CU) for actuating the switch element (SW), said control unit being coupled to the pulse output (POT). A level control unit (PSE) is designed to generate the control signal in such a manner that the respective level in the signal processing element (SVE) is reduced as a function of a predefined pulse-duty factor of the pulse signal being exceeded.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03G 3/30 - Automatic control in amplifiers having semiconductor devices

Abstract

A controlled current source comprises a signal input to receive a control input bus signal (D0,.., D[n-1]), a mapping unit (MU) with an input coupled to the signal input and an output to provide an internal control bus signal (d0,.., dn, Hc), a reference generator (RG) with an input coupled to the output of the mapping unit (MU) and with a low reference output to provide a low reference potential (Vg1) and with a high reference output to provide a high reference potential (Vgh), a current generating unit (CG) with a first input coupled to the output of the mapping unit (MU), a second input coupled to the output of the reference generator (RG) and an output to provide an output current (lout) controlled by the control input bus signal (D0.., D[n-1]) and the low and high reference potentials (Vgh, Vg1). Furthermore, a method for sourcing a current is provided.

IPC Classes  ?

• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Abstract

A modulation arrangement comprises an input (E) for supplying a data signal (DS), a pre-modulator (VMod) that is coupled to the input (E) and features a clock pulse input (TEV) for supplying a pre-clock pulse (VT), a main modulator (HMod) that is coupled to the pre-modulator (VMod) on the input side and comprises a clock pulse input (TEH) for supplying a main clock pulse (HT), as well as an output for providing a modulated control signal (ST), and a switchable current source (Q, S) for providing a current (IS) that is controlled by the modulated control signal (ST) at an output (A) of the modulation arrangement. Furthermore, a method for providing a modulated control signal is disclosed.

IPC Classes  ?

• H03K 7/08 - Duration or width modulation

Abstract

An amplifier arrangement includes an output amplifier stage (OA) comprising a stage input (SIN), a stage output (SOUT) which is coupled to a signal output (OUT) of the amplifier arrangement, and a capacitive element (CE) which couples the stage output (SOUT) to the stage input (SIN). A driver stage (DR) comprises a driver input (DIN) and a driver output (DOUT) which is coupled to the stage input (SIN). The driver stage (DR) is configured to generate a voltage potential at a driver output (DOUT) depending on an input current at the driver input (DIN) and to provide a charging current to the capacitive element (CE) being higher than the input current.

IPC Classes  ?

• H03F 1/14 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means

Abstract

A method for DC/DC conversion which comprises the steps of controlling a first switch (10) for coupling a supply terminal (5) to a first terminal (60) of an inductor (2) and a second switch (20) for coupling the first terminal (60) to a ground potential terminal (8). The method further comprises controlling a third switch (30) for coupling a second terminal (61) of the inductor (2) to the ground potential terminal (8) and a fourth switch (40) for coupling the second terminal (61) to an output terminal (6). A control sequence is used to control the four switches (10, 20, 30, 40) using four switching phases (A, B, C, D). A maximum of two switches out of the four switches (10, 20, 30, 40) change their switching position at a respective transition of subsequent switching phases (A, B, C, D).

IPC Classes  ?

• G05F 1/24 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using bucking or boosting transformers as final control devices

Abstract

A circuit arrangement (10) for driving an electrical load (2) comprises an input (11) for feeding a power-supply voltage (Vs) with an AC component and an output (13) for providing an output signal (Sout) for driving a connectable electrical load (2). The circuit arrangement (10) further comprises a frequency processing circuit (20) for proving a reference frequency (f1) as a function of the AC component, and a demodulator (60) with a first input (61) for feeding the reference frequency (f1), with a second input (62) that is coupled to the input (11) of the circuit arrangement (10), and with an output (63) that is coupled to the output (13) of the circuit arrangement (10).

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
• H03D 3/24 - Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits

Abstract

Regions doped on the top side with a dopant concentration of at most 1013 cm-3 are protected from contamination with dopant during a heat treatment step by producing an oxide layer (7) on the top side (6) and depositing a nitride layer (8) on the oxide layer. In this manner, the dopant concentration can be kept in the range of at most 1013 cm-3 close to the surface. Significant figure: 3

IPC Classes  ?

• H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
• H01L 21/223 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a gaseous phase
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 29/868 - PIN diodes
• H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type

Abstract

A circuit arrangement (1) for testing a reset circuit (11) comprises the reset circuit (11) and a changeover switch (14). The reset circuit has a voltage input (12) for supplying an input voltage (VDD) and an output (13) for providing a reset signal (POR) on the basis of the input voltage (VDD). The changeover switch (14) comprises a first input (15) for supplying a test voltage (VTM), a second input (16) for supplying a supply voltage (VBAT), a control input (17) for changing over between the first and the second input (15, 16) on the basis of a test adjustment signal (TM), and an output (18) which is coupled to the voltage input (12) of the reset circuit (11).

IPC Classes  ?

• G01R 31/30 - Marginal testing, e.g. by varying supply voltage
• G01R 31/3163 - Functional testing

Abstract

The invention relates to an amplifier arrangement having an input (1) for supplying a signal (Si) to be amplified, an output (2) for an amplified signal (So), and a first amplifier (100). The first amplifier (100) has a first input (11) which is coupled to the input (1) of the amplifier arrangement, a signal output (12) which is coupled to the output (2) of the amplifier arrangement, and a control output (13). The amplifier arrangement also has a second amplifier (200) with a first control input (21) which is coupled to the control output (13) of the first amplifier (100), and a current output (22) which is coupled to the signal output (12) of the first amplifier (100). In a first type of operation of the amplifier arrangement, only the first amplifier (100) amplifies the signal to be amplified (Si). In a further type of operation, the first amplifier amplifies with help from the second amplifier.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 3/185 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices

Abstract

A method includes a voltage converter outputting an output voltage that is based on an input voltage and on a first multiplication factor, determining a predicted current sink voltage based on a new multiplication factor obtained from a set of selectable values, based on a signal derived from the input voltage, based on a load voltage across an electrical load, and based on a correction voltage. The method also includes comparing a predicted current sink voltage with a predetermined threshold value and outputting the new multiplication factor to a control input of the voltage converter if the predicted current sink voltage exceeds the predetermined threshold value.

IPC Classes  ?

• G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
• G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Abstract

p) of the amplification phase. This avoids an undesired feed forward effect at the beginning of the amplification phase of an SC circuit.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

d) and the minimum of one further magnetic field sensor (11).

IPC Classes  ?

• G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures

Abstract

The invention relates to a current mirror arrangement comprising a switchable, adjustable current source (Q1, Q2) for providing an impressed current (IP), a current mirror (SP) having an input (E) for feeding in an impressed current (IP) and an output (A) for providing a current (I) and a step-up generator (AG) coupled to the current mirror (SP) such that the current (I) is switched on at an adjustable rise rate. The invention further relates to a method for switching on a current.

IPC Classes  ?

• G05F 3/26 - Current mirrors

Abstract

A filtering arrangement comprises a reference voltage input (1) and a compensation current arrangement (10) coupled to the reference voltage input (1) and configured to provide a control current at a current output (2) as a function of a voltage at the reference voltage input (1). The filtering arrangement also comprises a first and a second current source (20, 30) each having a control input (4, 5) coupled to the current output (2), a first and a second filter input (7, 8), and a first transistor (T1) and a second transistor (T2). The first transistor (T1) has a first connection (T11), a second connection (T12) and a control connection (T1c), where its first connection (T11) is coupled to the first current source (20) and its second connection (T12) is coupled to the first filter input (7) through a first resistor (Rl). The second transistor (T2) has a first connection (T21), a second connection (T22) and a control connection (T2c), where its first connection T21) is coupled to the second current source (30), its second connection (T22) is coupled to the second filter input (8) through a second resistor (R2) and its control connection (T2c) is coupled to its first connection (T21) and to the control connection (T1c) of the first transistor (T1). A capacitive element (C1) is coupled between the first connection (T11) of the first transistor (T1) and the second connection (T22) of the second transistor (T2) and a filter output (6) is coupled to the first connection (T11) of the first transistor (T1).

IPC Classes  ?

• H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback
• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof

Abstract

A circuit arrangement for DC/DC converters in particular has an input (E) for connecting a power accumulator (L1) and a power source (BT) connected thereto, an output (A) for driving an electrical load (D1, D2), a load current path (3), which can be switched, a charge current path (4), which can be switched, and a measuring apparatus (M) for detecting a load current (IL), which flows through the load current path (3). Furthermore, a method for controlling a DC/DC converter is provided.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
• G01R 19/10 - Measuring sum, difference, or ratio

Abstract

The invention relates to a measuring method wherein a plurality of magnetic field sensors (MS0 - MS15) are arranged along a circular periphery (CIR) and are adapted to emit a sensor signal (H0 - H15) depending on a magnetic field intensity. A diametrically magnetized magnetic source (MAG) is received to be rotatable on the circular periphery (CIR) about an axis of rotation (RA). A first set of sensor signals is received by the magnetic field sensors (MS0 - MS15) and a first alignment (AL1) of an axis (AX), which is defined by a reference value transition (RFD), is determined as the function of the first set. The magnetic source (MAG) is rotated about the axis of rotation (RA) and a second set of sensor signals is received and a second alignment (AL2) of the axis (AX) is determined as the function of the second set of sensor signals. A position (X0, Y0) of the axis of rotation (RA) is determined depending on the first and the second alignment (AL1, AL2).

IPC Classes  ?

• G01D 3/032 - Measuring arrangements with provision for the special purposes referred to in the subgroups of this group mitigating undesired influences, e.g. temperature, pressure affecting incoming signal, e.g. by averagingMeasuring arrangements with provision for the special purposes referred to in the subgroups of this group mitigating undesired influences, e.g. temperature, pressure gating undesired signals
• G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage

Abstract

A semiconductor body (10) comprises a field-effect transistor (11) comprising a drain region (12) of a first conduction type, a source region (13) of the first conduction type, a drift region (16) and a channel region (14) of a second conduction type. The drift region (16) comprises at least two stripes (15, 32) of the first conduction type extending from the drain region (12) in a direction towards the source region (13). The channel region (14) is arranged between the drift region (16) and the source region (13). The transistor comprises a further source region (38), a further drift region (42) comprising at least two further stripes (50, 51) of the first conduction type, extending towards the further source region, and a further channel region (44).

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Goods & Services

(1) Knobs, mice, track balls, digitizer tablets, touch screens, pads and key pads for computers, laptops, mobile phones, mp3, PDAs, GPS receivers, gaming consoles, car control and navigation systems, devices for positioning and determination of positions, namely movement sensors and rotational sensors, joysticks and parts thereof, sensors especially magnetic field sensors, rotary and sliding knobs for computers, laptops, mobile phones, mp3, PDAs, GPS receivers, gaming consoles, car control and navigation systems, navigation key/knob modules for laptops, mobile phones and PDAs; all aforesaid goods especially for mobile communication devices, navigation apparatus and remote controls

Abstract

A circuit arrangement for shifting a voltage level comprises a data/current converter (2) which is connected to a first connection (K1) and which has an input for supplying a digital input data signal (DIN), a first output for providing a current (I) and also a second output for providing a reference current (II), and comprises a current/data converter (3) which is connected to a second connection (K2) and which has a first input for supplying the current (I), a second input for supplying the reference current (II) and also an output for providing a digital output data signal (DOUT). In this case, a voltage level of the digital output data signal (DOUT) differs from a voltage level of the digital input data signal (DIN). A method for shifting a voltage level is also provided.

IPC Classes  ?

• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage

Abstract

A semiconductor element (10) comprises a first region (11) with a number of recesses (17, 20, 23) which extend from a first primary surface (13) of the semiconductor element (10) into a substrate (31) of the semiconductor element (1). In addition the semiconductor element (10) comprises a second region (12) in the first primary surface (13) which is surrounded by the first region (11).

IPC Classes  ?

• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2,...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an input signal at a respective data input (D1, D2) to a respective data output (Q1, Q2) either for a rising clock edge of a clock signal at a respective clock input (Cl, C2) or for a falling clock edge of the clock signal, depending on a control signal at a respective trigger control input (PH1, PH2). Clock inputs (Cl, C2) of the delay elements (FF1, FF2) are coupled to the reference frequency input (FIN). The data input (D1) and the trigger control input (PH1) of the first delay element (FF1) of the cascade are coupled to the data output (Q2, QN) of the last delay element (FF2, FFN) of the cascade. The data input (D2,...) and the trigger control input (PH2,...) of further delay elements (FF2,...) of the cascade are coupled to the data output (Q1,...) of a respective preceding delay element (FF1,...) of the cascade. The clock output (FOUT) is coupled to the data output (Q2,...) of the last delay element (FF2,...) of the cascade. Hereby the trigger control input (PH1,...) of one of the delay elements (FF1,...) of the cascade is coupled to the corresponding data output (QN,... ) by inverting means (INV1,...) and the respective data inputs (D2,...) of the other delay elements (FF2,...) of the cascade are coupled to the corresponding data output (Q1,...) by respective inverting means (INV2,... ).

IPC Classes  ?

• H03K 23/54 - Ring counters, i.e. feedback shift register counters

Abstract

The invention relates to a sacrificial layer provided under a micromechanical layer (2), isotropically etched back to residual portions so that spacers (4) are formed on the top side of a carrier (1) in an intermediate space (3), said spacers comprising a shape tapering toward the micromechanical layer. In this manner, after exposing the micromechanical layer by etching, the micromechanical layer is prevented from adhering to the top side of the carrier.

IPC Classes  ?

• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

The circuit arrangement (1) comprises an input (2) for the connection of an oscillator (3) and an amplifier circuit (20) having a first input (21) that is coupled to the input (1) of the circuit arrangement (1), having a second input (22) and an output (23) that is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty cycle (φ) can be accessed at the output (4) of the circuit arrangement (1). The circuit arrangement (1) furthermore incorporates a low-pass filter (40), the input of which is connected to the output (23) of the amplifier circuit (20), and an integrator circuit (50) the input of which is connected to the low-pass filter (40) and the output of which is connected to the second input (22) of the amplifier circuit (20) for the delivery of an adjustable threshold value (Vth) for controlling the duty cycle (φ).

IPC Classes  ?

• H03K 5/01 - Shaping pulses

Abstract

A circuit arrangement for protection against electrostatic charges comprises a dissipation element (AE) which is connected between a first and a second connection (K1, K2) of the circuit arrangement and has a control input via which the dissipation element (AE) can be conductively controlled. Furthermore, a trigger element (TE) is provided, which has a trigger output for outputting a trigger signal (TR) as a function of a voltage between the first and the second connection (K1, K2) of the circuit arrangement. The circuit arrangement furthermore has an interruption unit (UE) which can be controlled via a deactivation input (K3) by means of a deactivation signal (DIS) that can be supplied, and which interruption unit (UE) is coupled on the input side to the trigger output and on the output side to the control input. A method is also provided for dissipation of electrostatic charges.

IPC Classes  ?

• H03K 17/16 - Modifications for eliminating interference voltages or currents
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields

Abstract

A voltage regulator (10) comprises a first transistor (13) which couples aninput terminal (11) of the voltage regulator (10) to anoutput terminal (12) of the voltage regulator (10) and a second transistor (16). The first and the second transistors (13, 16) form a current mirror structure. Further on,the voltage regulator (10) comprises a control node (17) which is coupled to the input terminal (11) of the voltage regulator (10) via the second transistor (16) and which is coupled to the output terminal (12) of the voltage regulator (10) via a feedback circuit (28).Furthermore, the voltage regulator (10) comprises an amplifier (22) with an input terminal (23) which is coupled to the control node (17) and an output terminal (24) which is coupled to a control terminal (21) of the secondtransistor (16).

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Abstract

The invention relates to a circuit arrangement for protecting from electrostatic discharges, having a discharge structure (ESD1) comprising a discharge element (DE1) and a switchable element (SW1). The discharge element (DE1) is configured to divert an electrostatic discharge between a first and a second connection (K1, K2). The switchable element (SW1) can assume a first and a second switching state, wherein a function of the discharge element (DE1) can be activated as a function of the switching state of the switchable element (SW1).

IPC Classes  ?

• H03K 17/16 - Modifications for eliminating interference voltages or currents
• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts

Abstract

A sensor arrangement for detecting an angle of rotation of a rotating body. At least one first sensor and one second sensor are connected to one another in a cascade in such a manner that the sensor signal from the first sensor is converted into a first control current which is applied as a bias current to the second sensor, the two angular dependencies of the first and second sensors being multiplied. This achieves improved interpolation when determining the angle of rotation on the basis of the sensor signals provided by the sensor arrangement.

IPC Classes  ?

• G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes

Abstract

A DC/DC converter arrangement comprises an input terminal (10) to receive a supply voltage (VIN), an output terminal (12) to provide an output voltage (VOUT) and a switching arrangement (11), comprising a coil (46) and at least two switches (42, 43, 44, 45) to provide a Buck-Boost conversion. The arrangement further comprises a current detection circuit (50) which is coupled to the switching arrangement (11) for sensing a coil current (IL) and a comparator (24), comprising a first input (25) which is coupled to the output terminal (12) and a second input (26) which is coupled to an output (52) of the current detection circuit (50). An output (27) of the comparator (24) is coupled to the switching arrangement (11). Furthermore, the arrangement comprises a ramp generator (60) which is coupled to the first or the second input (25, 26) of the comparator (24).

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

An MEMS microphone is bonded onto the surface of an IC component containing at least one integrated circuit suitable for the conditioning and processing of the electrical signal supplied by the MEMS microphone. The entire component is simple to produce and has a compact and space-saving construction. Production is accomplished in a simple and reliable manner.

IPC Classes  ?

• H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device

Abstract

The through-contact of the substrate is formed by a contact hole filling (4) of a semiconductor layer (11) and a metallization (17) of a cutout (16) in a rear-side semiconductor layer (13), wherein the semiconductor layers are separated from one another by a buried insulation layer (12), at the layer position of which the contact hole filling and the metallization respectively end.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

The invention relates to a circuit configuration for controlling a particularly segmented LED background illumination, comprising a generator (50) having a first input (10) for introducing a synchronization signal (SYNC) comprising image and/or line frequency information of a display unit, a second input (20) for introducing a data signal (DATA) comprising image information of the display unit, and having an output (30) for providing a modulated signal (MOD).

IPC Classes  ?

• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

Abstract

A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.

IPC Classes  ?

• H01L 29/84 - Types of semiconductor device controllable by variation of applied mechanical force, e.g. of pressure

Abstract

In a measurement method, an array of magnetic field sensors (MS0 to MS15) is provided which in each case emit a sensor signal as a function of a magnetic field intensity. A rotation value of a magnetic source, which is magnetized in the form of sectors and is arranged such that it can move with respect to the array, is ascertained as a function of the emitted sensor signals. A set of sensor values is derived from said sensor signals. A number of sets of reference values is ascertained which corresponds to a number of predetermined positions of the magnetic source (MAG) as a function of the ascertained rotation value. The set of sensor values and the number of sets of reference values are compared with each other and a position is selected from the number of predetermined positions as a function of the comparison.

IPC Classes  ?

• G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
• G06F 3/038 - Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

In a sound reproduction device (1), an output terminal (2) to which a sound transducer (3) is attachable, an amplification device (200), and a control device (100) are provided. The amplification device (200) has an output point (210) which is coupled to the output terminal (2). A sound level can be provided by a sound transducer (3) connected to the output terminal (2) in accordance with a specific voltage at the input opening (30, 31, 32) of the sound transducer (3) when the sound reproduction device (1) is in operation. The control device (100) can calibrate an amplification of the amplification device (200) as a function of the dependence of the sound level on the voltage at the input point (30, 31, 32) of the sound transducer (3). For this purpose, the control device (100) has a measuring device (120) with a signal source (130) to provide a source signal and a measuring device (140) for the recording of a measuring signal as a function of the source signal. Both said signal source and said measuring device are coupled to the output terminal (2). The measuring device (120) is set up to determine at least one parameter for the sound transducer (3) in accordance with the measuring signal, from which parameter the dependence of the sound level can be derived from the voltage at the input point (30, 31, 32) of the sound transducer (3).

IPC Classes  ?

• H04R 3/00 - Circuits for transducers
• H04R 3/12 - Circuits for transducers for distributing signals to two or more loudspeakers
• H04R 5/04 - Circuit arrangements
• H04R 29/00 - Monitoring arrangementsTesting arrangements
• A61F 11/14 - Protective devices for the ears external, e.g. earcaps or earmuffs
• H03F 1/56 - Modifications of input or output impedances, not otherwise provided for