Abstract

A capacitor wafer is provided. The capacitor wafer includes a plurality of capacitor devices. Each of the capacitor devices includes a capacitor structure disposed in the capacitor wafer and a plurality of scribe lines at a surface of the capacitor wafer. The capacitor structure includes a first metal line of a top metal line layer extending horizontally over the capacitor structure; a seal ring structure surrounding the capacitor structure; and an interlayer dielectric (ILD) disposed over and surrounding the capacitor structure and the seal ring structure. The scribe lines define the capacitor devices from each other. A top surface of the seal ring structure is entirely covered by the ILD. A top surface of the first metal line is free from being entirely covered by the ILD. A method for forming the capacitor wafer is also provided.

IPC Classes  ?

• H01G 4/252 - Terminals the terminals being coated on the capacitive element
• H01G 4/30 - Stacked capacitors
• H01G 4/33 - Thin- or thick-film capacitors
• H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors

Goods & Services

Computer memories; Computer memory devices; Computer memory cassette; random access memory; RAM (random access memory) module; RAM (random access memory) card; Blank flash memory cards; Read-only memory chip; Memory cards [computer hardware]; Silicon chips; Semiconductors; Integrated circuits; Semiconductor chips Design of integrated circuits; Design of semiconductor chips; Design of computer chips; Technical research in the field of integrated circuits, semiconductors, chips, random access memory; conducting technical project studies in the field of integrated circuits, semiconductors, chips, random access memory; Research and development of new products; Product research and development; Inspection of integrated circuits, semiconductors, chips, random access memory for quality control purposes; Technical advice relating to operation of computers; information technology [IT] support services [troubleshooting of software]

Goods & Services

Computer memories; Computer memory devices; Computer memory cassette; random access memory; RAM (random access memory) module; RAM (random access memory) card; Blank flash memory cards; Read-only memory chip; Memory cards [computer hardware]; Silicon chips; Semiconductors; Integrated circuits; Semiconductor chips Design of integrated circuits; Design of semiconductor chips; Design of computer chips; Technical research in the field of integrated circuits, semiconductors, chips, random access memory; conducting technical project studies in the field of integrated circuits, semiconductors, chips, random access memory; Research and development of new products; Product research and development; Inspection of integrated circuits, semiconductors, chips, random access memory for quality control purposes; Technical advice relating to operation of computers; information technology [IT] support services [troubleshooting of software]

Goods & Services

Computer memories; Computer memory devices; Computer memory cassette; random access memory; RAM (random access memory) module; RAM (random access memory) card; Blank flash memory cards; Read-only memory chip; Memory cards [computer hardware]; Silicon chips; Semiconductors; Integrated circuits; Semiconductor chips Design of integrated circuits; Design of semiconductor chips; Design of computer chips; Technical research in the field of integrated circuits, semiconductors, chips, random access memory; conducting technical project studies in the field of integrated circuits, semiconductors, chips, random access memory; Research and development of new products; Product research and development; Inspection of integrated circuits, semiconductors, chips, random access memory for quality control purposes; Technical advice relating to operation of computers; information technology [IT] support services [troubleshooting of software]

Goods & Services

Capacitors; Silicon Capacitor; Computer memories; Computer memory devices; Computer memory cassette; random access memory; RAM (random access memory) module; RAM (random access memory) card; Blank flash memory cards; Read-only memory chip; Memory cards [computer hardware]; Silicon chips; Semiconductors; Integrated circuits; Semiconductor chips Design of integrated circuits; Design of semiconductor chips; Design of computer chips; Technical research in the field of integrated circuits, semiconductors, chips, random access memory, and silicon capacitors; conducting technical project studies in the field of integrated circuits, semiconductors, chips, random access memory, and silicon capacitors; Research and development of new products; Product research and development; Inspection of integrated circuits, semiconductors, chips, random access memory, and silicon capacitors for quality control purposes; Technical advice relating to operation of computers; information technology [IT] support services [troubleshooting of software]

Abstract

A semiconductor device includes a first stacking pair and a connecting unit. The first stacking pair comprises a first repeating unit and a second repeating unit. The first repeating unit comprises a first dielectric layer, a first device surrounded by the first dielectric layer, and a first interconnect structure comprising a first metal layer over the first device and surrounded by the first dielectric layer, the first metal layer electrically coupled to the first device. The second repeating unit comprises a second dielectric layer, a second interconnect structure comprising a second metal layer bonded to the first metal layer, and a second device surrounded by the second dielectric layer and electrically coupled to the second metal layer. The connecting unit comprises a contact pad electrically coupled to the first metal layer and the second metal layer. A method of manufacturing the semiconductor structure is also disclosed.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A programming method of a DRAM (dynamic random-access memory)-based one time programming (OTP) memory device is provided. A selected word line (WL) of a selected page is turned on. A sensing circuit is turned on to sense a first data set in the selected page into the sensing circuit. A cell plate voltage (VPLT) is set to a high voltage and the selected page is programmed. The VPLT is lowered, and the selected WL of the selected page is turned off.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A dynamic random-access memory (DRAM)-based one time programming (OTP) memory device includes: at least one memory bank comprising a plurality of memory array tiles (MATs) arranged in a matrix. Each of the plurality of MATs includes: a plurality of word lines extending along a row direction; a plurality of bit lines extending along a column direction; and a plurality of memory cells located on corresponding cross points of the plurality of word lines and the plurality of bit lines, each of the plurality of memory cells comprising a capacitor node. The capacitor nodes of the plurality of memory cells along the column direction in the memory bank are divided into a plurality of capacitor node segments, wherein at least two of the plurality of capacitor node segments are separately controllable.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A semiconductor device includes a semiconductor wafer, an antenna element and a radio frequency (RF) transponder. The semiconductor wafer includes a plurality of regions. Each region includes one or more dies. The antenna element is disposed in one of the regions where a device under test (DUT) is disposed. The antenna element is arranged to couple an RF signal into an electrical signal. The RF transponder is disposed in the one of the regions, and coupled to the antenna element and the DUT. The RF transponder is configured to send a stimulus signal to the DUT in response to the electrical signal, and drive the antenna element to output a modulated RF signal according to a response signal received from the DUT. The response signal is generated from the DUT in response to the stimulus signal. The modulated RF signal is indicative of a behavior of the DUT.

IPC Classes  ?

• G01R 31/265 - Contactless testing
• G01R 31/319 - Tester hardware, i.e. output processing circuits
• H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
• H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A device package includes a first tier, a second tier stacked upon the first tier, and a through tier via unitarily penetrating through the first and second tiers. The first tier includes a first device and a first interconnect structure electrically coupled to the first device, the first interconnect structure includes a first metal layer, and the first metal layer includes a first connection branch. The second tier includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure includes a second metal layer, and the second metal layer includes a second connection branch. The through tier via is electrically coupled to the first and second connection branches.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips

Abstract

A memory device includes sets of bitlines, a column selection circuit, and a set of data lines including a first data line and a second data line. The sets of bitlines includes a first set of bitlines and a second set of bitlines. Each data line includes line segments disposed along an extension direction. The column selection circuit couples between the sets of bitlines and the set of data lines. The column selection circuit selectively couples a first bitline in the first set of bitlines and a first bitline in the second set of bitlines to a first line segment and second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to a first line segment of the second data line.

IPC Classes  ?

• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A semiconductor device and a semiconductor package comprising the semiconductor device are provided. The semiconductor device comprises a first semiconductor die having a front side and a backside opposite to the front side and comprising first active components disposed adjacent to the front side of the first semiconductor die. The semiconductor device also comprises a second semiconductor die having a first side bonded to the backside of the first semiconductor die and a second side opposite to the first side. The second semiconductor die comprises passive components that are configured to manage a power delivery to the first semiconductor die.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H10D 1/20 - Inductors

Abstract

A memory device includes a first bit line set, a first column selection circuit, a first data line and a second data line. The first bit line set includes a first bit line and a second bit line. The first column selection circuit is coupled to the first bit line and the second bit line. The first data line includes a first line segment coupled to the first column selection circuit. The second data line includes a second line segment coupled to the first column selection circuit. Wherein the first column selection circuit is configured to electrically connect the first bit line to the first line segment for transmitting a first bit of normal data to the first line segment, and to electrically connect the second bit line to the second line segment for transmitting a first bit of Error Correction/Detection data to the second line segment.

IPC Classes  ?

• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

Provided is a semiconductor package structure including a carrier, a first chip, a second chip, a plurality of bonding wires, and a plurality of first bumps. The first chip is disposed on the carrier. The second chip is disposed on the first chip. The plurality of bonding wires is arranged to electrically connect the first chip and the carrier. The plurality of first bumps is arranged to electrically connect the second chip and the first chip. The plurality of first bumps is sandwiched between the second chip and the first chip.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A capacitor structure is provided. The capacitor structure includes a substrate, a plurality of capacitor cells, a first cell plate, a plurality of second cell plates, and a plurality of vias. The plurality of capacitor cells are formed upon the substrate. The first cell plate is disposed between the substrate and the plurality of capacitor cells, and the plurality of second cell plates are disposed on the plurality of capacitor cells respectively. The vias are disposed on the second cell plates. The plurality of capacitor cells are connected in series.

IPC Classes  ?

• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
• H01L 23/498 - Leads on insulating substrates
• H01L 23/528 - Layout of the interconnection structure

Abstract

A semiconductor structure including a semiconductor die, a component layer and a pseudo static random access memory (PSRAM) die is provided. The component layer is disposed on the surface of the semiconductor die, wherein the component layer includes an organic layer. The PSRAM die is disposed on the surface of the semiconductor die and is electrically connected to the semiconductor die. A manufacturing method of a semiconductor structure is also provided.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

The present application discloses a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a first dielectric, a first redistribution layer (RDL) disposed on a first surface of the first dielectric, a first bonding layer disposed on the first RDL, a plurality of bottom dies attached to the first bonding layer, a second dielectric filling gaps between the bottom dies, a plurality of conductive pillars disposed in the second dielectric without contacting the bottom dies, a second RDL disposed on the second dielectric and the bottom dies, a second bonding layer disposed on the second RDL, a plurality of top dies attached to the second bonding layer, a third dielectric filling gaps between the top dies, and a plurality of solder bumps disposed on a second surface of the first dielectric.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A capacitor device includes: a substrate; a stack capacitor and an interconnect structure. The stack capacitor is disposed on the substrate. The interconnect structure, disposed on the stack capacitor, has an exposed conductive layer configured to have a first conductive pad and a second conductive pad. The first conductive pad is electrically connected to a first electrode of the stack capacitor and the second conductive pad is electrically connected to a second electrode of the stack capacitor.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

The present application discloses a vertical semiconductor RFID structure. The vertical semiconductor RFID structure comprises a semiconductor RFID structure, a tag IC layer, a first conductive layer, and a second conductive layer. The tag IC layer is formed on a front side of the semiconductor substrate. The first conductive layer formed over a back side of the semiconductor substrate opposite to the front side, and the second conductive layer formed over a side of the tag IC layer that is distal to the semiconductor substrate, so that the tag IC layer and the semiconductor substrate are sandwiched between the first conductive layer and the second conductive layer. The second conductive layer is electrically coupled to the tag IC layer.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

The present application discloses a semiconductor device. The semiconductor device includes a memory stacking pair. The memory stacking pair includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. The first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side.

IPC Classes  ?

• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A package substrate includes a first dielectric layer, a second dielectric layer and a core layer. The first dielectric layer includes first electrical interconnect. The second dielectric layer includes second electrical interconnect. The core layer is situated between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above another between the first dielectric layer and the second dielectric layer. A first semiconductor die of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A stitching method for an exposure process includes following steps. A wafer is provided. The wafer includes interposer regions, each of which includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first and second memory chip regions. A photoresist layer is formed on the wafer. First exposure processes are performed on the photoresist layer by applying a first photomask to form first shot regions in the photoresist layer. Second exposure processes are performed on the photoresist layer by applying a second photomask to form second shot regions in the photoresist layer. The first shot regions and the second shot regions are arranged alternately in a first direction. The first shot regions and the second shot regions are overlapped to form stitching regions, each of which is not located in the logic chip region.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G03F 1/42 - Alignment or registration features, e.g. alignment marks on the mask substrates

Abstract

A capacitor device is provided. The capacitor device includes a capacitor structure, a conductive line, an interlayer dielectric (ILD) and a first via conductor. The capacitor structure includes a lower electrode and an upper electrode. The conductive line is leveled with the lower electrode and electrically isolated from the lower electrode. The ILD is disposed over the capacitor structure and the conductive line. The first via conductor is adjacent to the capacitor structure and electrically coupled to the conductive line. A method for manufacturing a capacitor die is also provided.

IPC Classes  ?

• H01G 4/33 - Thin- or thick-film capacitors
• H01G 4/252 - Terminals the terminals being coated on the capacitive element
• H01G 4/30 - Stacked capacitors
• H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A semiconductor package includes a plurality of integrated circuit (IC) substrates and a conductive structure. The IC substrates are stacked one above another. The conductive structure penetrates through the IC substrates. Each of the IC substrates includes an identification circuit coupled to the conductive structure. Each identification circuit is configured to identify a corresponding IC substrate by receiving an input signal from the conductive structure and accordingly generating an identifier of the corresponding IC substrate.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 15/04 - Voltage dividers
• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A semiconductor device includes a first substrate and a second substrate. The first substrate has a plurality of first-type transistors formed of planar-type transistors or fin-type transistors, wherein a gate silicon oxide layer of each of the planar-type transistors has a first thickness, and a gate silicon oxide layer of each of the fin-type transistors has a second thickness. The second substrate is bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors, wherein a gate silicon oxide layer of each of the GAA transistors has a third thickness. The third thickness is less than the first thickness or the second thickness.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor structure, a dielectric bonding structure, a second semiconductor structure, and a through via structure. The first semiconductor structure includes a first substrate and a first back-end-of-line (BEOL) structure over the first substrate. The dielectric bonding structure is over the first semiconductor structure. The second semiconductor structure is over the dielectric bonding structure. The second semiconductor structure includes a second BEOL structure over the dielectric bonding structure and a second substrate over the second BEOL structure. The through via structure penetrates the second semiconductor structure and the dielectric bonding structure to connect the first BEOL structure and the second BEOL structure. A method for forming a semiconductor package structure is also provided.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
• G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/419 - Read-write [R-W] circuits

Abstract

A memory device includes a plurality of sets of bitlines, a set of data lines and a column selection circuit. Each data line is segmented into line segments separated from each other. A first data line includes a first line segment and a second line segment adjacent to each other. A second data line includes a first line segment. The column selection circuit is configured to selectively a first bitline in a first set of bitlines and a first bitline in a second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line.

IPC Classes  ?

• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution structure, a SoC structure, a memory structure, a first electronic component, and a first encapsulation layer. The first redistribution structure has a first side and a second side opposite to the first side. The SoC structure is on the first side of the first redistribution structure. The memory structure is adjacent to the SoC structure and on the first side of the first redistribution structure. The first electronic component is on the second side of the first redistribution structure and electrically connected to at least one of the SoC structure or the memory structure. The first encapsulation layer encapsulates the first electronic component. The first electronic component includes a semiconductor capacitor structure or a voltage converter.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/15 - Ceramic or glass substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A memory device includes one or more memory blocks. Each memory block includes a plurality of first sense amplifier circuits, a plurality of row segments, and a plurality of row decoders. The row segments and the first sense amplifier circuits are arranged alternately along a first direction. Each row segment includes a plurality of memory cells arranged in rows and columns. Each column of memory cells extends in the first direction. The row segments are divided into N groups of row segments, and N is greater than one. The row decoders are coupled to the row segments respectively, and divided into N groups of row decoders.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 11/408 - Address circuits
• G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A method for manufacturing a plurality of semiconductor structures is provided. The method includes the operations as follows. A first hybrid bonding layer is formed over a first wafer including a plurality of first memory structures. A second hybrid bonding layer is formed over a second wafer including a plurality of control circuit structures. The memory structures and the control circuit structures are in contact with the first and the second hybrid bonding layers, respectively. The first wafer and the second wafer are bonded through a first hybrid bonding operation to connect the first and the second hybrid bonding layers, thereby obtaining a first bonded wafer. At least the first wafer, the second wafer, the first hybrid bonding structure, and the second hybrid bonding structure are singulated to obtain the plurality of semiconductor structures. A method for manufacturing a system in package (SiP) is also provided.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.

IPC Classes  ?

• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements

Abstract

A capacitor structure is provided. The capacitor structure includes a substrate, a middle-of-line (MEOL) structure, and a metallization structure. The substrate has a first surface and a second surface opposite to the first surface. The MEOL structure is over the first surface of the substrate. The MEOL structure includes a capacitor, and the capacitor includes a bottom plate and a top plate over the bottom metal plate. The metallization structure is over the MEOL structure. The substrate further includes a plurality of first through vias extending from the second surface of the substrate to the bottom metal plate. The semiconductor structure including the capacitor structure and the method for manufacturing the semiconductor structure are also provided.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 49/02 - Thin-film or thick-film devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A memory device includes a memory die, a non-volatile memory circuit, and a logic die. The memory die includes a first memory space and a second memory space. The non-volatile memory circuit stores a repair table file corresponding to the first memory space. The logic die is coupled to the memory die and the non-volatile memory. The logic die selectively accesses the first memory space or the second memory space of the memory die according a comparing result of an input address and the repair table file. The memory die and is different from the logic die.

IPC Classes  ?

• G11C 29/44 - Indication or identification of errors, e.g. for repair
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware
• G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

IPC Classes  ?

• G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
• G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
• G11C 11/4076 - Timing circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/419 - Read-write [R-W] circuits

Abstract

An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/419 - Read-write [R-W] circuits
• G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
• G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Abstract

A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

IPC Classes  ?

• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A DRAM chiplet structure is provided. The DRAM chiplet structure includes a first hybrid bonding structure, a DRAM interface structure, and a first DRAM core structure. The first hybrid bonding structure has a first surface and a second surface. The DRAM interface structure is in contact with the first surface of the first hybrid bonding structure. The first DRAM core structure is in contact with the second surface of the first hybrid bonding structure. The DRAM interface structure is electrically connected to the first DRAM core structure through the first hybrid bonding structure.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/528 - Layout of the interconnection structure
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• G11C 11/409 - Read-write [R-W] circuits

Abstract

An interposer structure is provided. The interposer structure includes a plurality of interposer units in an array arrangement from a top view perspective. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the plurality of second regions is free of the capacitor structure. The first region surrounds the plurality of second regions. A method for manufacturing an interposer structure is also provided.

IPC Classes  ?

• H01L 49/02 - Thin-film or thick-film devices
• H01G 4/012 - Form of non-self-supporting electrodes
• H01G 4/228 - Terminals
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 27/108 - Dynamic random access memory structures

Abstract

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices

Goods & Services

Memory, namely, semiconductor memory chips; RAM (Random Access Memory) cards; Read-only memory integrated circuit chips; Integrated circuits; Semi-conductors

Goods & Services

Information technology consultancy services in the field of design of semiconductor chips and design of integrated circuits; Design of semiconductor chips; Design of integrated circuits

Abstract

A memory cell includes: a latch, powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a first connecting terminal and a second connecting terminal; a first programmable fuse, having a first terminal coupled to the first connecting terminal and a second terminal coupled to the second reference voltage; and a second programmable fuse, having a first terminal coupled to the second connecting terminal and a second terminal coupled to the second reference voltage.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/14 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory

Abstract

A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.

IPC Classes  ?

• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

IPC Classes  ?

• H01L 29/40 - Electrodes
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 27/108 - Dynamic random access memory structures
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements

Abstract

The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• H03K 19/0175 - Coupling arrangementsInterface arrangements
• H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/108 - Dynamic random access memory structures
• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers. The first and second semiconductor portions are stacked vertically with one another, so that the first conductive contacts are electrically connected to the control circuit, and the first conductive contacts in combinations with the first conductive vias form a plurality of transmission channels.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 23/66 - High-frequency adaptations
• H01L 49/02 - Thin-film or thick-film devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/64 - Impedance arrangements

Abstract

In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102). The cell terminals (104) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the cell terminals (103), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the cell terminals (103).

IPC Classes  ?

• H01L 49/02 - Thin-film or thick-film devices
• H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
• H01L 21/283 - Deposition of conductive or insulating materials for electrodes
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 27/108 - Dynamic random access memory structures