Cogniscience Limited

United Kingdom

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2023 1
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IPC Class
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units 1
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal 1
G06N 3/04 - Architecture, e.g. interconnection topology 1
H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] 1
H04L 12/56 - Packet switching systems 1
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Found results for  patents

1.

On chip router

      
Application Number 17997085
Grant Number 12010033
Status In Force
Filing Date 2021-04-26
First Publication Date 2023-06-29
Grant Date 2024-06-11
Owner COGNISCIENCE LIMITED (United Kingdom)
Inventor
  • Furber, Steve
  • Liu, Gengting

Abstract

There is disclosed a router for routing data on a computing chip comprising a plurality of processing elements, the router comprising: a packet processing pipeline; a dropped packet buffer; and one or more circuits configured to: determine that a data packet in the packet processing pipeline is to be dropped; move the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer; and re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing.

IPC Classes  ?

  • H04L 47/32 - Flow controlCongestion control by discarding or delaying data units, e.g. packets or frames
  • H04L 47/129 - Avoiding congestionRecovering from congestion at the destination endpoint, e.g. reservation of terminal resources or buffer space
  • H04L 49/90 - Buffering arrangements

2.

ON CHIP ROUTER

      
Application Number GB2021051009
Publication Number 2021/219985
Status In Force
Filing Date 2021-04-26
Publication Date 2021-11-04
Owner COGNISCIENCE LIMITED (United Kingdom)
Inventor
  • Furber, Steve
  • Liu, Gengting

Abstract

There is disclosed a router for routing data on a computing chip comprising a plurality of processing elements, the router comprising: a packet processing pipeline; a dropped packet buffer; and one or more circuits configured to: determine that a data packet in the packet processing pipeline is to be dropped; move the data packet that is to be dropped from the packet processing pipeline to the dropped packet buffer; and re-insert the dropped data packet from the dropped packet buffer into the packet processing pipeline for re-processing.

IPC Classes  ?

  • H04L 12/823 - Packet dropping
  • H04L 12/861 - Packet buffering or queuing arrangements; Queue scheduling
  • H04L 12/835 - Bitrate adaptation in active flows using buffer capacity information at the endpoints or transit nodes
  • G06N 3/04 - Architecture, e.g. interconnection topology

3.

Data transmission method

      
Application Number 12094901
Grant Number 08289971
Status In Force
Filing Date 2006-11-21
First Publication Date 2008-10-30
Grant Date 2012-10-16
Owner Cogniscience Limited (United Kingdom)
Inventor Furber, Stephen Byram

Abstract

A method of transmitting data between a plurality of inter-connected elements. The method comprises receiving a message from a first element, said message comprising a routing key plus optionally a data payload. The routing key is processed to identify a plurality of said inter-connected elements, and data is transmitted to said identified plurality of inter-connected elements.

IPC Classes  ?

  • H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L 12/56 - Packet switching systems
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal