Abstract

A device in communication with a plurality of memory devices storing a plurality of datasets and a host, the device including one or more circuits to receive a plurality of messages pertaining to the plurality of datasets, determine an amount of information corresponding to each dataset of the plurality of datasets, identify actions for each message of the plurality of messages, the actions including at least one of updates to the plurality of datasets or accesses of the plurality of datasets, update a table to reflect receipt of the plurality of messages, and determine a pattern associated with the plurality of messages.

IPC Classes  ?

• G06F 9/54 - Interprogram communication

Abstract

Novel communication techniques for Bluetooth LE devices. In some cases, a central device transmits broadcast messages, which can be received by one or more peripheral devices, which then transmit responses in turn. In an aspect, these techniques can condense multiple advertising/scan request/scan response packets into a single transmission window and/or multiple, contiguous receive windows for the central device and single transmit/single receive windows for each peripheral device.

IPC Classes  ?

• H04W 72/30 - Resource management for broadcast services
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 12/041 - Key generation or derivation

Abstract

In some embodiments, the method for scaling to a super resolution based on machine learning is provided. The method may include receiving a data stream. The device may include circuitry to upscale media by a scale factor to a super resolution. The circuitry can be configured with a number of one or more multipliers and adders for one or more neurons of one or more layers of a neural network. The number of one or more multipliers and adders can be determined based at least on the scale factor. The method may include determining a plurality of output data points corresponding to the one or more data points upscaled by the scale factor to the super resolution. The method may include providing as output the super resolution of the media. The method may further include identifying one or more features of one or more data points from the data stream.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

A power amplifier is provided. The power amplifier includes a first circuit comprising a first transistor and a second transistor coupled respectively to a third transistor and a fourth transistor. The power amplifier also includes a second circuit comprising a transformer having a first winding and a second winding. The first winding comprises a first terminal coupled to the third transistor and a second terminal coupled to the fourth transistor to receive a differential voltage signal with a gain from the first circuit. The second winding comprises a first terminal being grounded and a second terminal serving as an output terminal. The power amplifier circuit further includes a third circuit comprising a programmable capacitor from a midpoint of the first winding to a common node that is coupled to ground. The programmable capacitor is tunable to reduce second harmonic seen at the output terminal.

IPC Classes  ?

• H03F 1/42 - Modifications of amplifiers to extend the bandwidth
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Abstract

Techniques for performing automatic PHY updates in Bluetooth devices. In some cases, a device might detect the reception of a packet sent with a particular PHY and automatically update the device's physical layer to employ that PHY for receiving and/or transmitting subsequent packets.

IPC Classes  ?

• H04W 76/14 - Direct-mode setup
• H04W 76/15 - Setup of multiple wireless link connections

Abstract

The systems and methods described provide a solution for automatic training of echo canceller (EC) in upstream signal receivers on sub-carriers experiencing low activity in the upstream communication. The solution can include one or more processors identifying a plurality of bins (e.g., EC bins). Each bin of the plurality of bins can correspond to a portion of a frequency range of a cable line. The one or more processors can determine that a power level of an echo signal of each of a bin of the plurality of bins and one or more bins adjacent to the bin exceed a respective threshold for the power level. The one or more processors can train an echo canceller of the echo signal for the bin, responsive to the determining.

IPC Classes  ?

• H04B 3/23 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
• H03H 21/00 - Adaptive networks

Abstract

A wireless device can include a first radio configured to transmit over a first link and a second link of a first wireless band. The first radio can be configured to detect an OBSS communication on the first link of the first wireless band. The wireless device can perform coordinated link-switch (CLS) operations. The wireless device can be configured to operate as an access point (AP) for one or more stations of a wireless network or a station.

IPC Classes  ?

• H04W 36/08 - Reselecting an access point
• H04W 36/30 - Reselection being triggered by specific parameters by measured or perceived connection quality data
• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance

Abstract

A device including one or more circuits. The one or more circuits can receive a request associated with a first dataset stored by a memory device of a plurality of memory devices. The one or more circuits can generate, based on information associated with the memory device and the request, a first value corresponding to a first portion of a first map. The one or more circuits can determine, based on a first value of the first portion of the first map, that a first row of the plurality of rows includes a bad block.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Methods, systems, and devices for improving security of media streams are disclosed. The system can receive a decoded media stream from a media decoding pipeline that receives and decodes an encoded media stream. The system can identify, based on the decoded media stream, a set of features to generate, and generate the set of features using the decoded media stream. Such features may include luma histograms, pixel intensity data, motion vectors, edge detection, audio gain, tonal information, pitch information, among other types of features. The system can provide the set of features to a processor executing a machine-learning model, wherein the processor executing the machine-learning model is prevented from accessing the decoded media stream by the device.

IPC Classes  ?

• H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
• G06N 20/00 - Machine learning
• H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
• H04N 19/517 - Processing of motion vectors by encoding
• H04N 21/439 - Processing of audio elementary streams

Abstract

A method for improving wafer-level optical characteristic uniformity. The method includes forming a first layer of dielectric overlying the first wafer and a second layer of dielectric overlying the second wafer. The method also includes measuring a refractive index distribution of the second layer and measuring a first thickness distribution of the first layer. The method also includes determining a second thickness distribution for the first layer based on the refractive index distribution and the first thickness distribution. The method further includes removing material nonuniformly and selectively from the first layer based on the second thickness distribution, resulting in a third layer in the second thickness distribution characterized by a spectral response with a characteristic wavelength uniformity better than +/−2.5 nm across the first wafer.

IPC Classes  ?

• G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films

Abstract

A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Method and structure for shielding electromagnetic interference in photonic integrated circuits (PIC) disposed on electronic integrated circuits (EIC). The invention addresses the electromagnetic interference problem by employing vias through the PIC's bulk silicon substrate. The invention also uses a conductive layer covering the backside of the PIC bulk silicon substrate on which the metal heat spreader can be placed. Now, the vias can make electrical contact from the reference net formed for PIC's light transmission component on one or more metal layers of the PIC to the conductive layer on the backside of the PIC. Such an arrangement allows for robust electrical connection and allows the metal heat spreader to act as robust ground thus terminating the electromagnetic fields.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop/interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop/interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

A signal integrity optimized package is provided. An apparatus includes a core comprising a top surface, bottom surface, and a first plane coupled to the top surface of the core. The first plane includes a first region circumscribed by a first ditch, wherein the first region includes an electrically conductive material, and wherein the first ditch is configured to electrically isolate the first region.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

Novel tools and techniques for packet filtering in a network. A networking device might feature an access control list (ACL) with filter rules, each having a field to identify, for example, a possible state of a vehicle. Based on this field, rules inapplicable to that state can be disregarded when evaluating packets against the rules in the ACL.

IPC Classes  ?

• H04L 9/40 - Network security protocols

Abstract

The subject technology is directed to semiconductor devices and manufacturing methods. In various embodiments, the subject technology provides a semiconductor device, which comprises a first circuit characterized by a first coefficient of thermal expansion (CTE) and a substrate characterized by a second CTE. A ratio of the first CTE to the second CTE is greater than or equal to 3:5, which ensures harmonious thermal behavior, leading to improved yield and reduced warpage. In some implementations, one or more circuit elements may be embedded in the substrate. There are other embodiments as well.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 2/3 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 192 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

The subject technology is directed to semiconductor devices and manufacturing methods. In various embodiments, the subject technology provides a method for manufacturing a semiconductor device, which comprises forming a substrate and coupling a first circuit to the substrate. The first circuit is characterized by a first coefficient of thermal expansion (CTE) and the substrate is characterized by a second CTE. A ratio of the first CTE to the second CTE is greater than or equal to 3:5, which ensures harmonious thermal behavior, leading to improved yield and reduced warpage. In some implementations, one or more circuit elements may be embedded in the substrate. There are other embodiments as well.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A device may include a plurality of processors coupled to one or more network interfaces configured to provide wireless connectivity, and a controller. The controller may be configured to establish a wireless connection via a first processor of the plurality of processors. Responsive to a trigger of the first processor scanning for one or more channels, the controller may be configured to transfer the established wireless connection from the first processor to a second processor of the plurality of processors. The second process is different from the first processor. Responsive to the second processor detecting data to be received from the established wireless connection, the controller may be configured to transfer the established wireless connection from the second processor back to the first processor.

IPC Classes  ?

• H04W 76/15 - Setup of multiple wireless link connections
• H04W 76/20 - Manipulation of established connections

Abstract

A resonator for beat mode suppression is provided. A resonator includes a substrate comprising a top surface, a bottom electrode disposed on the top surface of the substrate, a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The bottom electrode includes a first elongated member configured to extend longitudinally along the top surface on a first side of the substrate.

IPC Classes  ?

• H03H 9/205 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

Operations of a security device are provided herein. The operations may include receiving, via a first network interface, a network packet, and evaluating attributes of the received network packet against a ruleset to identify a first rule match, wherein the attributes comprise an identifier of the first network interface, a source address, and a destination address. The operations may further include comparing the attributes of the received network packet against a table listing one or more network devices associated with the first network interface or a second network interface. The operations may further include switching the attributes of the received network packet by changing the identifier of the first network interface to an identifier of the second network interface and swapping the source address and the destination address, and evaluating the switched attributes of the received network packet against the ruleset to identify a second rule match. The switched attributes of the received network packet may be compared against the table, and one of the first rule match or the second rule match may be selected based on the comparisons of the network packet attributes and the switched network packet attributes against the table. The received network packet may be processed according to the selected one of the first rule match or the second rule match.

IPC Classes  ?

• H04L 9/40 - Network security protocols

Abstract

The subject technology is directed to encoder systems and methods. According to an embodiment, the subject technology provides a magnetic encoder that comprises a first magnet and a second magnet. The first magnet comprises a first pole pair and an opening. The second magnet comprises a second pole pair and is positioned inside the opening. The magnetic encoder further comprises a first sensor that is configured to detect and generate a first signal based on the magnetic flux orientation of the first magnet and a second sensor that is configured to detect and generate a second signal based on the magnetic flux orientation of the second magnet. To achieve this feat, the first magnet and second magnet are magnetized in two separate types of magnetization (e.g., diametrical or axial magnetization) to generate two separate types of magnetic flux orientations that could be detected via the two types of magnetic sensors.

IPC Classes  ?

• G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage

Abstract

A solution for regulating a voltage for a broad range of integrated circuits (ICs) using a plurality of switch capacitor voltage regulator circuits is disclosed. A system can include a plurality of circuits configured to provide a voltage output responsive to a voltage input. Each circuit can include a plurality of switches and one or more capacitors and can be coupled in parallel with each of other circuits of the plurality of circuits, so that an input of each circuit is coupled to the voltage input and an output of each circuit is coupled to the voltage output. The plurality of switches of each circuit can be configured to switch on and off at a phase that is different from a phase of at least one another plurality of switches of another circuit of the plurality of circuits.

IPC Classes  ?

• H02M 1/14 - Arrangements for reducing ripples from DC input or output
• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

Abstract

An area-efficient LDMOS FinFET is provided. An apparatus includes a substrate having a first doping, the substrate comprising a first well having a second doping, and a second well having a third doping, and a fin disposed on the substrate. The fin is positioned over the first well and extends, at least in part, over the second well. The fin includes a first doped region disposed on the first well and having a doping lighter than the second doping, and a second doped region disposed on the first well having the third doping.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A device including a first circuit, a second circuit, and a third circuit. The first circuit to receive a first signal and a second signal, and the first circuit to provide a third signal. The second circuit to receive a fourth signal and a fifth signal, and the second circuit to provide a sixth signal. The third circuit to receive the third signal and the sixth signal, and the third circuit to provide a seventh signal to indicate whether to track a difference between an amount of voltage provide to a driver and an amount of voltage provided by the driver or track a difference between an amount of voltage provided by a source and the amount of voltage provided to the driver.

IPC Classes  ?

• H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A device including a first circuit, a second circuit. The first circuit to receive a first signal, a second signal, and a third signal, and the first circuit to provide a fourth signal and a fifth signal. The second circuit to receive the fourth signal and the fifth signal, and the second circuit to control a first set of components to maintain a difference between a first amount of power provided to a first terminal of a driver and a second amount of power provided to a second terminal of the driver or to control a second set of components to maintain the difference between the first amount of power provided to the first terminal of the driver and the second amount of power provided to the second terminal of the driver.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
• H03K 17/30 - Modifications for providing a predetermined threshold before switching

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a stiffener member with a via. In various embodiments, an apparatus includes a substrate and a connector electrically coupled to the substrate. A stiffener member is disposed between the substrate and the connector and configured to restrain at least one of the substrate or the connector. A via extends through a body of the stiffener member and electrically couples the connector to the substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H05K 1/02 - Printed circuits Details

Abstract

Novel semiconductors and fabrication techniques are provided. In various embodiments, a semiconductor includes a source, a drain, a first gate, a second gate, and a channel. The second gate is electrically coupled to the first gate. The first gate and the second gate are configured to control current between the source and the drain. The channel is in contact with the first gate and the second gate. The channel is configured such that the current flows through the channel. Other aspects, embodiments, and features are also claimed and described.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03M 1/66 - Digital/analogue converters

Abstract

A semiconductor device, such as a fin field-effect transistor (FinFET), that can provide advantages in terms of electrostatic discharge protection. The semiconductor device includes a fin with an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region. The semiconductor device further includes a gate disposed on the undoped region of the fin, a silicide layer disposed on the third doped region, and an interconnect disposed on the silicide layer to form a drain.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

Systems and methods use a protocol for a secure probe exchange Some embodiments relate to a first device. The first device includes a circuit configured to provide at least one frame across a connection to a second device in response to an unprotected broadcast probe request message. The frame includes an unprotected unicast probe request message. An unprotected broadcast probe request message may refer to a broadcast message (e.g., a management frame) that requests a response and is not encrypted in some embodiments.

IPC Classes  ?

• H04W 12/06 - Authentication
• H04W 76/10 - Connection setup

Abstract

Systems and methods use a protocol for a secure reassociation exchange. A first device can be used in the exchange and includes a circuit configured to provide at least one frame to a second device. The frame includes comprises a protected reassociation request message. Alternatively, frame can include a protected reassociation response message.

IPC Classes  ?

• H04W 12/037 - Protecting confidentiality, e.g. by encryption of the control plane, e.g. signalling traffic
• H04W 12/08 - Access security
• H04W 76/19 - Connection re-establishment

Abstract

A system may include one or more processors configured to receive a write operation to write a block of data to a logical device established using one or more storage devices which reserve one or more data strips and one or more metadata blocks to store data of write journals. The one or more processors may identify a first data strip of the block of data to be written to a first storage device of the one or more storage devices, write a copy of the first data strip to a data strip of the one or more data strips reserved on the first storage device, write metadata relating to the block of data to a metadata block of the one or more metadata blocks reserved on the first storage device, and execute the write operation to store the block of data across the one or more storage devices.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

The systems and methods discussed herein related to analog to digital conversion. An apparatus can include an analog to digital converter including a loop circuit and a comparator circuit. The apparatus can also include a first circuit configured to provide comparator offset calibration for the comparator circuit and a second circuit configured to provide loop calibration for the loop circuit.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A gate all-around laterally diffused metal-oxide semiconductor device is provided. An apparatus includes a substrate, two or more first sheets disposed on the substrate, a gate disposed on the substrate and at least part of the two or more first sheets, and a first epitaxial layer disposed on the substrate on a first side of the gate and at least part of the two or more first sheets. At least part of the two or first more sheets extends longitudinally from the gate to the first epitaxial layer.

IPC Classes  ?

• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

An LDMOS with reduced gate charge and time-dependent dielectric breakdown is provided. An apparatus includes a substrate comprising a first well having a first doping and a second well region having a second doping, a source formed in the first well, and a gate comprising an undoped block and a doped block. The undoped block is disposed at least partially on the source, first well, and second well. The doped block is disposed at least partially on the second well.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

Technical solutions can provide convective cooling of a heat generating circuit through fluid channels formed beneath the circuit and alongside through substrate vias (TSVs). A plurality of parts of TSVs can be etched perpendicularly inside of a surface of a first substrate, where each of the parts of TSVs can be spaced apart from other parts of the TSVs by a set pitch. A plurality of fluid channels can be etched in the same first substrate, each one of which can be located between one or more of the parts of TSVs. A second substrate including a matching set of parts of TSVs can be bonded to the surface of the first substrate to seal the plurality of fluid channels along the surface of the first substrate and complete the TSVs formation. The plurality of fluid channels can dissipate heat from the circuit in thermal contact with the first substrate.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The subject technology is directed to integrated circuit technologies. In an embodiment, the subject technology provides a device that comprises a first circuit and a second circuit and a third circuit. The first circuit is coupled to the second circuit and the third circuit through a first interconnect. The third circuit is coupled to a fourth circuit through a second interconnect. The fourth circuit includes a processor circuit. The third circuit may support data transfer at a speed greater than what the second circuit could handle, facilitating the data transmission between the first circuit and the fourth circuit. There are other embodiments as well.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency

Abstract

Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

IPC Classes  ?

• H03M 1/66 - Digital/analogue converters
• H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
• H03M 1/74 - Simultaneous conversion

Abstract

The technical solutions can include a transmitter of a source device providing access to an application. The transmitter can be configured to detect a category of an application from a first packet to be transmitted from the source, determine a quality of service (QOS) for the application based on the category of the application, mark the first packet with a marker corresponding to the QoS and schedule transmission of the first packet based on the QoS to a destination device. The technical solutions can include a receiver of the destination device configured to identify the QoS set by the transmitter using the marker of the first packet received from the transmitter, mark a second packet to be transmitted from the destination device to the source device using the marker of the first packet, and schedule transmission of the second packet based at least on the QoS to the transmitter.

IPC Classes  ?

• H04L 47/2475 - Traffic characterised by specific attributes, e.g. priority or QoS for supporting traffic characterised by the type of applications
• H04L 45/302 - Route determination based on requested QoS
• H04L 45/745 - Address table lookupAddress filtering

Abstract

This solution provides a Quality of Service (QoS) enablement that involves automatic detection of application categories generating IP traffic in an IP network, utilizing a multi-stage processing of select packets based on a dynamic "shallow packet inspection" procedure. Detected application categories can be classified to meet specific QoS requirements such as low latency, high throughput, and low packet loss. The source device can dynamically mark the packets in the upstream direction based on detected application session attributes, allowing for appropriate QoS queue mapping and transmission. Similarly, downstream packets can be correlated and associated with corresponding upstream packets, ensuring consistent QoS markings and downstream queue mapping for efficient downstream transmission on the destination device.

IPC Classes  ?

• H04L 41/50 - Network service management, e.g. ensuring proper service fulfilment according to agreements

Abstract

A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 1/10 - Distribution of clock signals
• G06F 1/14 - Time supervision arrangements, e.g. real time clock

Abstract

The subject technology is directed to systems and methods for semiconductor devices with die-to-die interfaces. In an embodiment, the subject technology provides an apparatus that includes a first circuit comprising a first interface. The apparatus further includes a first memory device coupled to the first circuit through a second circuit. The second circuit includes a second interface coupled to the first memory device and a third interface coupled to the first circuit. The one or more interfaces of the apparatus are optimized to support a high data rate, breaking the design constraints between the circuit and the associated memory devices. There are other embodiments as well.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A solution for providing improvements in performance of latency sensitive traffic, multi-link operation, link adaptation and in-device coexistence is disclosed. A device with a Wi-Fi transceiver and a second transceiver sharing at least one antenna can detect a burst of communications received by the second transceiver exceeding a time period allocated for second communications. The device can be in communication with a Wi-Fi AP to receive Wi-Fi communications. The device can determine, responsive to the detection, a schedule for the AP to transmit Wi-Fi communications to the device, the schedule comprising a burst limit of a first time period on a periodic basis of a second time period. The device can communicate the schedule to the access point.

IPC Classes  ?

• H04W 72/12 - Wireless traffic scheduling
• H04W 84/12 - WLAN [Wireless Local Area Networks]
• H04W 88/08 - Access point devices

Abstract

Improved tools and techniques for configuring a write head of a hard disk drive and/or for writing data to a hard disk drive. The write surface of a disk in the hard disk drive can be divided into multiple logical zones, with different interleave sizes for each zone. This scheme can meet latency requirements for regions closer to the center of the write surface while providing for better error rate performance in regions further away from the center of the write surface.

IPC Classes  ?

• G11B 20/12 - Formatting, e.g. arrangement of data block or words on the record carriers

Abstract

A system may include one or more processors configured to receive a frame comprising a quantity of commands, a quantity of storage devices, and a buffer map. In response to the frame, the one or more processors may read, using the buffer map and from a memory, (1) input data for each of one or more storage devices corresponding to the quantity of storage devices and (2) an identifier of each of the one or more storage devices. The one or more processors may send, to the one or more storage devices, a plurality of commands corresponding to the quantity of commands, based at least on the input data for each storage device and the identifier of each storage device.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A solution for providing laser mode hop detection in hard disk drives can include a first circuit to provide a signal having a step voltage whose amplitude is adjustable according to a first control signal. The solution can include a second circuit causing the signal to be delayed by a time period to produce a delayed signal, the time period adjustable according to a second control signal. The solution can include a filter to receive the delayed signal as input and provide as output an offset signal corresponding to a frequency response a sensor. The system can subtract the offset signal from a sensor signal of a sensor to provide an output.

IPC Classes  ?

• G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor
• G11B 27/36 - Monitoring, i.e. supervising the progress of recording or reproducing
• G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor

Abstract

A solution can detect an HDD laser mode hop within an improved response time using a sensor amplification circuitry balanced by a frequency response of a gain stage circuit. A sensor of a first circuit can receive an optical signal of a laser as input and output a first voltage that an amplifier can amplify to produce an amplified first voltage indicative of a mode hop event trailing the optical signal by a first response time of a first frequency response. A second circuit coupled in series with the first circuit and operating according to a second frequency response an inverse of the first frequency response can receive the amplified first voltage and generate, based at least on the amplified first voltage adjusted by the second frequency response, a second voltage indicative of the mode hop event within a second response time that is shorter than the first response time.

IPC Classes  ?

• G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
• G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor

Abstract

In some aspects, the disclosure is directed to methods and systems for providing an architecture for building high performance silicon components that support a rich set of networking and security features. In many implementations, the architecture splits network and security functions into two functional and logical blocks (which may physically be on the same die or integrated circuit in some implementations, or may be split on separate integrated circuits). The network functions may be executed via an integrated network interface card and accelerator subsystem with a high throughput execution pipeline. Security functions may be executed asynchronously from the network processing functions, in many implementations.

IPC Classes  ?

• H04L 9/40 - Network security protocols
• H04L 49/1546 - Non-blocking multistage, e.g. Clos using pipelined operation

Abstract

The subject technology is directed to power conversion systems and methods. In some embodiments, the subject technology provides a device comprising a first switch configured to receive a first signal and a second switch configured to receive a second signal. A voltage generator is coupled to the first switch. The device further comprises a first resistor coupled to the first switch and a second resistor coupled to the first resistor. The first switch is further coupled to a first capacitor, which acts as a charge pump to generate the negative voltage such that the output of the device comprises both positive and negative voltages. Embodiments of the subject technology achieve bipolar signaling based on a unipolar design, effectively minimizing DC leakage and overall power consumption. There are other embodiments as well.

IPC Classes  ?

• H02M 7/483 - Converters with outputs that each can have more than two voltage levels
• H02M 1/00 - Details of apparatus for conversion

Abstract

A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.

IPC Classes  ?

• H03L 7/24 - Automatic control of frequency or phaseSynchronisation using a reference signal directly applied to the generator
• H04L 7/00 - Arrangements for synchronising receiver with transmitter

Abstract

The subject technology is directed to systems and methods for semiconductor devices with extended high-bandwidth memory (HBM) offsets. In a specific embodiment, the subject technology provides an apparatus that includes a circuit comprising a first connector and a second connector. The circuit is configured to send a first signal using the first connector to indicate a first selection. The apparatus further includes a first memory device comprising a first selector and a third connector and a fourth connector. The first selector is configured to couple the third connector to the second connector based on the first signal. The one or more connectors of the first memory devices cover a broad distance to ensure robust connectivity between the circuit and the first memory device. There are other embodiments as well.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 13/40 - Bus structure

Abstract

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using first coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the first coefficients.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03H 17/00 - Networks using digital techniques
• H03H 17/06 - Non-recursive filters
• H04B 1/04 - Circuits

Abstract

An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

Technical solutions include systems and methods for coordinated partial-rank nulling in multi access point (AP) transmissions. A first AP can transmit to a second AP a message identifying a station of the first AP for which interference from the second AP is to be partially nulled and a direction in which the interference from the second AP is partially nulled. The first AP can receive from the second AP a message identifying a station of the second AP for which interference from the first AP is to be partially nulled and a direction in which the interference from the first AP is partially nulled at the second station. The first AP can configure settings to coordinate with the second AP a time and a frequency of a transmission to the first station to be sent according to the second direction to partially null the interference at the second station.

IPC Classes  ?

• H04J 11/00 - Orthogonal multiplex systems
• H04W 72/27 - Control channels or signalling for resource management between access points

Abstract

A method includes setting, by a controller, a first bit-rate level for a next video segment, and comparing a fill level of a playback buffer to a first threshold. If the fill level of the playback buffer satisfies the first threshold, the first bit-rate level for the next video segment is replaced by setting a second bit-rate level for the next video. A first request is issued to a server for the next video segment encoded at the first bit-rate level or, if the fill level of the playback buffer satisfies the first threshold, encoded at the second bit-rate level and downloading of the requested next video segment and storing the requested video segment in the playback buffer. A decoder decodes the next video segment from the playback buffer for playback on a display device after the next video segment has been downloaded and stored in the playback buffer.

IPC Classes  ?

• H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
• H04N 21/437 - Interfacing the upstream path of the transmission network, e.g. for transmitting client requests to a VOD server
• H04N 21/439 - Processing of audio elementary streams
• H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
• H04N 21/845 - Structuring of content, e.g. decomposing content into time segments

Abstract

The present invention is directed to semiconductor devices and manufacturing methods. According to an embodiment, the present invention provides a semiconductor have includes a circuit that is coupled to a substrate. The substrate comprises a plurality of layers, some of which comprise organic material. In some implementations, the substrate may be a coreless substrate that is free from a core material. There are other embodiments as well.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/311 - Etching the insulating layers
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Abstract

Mode hop detection is provided. A device includes circuitry to receive, from a reader element an indication of one or more properties of a magnetic medium detected by the reader element. The device includes circuitry to determine an envelope of the signal. The device includes circuitry to adjust, responsive to the envelope, a current provided to a laser configured to heat the magnetic medium.

IPC Classes  ?

• G11B 7/126 - Circuits, methods or arrangements for laser control or stabilisation
• G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor

Abstract

Spatial reuse is provided. A device can identify first symbols orthogonal to second symbols, responsive to a receipt of an indication, from a second device, of a transmission of a second message including the second symbols. The device can transmit a first message including the first symbols, simultaneously with the transmission of the second message.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

Systems and methods can advantageously provide a protocol. A device using the protocol can include circuitry device configured to provide at least one frame while a connection is being established. The frame includes data indicating that the device is capable of a data management multilink (DMML) operation. In some examples, the frame is provided according to an 802.11 protocol.

IPC Classes  ?

• H04W 52/32 - TPC of broadcast or control channels
• H04W 52/02 - Power saving arrangements
• H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
• H04W 76/10 - Connection setup

Abstract

A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.

IPC Classes  ?

• H04L 7/00 - Arrangements for synchronising receiver with transmitter
• H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

Systems and methods use a protocol for handoff operations. A first device using the protocol includes a circuit configured to provide at least one frame across a connection to a second device in response to a pending failure. The frame includes data indicating at least one target access point for the second device.

IPC Classes  ?

• H04W 36/08 - Reselecting an access point
• H04W 36/00 - Handoff or reselecting arrangements

Abstract

The present invention is directed to semiconductor devices and packages. According to an exemplary embodiment, one or more substrate extensions are coupled to a base substrate, with portions of one or more substrates extending beyond the base substrate. Electrical and/or optical connections are connected to these substrate extensions. There are additional embodiments as well.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A system may include circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver and couple a first end of a second resistor to a second input terminal of the line driver. The circuitry may be configured to receive, at a second end of the first resistor, a first signal. The circuitry may be configured to receive, at a second end of the second resistor, a second signal. The circuitry may be configured to set at least one of the first resistor or the second resistor to cause the line driver to output a predetermined range of output voltages, based at least on a voltage sensed from at least one of the first signal or the second signal.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers

Abstract

Systems and methods use a protocol for disassociation/deauthentication. Some embodiments relate to a first device including a circuit configured to provide at least one frame across a connection to a second device during a disassociation operation or deauthentication operation. The frame can include data indicating at least one target access point for the second device. The frame can be provided according to an 802.11 protocol and the connection can be established by using an association or authentication operation.

IPC Classes  ?

• H04W 72/0446 - Resources in time domain, e.g. slots or frames

Abstract

The present invention relates to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device comprising a double-sided fanout die package is provided. On one surface of a main circuit board for the semiconductor device, regular single-sided flip-chip dies and tall SMT components are coupled, along with one or more double-sided fanout dies, which are stacked with corresponding sub-sized circuit boards that are also coupled to the same surface, with a smaller height than the tallest surface mount device. A portion of the metal routing and grounding connections in the main circuit board for one or more double-sided fanout dies can be transferred to the sub-sized circuit boards, thereby reducing the area of the main circuit board without increasing the number of circuit board layers. There are other embodiments as well.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A system may include circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver, and couple a first end of a second resistor to a second input terminal of the line driver. The circuitry may be configured to receive, at a second end of the first resistor, a first signal. The circuitry may be configured to receive, at a second end of the second resistor, a second signal. The circuitry may be configured to set resistance of at least one of the first resistor or the second resistor such that the line driver outputs a predetermined range of output voltages based at least on a voltage sensed from at least one of the first signal or the second signal.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers

Abstract

An apparatus includes a first circuit that has a photodetector. The photodetector is reverse-biased by a reverse-bias voltage. A common mode voltage is added to the reverse-bias voltage to provide an offset to the photodetector voltage. A second circuit is coupled to the first circuit to provide the common mode voltage for the first circuit. A third circuit is coupled to the second circuit that includes a first voltage source and a second voltage source having opposite voltages equal to half of the reverse-bias voltage. Each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the third circuit. The first voltage source and the second voltage source provide the reverse-bias voltage to the first circuit to reverse-bias the photodetector. The third circuit provides a photodetector current at an output of the third circuit.

IPC Classes  ?

• G01J 1/44 - Electric circuits
• H03H 11/04 - Frequency selective two-port networks

Abstract

A device includes a port and a transformer. The transformer includes a first coil that has a first node and a second node and a second coil that is coupled to the output port. The device also includes a pulse generator coupled to the first node to generate two or more pulses with a first period on the first node and a delay module that is coupled between the second node of the first coil and the pulse generator. The delay module is generates a time delay to the two or more pulses of the pulse generator before the two or more pulses are delivered to the second node. The second coil provides a signal at the port.

IPC Classes  ?

• G01S 7/28 - Details of pulse systems
• G01S 7/484 - Transmitters

Abstract

Systems and methods relate a device for monitoring or tracking clock frequency. The device can include a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal, and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal is indicative of a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal. The device can also include a third circuit configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal using the second signal.

IPC Classes  ?

• H03K 21/02 - Input circuits
• G01R 23/00 - Arrangements for measuring frequenciesArrangements for analysing frequency spectra
• G06F 1/10 - Distribution of clock signals

Abstract

Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

IPC Classes  ?

• H03L 7/08 - Details of the phase-locked loop
• G06F 1/10 - Distribution of clock signals
• G06F 1/12 - Synchronisation of different clock signals
• H03K 3/037 - Bistable circuits
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

A device may include one or more ring oscillators and circuitry. The one or more ring oscillators may include a plurality of rings. The circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. The circuitry may be configured to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals to one or more digital signals.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters

Abstract

The present invention is directed to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device with a heat spreader structure is provided. The heat spreader is configured to couple to a second layer to establish an effective thermal dissipation path for heat generated from a hot spot of a circuit. The second layer comprises a first portion and a second portion. The first portion is coupled to the hot spot. The heat spreader comprises a third portion and a fourth portion. The third portion comprises a protrusion coupled to the first portion via a first side surface. There are other embodiments as well.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.

IPC Classes  ?

• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Abstract

Disclosed herein are implementations of a hybrid network for use in a full duplex communication system. In one aspect, the hybrid network includes a first circuit coupled between an output of a communication channel and a shared output of a transmitter and the communication channel, a second circuit coupled between a first output of the transmitter and the shared output, a third circuit coupled between the shared output and an input of an amplifier, a fourth circuit coupled between the input of the amplifier and a second output of the transmitter, and a fifth circuit coupled between an output of the amplifier and the input of the amplifier. In some embodiments, the output of the amplifier is coupled to an input of a receiver.

IPC Classes  ?

• H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
• H04B 1/403 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

IPC Classes  ?

• G01J 1/46 - Electric circuits using a capacitor
• G01J 1/44 - Electric circuits

Abstract

Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

IPC Classes  ?

• H04L 43/026 - Capturing of monitoring data using flow identification
• H04L 41/147 - Network analysis or design for predicting network behaviour

Abstract

An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.

IPC Classes  ?

• H03M 7/40 - Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
• H03M 7/16 - Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code

Abstract

A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.

IPC Classes  ?

• H04L 27/00 - Modulated-carrier systems
• H04L 27/36 - Modulator circuitsTransmitter circuits

Abstract

The present invention is directed to semiconductor devices and manufacturing methods thereof. In a specific embodiment, the present invention provides a semiconductor device that includes a filling material that supports the sides of an integrated circuit, which is coupled to a surface of a semiconductor substrate and surround by a ring structure. A portion of the filling material is positioned between the integrated circuit and the semiconductor substrate. There are other embodiments as well.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation

Abstract

A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H04L 27/00 - Modulated-carrier systems

Abstract

An apparatus includes a first circuit to receive a first input data, a second input data and coefficients, generate a first distortion term and a second distortion term based, respectively on the first input data and the coefficients and the second input data and the coefficients, and change a polarity of the first distortion term and the second distortion term. A first subtraction circuit subtracts the first distortion term from the first input data and generates first difference data, and a second subtraction circuit subtracts the second distortion term from the second input data and generates second difference data. A transmit data-path generates a RF output. The first difference data and the second difference data compensate, based on the polarity changes of the first distortion term and the second distortion term, respectively, one or more impairments of the RF output.

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/16 - Circuits
• H04B 1/68 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for wholly or partially suppressing the carrier or one side band

Abstract

An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Abstract

A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.

IPC Classes  ?

• H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering
• H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

An apparatus includes a circuitry to perform a first startup stage and to vary, during a second startup stage subsequent to the first startup stage, a duty cycle of a pulse controlling one or more switches of the circuitry.

IPC Classes  ?

• H02M 1/36 - Means for starting or stopping converters
• H02M 1/32 - Means for protecting converters other than by automatic disconnection
• H03K 7/08 - Duration or width modulation

Abstract

A device includes a first circuit, a ground, a reference voltage source that provides a reference voltage, and a first transistor that includes a first drain, a first source, and a first gate. The first circuit is coupled between the first source and the ground. The device has a second transistor that includes a second source and a second gate. The second transistor is biased as a source follower with the second source of the second transistor being set at the reference voltage. The first gate of the first transistor is coupled to the second gate of the second transistor, the first source has equal voltage as the second source, and the first circuit is coupled between the first source having the reference voltage and the ground to draw a constant current from the first source and to bias the first transistor in the saturation region to reduce parasitic capacitance.

IPC Classes  ?

• H05B 45/36 - Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI]
• H05B 45/345 - Current stabilisationMaintaining constant current

Abstract

A device includes a circuit that generates a first current associated with a voltage of a region of a semiconductor substrate, a second current associated with a temperature of the region, a third current associated with a first process parameter of the region, and a fourth current associated with a second process parameter of the region. A multiplexer of the device receives the first, second, third, and fourth currents and selects the currents one by one and periodically. A ring oscillator of the device is coupled to the multiplexer and receives the first, second, third, and fourth currents one by one and periodically, from the multiplexer. The ring oscillator oscillates at oscillation frequencies that are based on the received current from the multiplexer. The voltage, temperature, and the first and second process parameters of the region are determined based on the oscillation frequencies.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

In some aspects, the disclosure is directed to methods and systems for providing a hybrid low power, high bandwidth media transport protocol between media sinks and media sources by splitting control and synchronization commands to a low power communication interface, and media data to a high bandwidth unidirectional communication interface. Media sinks need not transmit via the high bandwidth unidirectional communication interface, reducing power consumption, which may be particularly beneficial for small devices with limited battery capacity such as wireless earbuds.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04L 69/14 - Multichannel or multilink protocols
• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• H04W 56/00 - Synchronisation arrangements
• H04W 84/12 - WLAN [Wireless Local Area Networks]
• H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks

Abstract

In an example architecture flexible arithmetic coding system, coding circuitry of a device may receive video data that is to be coded (e.g., to be encoded or decoded) by arithmetic coding. The coding circuitry may compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation. The coding circuitry may perform arithmetic coding on the video data using the at least one of the LPS range or the MPS range. Arithmetic coding may be binary arithmetic coding. The computation of the LPS range or the MPS range using the multiplication operation may reduce computational cost.

IPC Classes  ?

• H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• H04N 19/126 - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
• H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
• H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

An apparatus of the subject technology includes a first comparator circuit having a first offset voltage and a first circuit to generate a first code based on the first offset voltage. The apparatus further comprises a second comparator circuit having a second offset voltage and a second circuit that generates a second code based on the second offset voltage and the first code. The first offset voltage and the second offset voltage are partially compensated based on the second code.

IPC Classes  ?

• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

A circuit includes a driver to provide a voltage at a node of a load and a first circuit to facilitate determining a load current at the node. The load is a capacitive load and the first circuit facilitates determining the load current by measuring a replica current and determining a capacitance of the load using values of the voltage and the replica current.

IPC Classes  ?

• G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof

Abstract

An apparatus includes a boost converter including a compensation circuit to implement a switching scheme and partitioned into multiple circuits and a calculator circuit configured to determine a voltage to be applied to the compensation circuit. The multiple circuits each includes a capacitor and a voltage is applicable to pre-charge the capacitors to a voltage corresponding to an error voltage, as determined by the calculator circuit. The pre-charged capacitors can enable an immediate settling of the error voltage to achieve an instantaneous response of the compensation circuit. Beneficially, the apparatus can drive a power stage circuit to supply power to a load (e.g., LED) without overshoot or undershoot.

IPC Classes  ?

• H05B 45/38 - Switched mode power supply [SMPS] using boost topology
• H02M 1/00 - Details of apparatus for conversion
• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

The present invention is directed to electrical circuits. In a specific embodiment, a first interface circuit is coupled to a first plurality of ports for processing signals at a first frequency range, and a second interface circuit is coupled to a second plurality of ports for processing signals at a second frequency range. The first interface circuit is coupled to a timing channel circuit. The second interface circuit is coupled to an energy channel circuit. There are other embodiments as well.

IPC Classes  ?

• H03H 7/01 - Frequency selective two-port networks
• G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
• G01S 7/487 - Extracting wanted echo signals
• G01S 7/527 - Extracting wanted echo signals

Abstract

A circuit includes a boost circuit, a first circuit coupled to the boost circuit and a second circuit coupled to the boost circuit. The boost circuit, the first circuit, and the second circuit form an open loop. The first circuit and the second circuit maintain a switching frequency of the boost circuit above a threshold frequency.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/00 - Details of apparatus for conversion
• H02M 1/14 - Arrangements for reducing ripples from DC input or output

Abstract

A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• H03M 1/80 - Simultaneous conversion using weighted impedances
• H03M 3/00 - Conversion of analogue values to or from differential modulation