Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
3.
DNA Alignment using a Hierarchical Inverted Index Table
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Methods and device for constructing a specification data structure for a module of a multiprocessor array (MPA) chip. The specification data structure includes parameters for combining a plurality of register transfer language (RTL) templates for submodules of the modules into an RTL description of the module, parameters for combining a plurality of test bench templates for respective submodules into a test bench for the module, parameters for combining a plurality of physical design script templates for respective submodules into a physical design script for the module, and/or parameters for constructing an API for the module based on a set of functional criteria for module operation. The RTL description, the test bench, the physical design script, and/or the API are constructed and stored in memory for use in designing and fabricating the module.
Methods and device for constructing a specification data structure for a module of a multiprocessor array (MPA) chip. The specification data structure includes parameters for combining a plurality of register transfer language (RTL) templates for submodules of the modules into an RTL description of the module, parameters for combining a plurality of test bench templates for respective submodules into a test bench for the module, parameters for combining a plurality of physical design script templates for respective submodules into a physical design script for the module, and/or parameters for constructing an API for the module based on a set of functional criteria for module operation. The RTL description, the test bench, the physical design script, and/or the API are constructed and stored in memory for use in designing and fabricating the module.
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
13.
Wireless transport framework with uncoded transport tunneling
Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
14.
Parameterized radio waveform techniques for operating in multiple wireless environments
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device, performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.
A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
H04N 7/16 - Analogue secrecy systemsAnalogue subscription systems
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
19.
Parameterized radio waveform techniques for operating in multiple wireless environments
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
H04N 19/43 - Hardware specially adapted for motion estimation or compensation
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
21.
Comprehensive system design to address the needs for virtual segmentation of the coaxial cable plant
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H02J 1/02 - Arrangements for reducing harmonics or ripples
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.
A broadcast/broadband convergence system that delivers content from content sources to user equipment devices. The system provides: significantly enhanced mobile capability to the broadcast industry; an additional revenue source for the broadcast industry by dynamically selling available spectral resources for use by wireless broadband networks and/or broadcast content off-loaded from wireless broadband networks; additional spectrum for the broadband industry through the dynamic purchase of available spectrum; and an enriched user experience. A spectrum server may facilitate the dynamic allocation of radio spectrum made available by the broadcast networks. The broadcast networks may broadcast with enhanced waveform parameters to support mobile devices as well as fixed devices.
H04W 4/06 - Selective distribution of broadcast services, e.g. multimedia broadcast multicast service [MBMS]Services to user groupsOne-way selective calling services
A flexible diplexer may include a programmably reconfigurable filter pair capable of rendering a variety of band-split arrangements in a digital signal processor (DSP) backed design in hybrid fiber coaxial cable plant/system deployments. The flexible diplexers may thereby meet a larger range of band-split requirements, including the full range of band-split requirements. Configurability may be achieved by digitizing the signal at either input interface of a diplexer in a diplexer/amplifier complex after bandpass filtering, and two-to-four wire conversion at the respective forward (e.g. downstream) and reverse (e.g. upstream) input interfaces. A new band-split may be obtained by updating the digital filters using specified coefficient sets determined off-line and retrieved from memory. The flexible diplexer/amplifier complex may enable the implementation of additional functionality including equalization and tilt regeneration, self-interference cancellation, virtual segmentation, and/or creation of auxiliary service points to provide access to/from a small cell base station and/or Wi-Fi access point.
H04B 3/20 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other
H04B 3/21 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a set of bandfilters
27.
Enhanced polarization weighting to enable scalability in polar code bit distribution
Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
28.
Dynamic reconfiguration of applications on a multi-processor embedded system
A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Digital signal processors; data processors; micro
processors; signal processors; integrated circuits;
downloadable computer-aided manufacturing (CAM) software for
integrated circuits; downloadable computer-aided design
(CAD) software for designing and programming integrated
circuits. Engineering services, namely, non-recurring engineering in
the field of computer software, integrated circuits, and
processors; design for others in the fields of computer
software and engineering for integrated circuits and
processors; custom design and engineering of computer
software, integrated circuits, and processors; engineering
design services; research, development, engineering, and
testing services in the field of computer software,
integrated circuits, and processors; consulting in the field
of engineering; electrical engineering. Licensing of industrial property rights; licensing of
intellectual property rights; computer software licensing;
licensing of software for design of integrated circuits.
30.
Scrambling sequence design for embedding receiver ID into frozen bits for blind detection
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
(1) Digital signal processors; central processing units; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits. (1) Engineering services, namely, non-recurring computer hardware and computer software engineering in the field of computer software, integrated circuits, and computer processors; design for others in the fields of computer software and computer hardware and computer software engineering for integrated circuits and computer processors; custom design and engineering of computer software, integrated circuits, and computer processors; engineering design services in the field of computer hardware and computer software; research, development, engineering, and testing services in the field of computer software, integrated circuits, and computer processors; consulting in the field of computer hardware and computer software engineering; electrical engineering.
(2) Licensing of industrial property rights; licensing of intellectual property rights; computer software licensing; licensing of software for design of integrated circuits.
33.
Multimedia streams which use control information to associate audiovisual streams
A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/04 - Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
H04L 1/06 - Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
34.
Low latency video codec and transmission with parallel processing
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
35.
Control information for a wirelessly-transmitted data stream
Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
H04N 7/16 - Analogue secrecy systemsAnalogue subscription systems
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Digital signal processors; data processors; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits Engineering services, namely, non-recurring engineering in the field of computer software, integrated circuits, and processors; design for others in the fields of computer software and engineering for integrated circuits and processors; custom design and engineering of computer software, integrated circuits, and processors; engineering design services; research, development, engineering, and testing services in the field of computer software, integrated circuits, and processors; consulting in the field of engineering; electrical engineering Licensing of industrial property rights; licensing of intellectual property rights; computer software licensing; licensing of software for design of integrated circuits
09 - Scientific and electric apparatus and instruments
Goods & Services
Digital signal processors; data processors; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits
39.
Multiprocessor system with improved secondary interconnection network
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
42.
A COMPREHENSIVE SYSTEM DESIGN TO ADDRESS THE NEEDS FOR VIRTUAL SEGMENTATION OF THE COAXIAL CABLE PLANT
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device, performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may include first program instructions executable to perform a function. In some embodiments, the software code may also include one or more language constructs that are configurable to specify one or more one or more parameter inputs. In some embodiments, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In some embodiments, the hardware resources include multiple processors and may include multiple supporting memories.
Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
47.
Scrambling sequence design for embedding receiver ID into frozen bits for blind detection
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H02J 1/02 - Arrangements for reducing harmonics or ripples
Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.
Techniques are disclosed relating to spectrum sharing between different radio access technologies. In some embodiments, a broadcast base station is configured to wirelessly broadcast audio and video data to a plurality of broadcast receiver devices using a particular frequency band. In these embodiments, the broadcast base station is configured to discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform cellular packet-switched wireless data communications using the particular frequency band.
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 15/76 - Architectures of general purpose stored program computers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.
Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.
A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/04 - Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
H04L 1/06 - Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
56.
Memory-network processor with programmable optimizations
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
H04N 7/16 - Analogue secrecy systemsAnalogue subscription systems
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
59.
LOW LATENCY VIDEO CODEC AND TRANSMISSION WITH PARALLEL PROCESSING
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
60.
Low latency video codec and transmission with parallel processing
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
61.
Parameterized radio waveform techniques for operating in multiple wireless environments
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 15/76 - Architectures of general purpose stored program computers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
H04N 7/16 - Analogue secrecy systemsAnalogue subscription systems
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
Techniques are disclosed relating to spectrum sharing between different radio access technologies. In some embodiments, a broadcast base station is configured to wirelessly broadcast audio and video data to a plurality of broadcast receiver devices using a particular frequency band. In these embodiments, the broadcast base station is configured to discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform cellular packet-switched wireless data communications using the particular frequency band.
System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
71.
Scrambling sequence design for multi-mode block discrimination on DCI blind detection
Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
G06F 9/00 - Arrangements for program control, e.g. control units
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
G06F 15/177 - Initialisation or configuration control
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
76.
Processing system with interspersed processors with multi-layer interconnection
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
77.
Dynamic reconfiguration of applications on a multi-processor embedded system
A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.
Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
81.
SCRAMBLING SEQUENCE DESIGN FOR EMBEDDING UE ID INTO FROZEN BITS FOR DCI BLIND DETECTION
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may include first program instructions executable to perform a function. In some embodiments, the software code may also include one or more language constructs that are configurable to specify one or more parameter inputs. In some embodiments, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In some embodiments, the hardware resources include multiple processors and may include multiple supporting memories.
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/04 - Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
H04L 1/06 - Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
89.
Parameterized radio waveform techniques for operating in multiple wireless environments
Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
91.
Processor Instructions to Accelerate FEC Encoding and Decoding
Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both ûφ= 0 and ûφ= 1 bit estimate (LLR) updates based on the row from which the updated row will be derived.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
G06F 19/24 - for machine learning, data mining or biostatistics, e.g. pattern finding, knowledge discovery, rule extraction, correlation, clustering or classification
G06F 19/18 - for functional genomics or proteomics, e.g. genotype-phenotype associations, linkage disequilibrium, population genetics, binding site identification, mutagenesis, genotyping or genome annotation, protein-protein interactions or protein-nucleic acid interactions
97.
DNA alignment using a hierarchical inverted index table
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
H04N 7/16 - Analogue secrecy systemsAnalogue subscription systems
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video streamRemultiplexing of multiplex streamsInsertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rateAssembling of a packetised elementary stream
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
99.
Multimedia streams which use control information to associate audiovisual streams
A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/04 - Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
H04L 1/06 - Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
100.
Real time analysis and control for a multiprocessor system
System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
