The present invention relates to the technical field of storage, and particularly, to a storage method and a storage system of a memory, so as to solve a problem of an increase in resource costs caused by a fact that large storage space is needed when an SLC memory stores large amount of data, and solve a problem that data loss easily occurs due to a complex structure when an MLC memory stores data having high security. The following method is used in embodiments, and the method comprises: determining to-be-migrated data in a logic block in an SLC mode, and migrating the to-be-migrated data in the logic block in the SLC mode to a logic block in an MLC mode having not stored data; and determining to-be-migrated data in an logic block in an MLC mode, and migrating the to-be-migrated data in the logic block in the MLC mode to a logic block in an SLC mode having not stored data. When stored data has a high requirement for security, the data is migrated to the logic block in the SLC mode and is stored; and when a large amount of data is stored, the data is migrated to the logic block in the MLC mode and is stored.
An on-chip reference voltage generation circuit, comprising a clamping unit (20), an initial parameter unit (21), a power supply generation unit (25), a calibration unit (26), a selection unit (22), a control unit (23) and a reference voltage generation unit (24); the clamping unit (20) is used to clamp the supply voltage; the initial parameter unit (21) is used to store a preset initial parameter, operate and output the preset initial parameter under the clamped voltage; the power supply generation unit (25) is used to stabilize the inputted supply voltage and output a stabilized voltage supply; the calibration unit (26) is used to generate and output a calibrated parameter by using the stabilized voltage supply as an operating voltage; the selection unit (22) is used to receive the preset initial parameter and the calibrated parameter, and select one of the two parameters to be outputted; the control unit (23) is used to transmit a control signal after a preset period of time to control the selection unit (22) to select the calibrated parameter; and the reference voltage generation unit (24) is used to generate a first reference voltage (VREF1) according to the preset initial parameter, and generate a second reference voltage (VREF2) according to the calibrated parameter, the first reference voltage (VREF1) serving as the reference voltage of the power supply generation unit (25).
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
The present invention is applicable in the technical field of chips. Provided in embodiments of the present invention is a method for verifying an SOC chip. The method comprises the following steps: loading a testing procedure; scheduling a corresponding system function from a system interface function library on the basis of the testing procedure, and generating a random event on the basis of the system function and of a maintenance list corresponding to the system function; and verifying a test-awaiting chip on the basis of the random event. The present invention allows the testing procedure compiled by a software engineer to run directly on an existing verification platform, thereby implementing co-verification of software and hardware, while at the same time packages low-level information, thus allowing for convenient use and reuse of verification system.
The present invention is applicable in the technical field of chip. Provided in embodiments of the present invention is a method for verifying an SOC chip. The method comprises the following steps: loading a testing procedure; scheduling a corresponding system function from a system interface function library on the basis of the testing procedure, and generating a random event on the basis of the system function and of a maintenance list corresponding to the system function; and verifying the test-awaiting SOC chip on the basis of the random event. The present invention allows the testing procedure compiled by a software engineer to run directly on an existing verification platform, thereby implementing co-verification of software and hardware, while at the same time packages low-level information, thus allowing for convenient use and reuse of verification system.
Provided are a method and apparatus for detecting resistive touch panel. In order to obtain the inclination angle of a connecting line between two points, the present invention firstly calculates the resistance variance ratio of the Y plane relative to the X plane based on the voltage detection before touching and after the touching of two points; and then calculates the inclination angle based on the corresponding relationship between the inclination angle and the resistance variance ratio. In order to obtain the distance between the two points, the present invention firstly calculates the resistance variance ratio, and a first ratio of the resistance variance of any one plane of the X plane and the Y plane relative to the total resistance of the any one plane; then calculates a second ratio of an equivalent contact resistance at midpoint relative to the total resistance of the any one plane; and lastly calculates the distance between the two points based on the resistance variance ratio determined according to the corresponding relationship, the first ratio, the second ratio, and the correlated relationship of the distance between the two points. In addition, the present invention can also calculate the coordinates of the two points.
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
6.
DIRECT DRIVE CIRCUITRY AND METHOD FOR HOT PLUG DETECTION OF AUDIO LINE END
Direct drive circuitry and a method for the hot plug detection of an audio line end. The circuitry includes an audio line end jack, a pull-up circuit, a pull-down circuit and an operational amplifier. Two ends of the audio line end jack are connected to the pull-up circuit and pull-down circuit respectively, the positive input end of the operational amplifier inputs a reference voltage, the negative input end and output end of the operational amplifier are connected to two ground ends of the audio line end jack respectively, and by detecting the voltage at the negative input end of the operational amplifier, the hot plug state of the audio line end is determined according to the detected voltage . The direct drive circuitry for the hot plug detection of an audio line end is simple and reliable without occupying an additional GPIO port to perform detection, saving Pin resources; moreover, whether or not the operational amplifier is opened will not affect the accuracy of the detection result, which can reduce power consumption and at the same time reduce the number of elements used by the direct drive circuitry for detection, saving the area of the printed circuit board (PCB) and lowering the cost.
Disclosed are a semiconductor device, a chip and a method for modifying bit data, which relate to the technical field of chip design, and add a modification manner for modifying bit data recorded in a chip. The chip for recording bit data of the present application comprises N columns of metal layers, and each column comprises M metal layers, N and M being integers not smaller than 2. A bitline of an NMOS transistor for recording the bit data is cured in a bottom or top metal layer of an edge column in the N columns of metal layers, and a drain of the NMOS transistor is cured in a bottom or top metal layer of another edge column. Adjacent metal layers in the same layer are in a state of being connected or disconnected, and a connection layer is or is not disposed between adjacent layers at the same column, so that a path exists or does not exist between the bitline and the drain. By adopting the solution, a modification manner for modifying bit data recorded in a chip can be added.
The present invention is suitable for the field of digital technology, providing a randomizing circuit, a storage control unit, a storage, and a communication system and method. The randomizing circuit comprises a PN code generator, and a seed generator which is connected to the PN code generator and used for providing an initial seed for the PN code generator. The present invention improves the randomization level and randomness of the PN code by way of adding into the randomizing circuit a seed generator used for changing the initial value of the randomizing circuit. Thus the storing stability of the storage which contains the randomizing circuit and security of data transmission in the communication system which contains the randomizing circuit are improved.
Disclosed are a switch-mode power supply control system and method thereof. The switch-mode power supply control system comprises a reference signal generating circuit (10), a power switch driving circuit (50), a power switch and output circuit (60), a pulse frequency modulation (PFM) controlling circuit (30), a pulse width modulation (PWM) controlling circuit (20) and a preset duty cycle adjustment circuit (40). The preset duty cycle adjustment circuit (40) is used to compare the voltage feedback signal and the current feedback signal of the power switch and output circuit (60) with a received reference voltage signal or reference current signal, decide whether to output a mode switching signal to the PWM controlling circuit (20), and output a control logic signal to the power switch driving circuit (50) if a mode switching signal is received. The switch-mode power supply control system can quickly increase the actual output voltage of the switch-mode power supply, thus improves the load transient response and avoids affecting the normal operation of electronic devices.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
10.
AUDIO POWER AMPLIFIER AND METHOD FOR SWITCHING AUDIO POWER AMPLIFICATION MODES
An audio power amplifier and a method for switching audio power amplification modes, performing switching of power amplification modes to meet requirements of electronic products for power consumption and electromagnetic interference (EMI) in different function modes. The method involves: when a device in which a power amplifier exists determines that the power consumption corresponding to the function mode that the device is currently in is lower than a power consumption threshold, a switch array unit (2) is indicated switching on a Class AB drive unit (3); when it is determined that the power consumption is greater than or equal to the power consumption threshold, and a function unit being more sensitive to EMI has been turned on, a control signal for indicating switching on the Class AB drive unit (3) is sent to the switch array unit (2); when it is determined that the power consumption is greater than or equal to the power consumption threshold, and none of function units being more sensitive to EMI has been turned on, the switch array unit (2) is indicated switching on a Class D modulation unit (4).
Provided is an audio data encoding method and device for use in Ogg/Vorbis encoding in portable multimedia players. The method comprises: receiving audio data requiring encoding (300); performing MDCT to the audio data (310); calculating the masking curve on the basis of the MDCT results (320); calculating and generating the base curve on the basis of the masking curve by means of the piecewise linear method (330); calculating and generating the spectral residual on the basis of the masking curve and the base curve (340); performing channel coupling to the spectral residual (350); performing vector quantization calculations on the post-channel coupling results (360); encoding, according to an assigned sampling rate and a bit rate, the data obtained by means of vector quantization calculation, and then obtaining encoded audio data (370). The method substitutes the tone-masking curve and noise-masking curve with a single masking curve, thereby reducing the amount of encoding calculations, and uses an assigned sampling rate and bit rate to encode post-vector quantization data, thereby reducing the amount of program space the encoding occupies. The method reduces the complexity of Ogg/Vorbis encoding calculations, thereby making possible Ogg/Vorbis encoding in a portable device.
G10L 19/00 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocodersCoding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
G10L 19/02 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocodersCoding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders
12.
CHIP WITH VERSION NUMBER AND METHOD FOR MODIFYING CHIP VERSION NUMBER THEREOF
A chip with a version number and a method for modifying the chip version number thereof, belonging to the field of chip design, are provided. The chip structure comprises a pair of independent channels (channel 1, channel 2) running through the chip from the bottom to the top and connecting to a high voltage and a low voltage respectively, wherein one of the channels is led out as a bit of the version number, so that the modification of the chip version number is no longer dependent on a specific layer, and each of metal layers (metal 1, metal 2, metal 3, metal 4) can achieve the chip version number modification. A cross-layer structure is set in each via layer (via 1, via 2, via 3). As long as any via layer is changed, the chip version number is modified.
An integrated circuit with a scan chain and a chip testing method are disclosed. The integrated circuit (20) includes a first interface group (11), a second interface group (14) and a scan data selector (12). The first interface group (11) and the second interface group (14) each respectively include at least two I/O ports which can be packaged as external pins of the integrated circuit. Each I/O port of the first interface group (11) corresponds to the input end of the scan data selector (12). The output end of the scan data selector (12) is connected with the scan data input end of the scan chain (13). The scan data output end of the scan chain (13) is connected with each I/O port of the second interface group (14).
An integrated circuit is disclosed in present invention, which includes: a first frequency division unit, a counter, an oscillation signal generation circuit and a second frequency division unit; wherein: the first frequency division unit is used for dividing the frequency of an external clock signal from exterior of the integrated circuit to acquire a first reference clock; the oscillation signal generation circuit is used for generating the oscillation signal; the counter is used for taking count of the oscillation signal using the first reference clock to acquire frequency information of the oscillation signal; and, the second frequency division unit is used for dividing the frequency of the oscillation signal according to a frequency division factor obtained on the basis of the frequency information to acquire a second reference clock. A method for acquiring a reference clock in the integrated circuit is also disclosed in the invention. The solution of the invention can acquire an accurate reference clock under the condition of without a low-frequency crystal oscillator, and save precious pin resources.
H03K 23/58 - Gating or clocking signals not applied to all stages, i.e. asynchronous counters
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
A device for analyzing code streams is disclosed by the present invention, comprising a decoder library consisting of more than one decoder, a component module, and a user interface module. The component module is used for selecting corresponding decoders according to inputted code streams, invoking an interface unit corresponding to the decoder library according to an operation instruction from the user interface module, receiving data from the decoder library, and outputting the data to the user interface module; the user interface module is used for providing a human-computer interaction interface which is visible for users, receiving operation instructions from the users, outputting the operation instructions to the component module, and displaying data from the component module on the human-computer interaction interface. A method for analyzing code streams is also disclosed by the present invention, which is implemented based on the device for analyzing code streams. The device for analyzing code streams provided by the present invention can support multimedia code streams with multiple types of coding standards.
A method and a device for reducing the waste of the central process unit (CPU) resource during the filling process of a vector graphic, and the method includes: parsing the vector graphic to obtain a series of polygons; mapping the polygons into a new drawing coordinate whose unit is 1/2n pixel using a transform parameter and a transform matrix, while updating an original drawing window into the new drawing coordinate at the same time, wherein the transform parameter is A, A=2n/K, n is a shift parameter, the unit of the vertex coordinate of the polygon is 1/K pixel, and n, K are valued for natural numbers; obtaining the portions of the polygons located in the new drawing window in the new drawing coordinate ; transforming the portions of the polygons located in the new drawing window in the new drawing coordinate into a group of scan segments; and shifting the original code of the coordinate of the scan segments to right by n bit, and rendering the pixels of the shifted scan segments. In the embodiment of the present invention, when the pixels covered by the scanning line are rendered, and the division operations are replaced with the manner of shifting the coordinate values, and the generated polygon cutting error is transferred to the calculating process before the rendering, the division operation is reduced in the precondition of ensuring the result is correct, so that the occupation of the CPU resource is reduced.
An integrated circuit, wherein a voltage-adjustable power supply circuit(42) receives a first power supply control signal(6) output by a programming power supply control circuit(41), outputs a first voltage signal to a efuse circuit(44) by a power source switching circuit(43) and outputs the first voltage signal to other functional circuits(45) of the integrated circuit, and the efuse circuit(44) receives the first voltage signal and a first programming control signal(5) output by the programming power supply control circuit(41) and burns out a corresponding efuse therein; or the voltage adjustable power supply circuit(42) receives a second power supply control signal(6) output by the programming power supply control circuit(41) and outputs a second voltage signal to other functional circuits(45) of the integrated circuit, and the efuse circuit(44) receives a second programming control signal(5) output by the programming power supply control circuit(41) and ensures a corresponding efuse therein not to be burnt out. Compared with the integrated circuit in the prior art, which integrates the efuse circuit(44), the integrated circuit of the invention saves production cost and use cost and also saves the lead pin resources of the integrated circuit.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
A battery charging method and device. The device includes a constant current circuit (403), a constant voltage circuit (404) and a control circuit (405). The control circuit (405) is used to control the constant current circuit (403) to charge a battery (402) with a constant current, control the constant voltage circuit (404) to charge the battery (402) with a constant voltage after the battery voltage during the constant current charging process reaches a preset charge limit voltage, control the battery (402) to be charged in the form of pulses after the charging current during the constant voltage charging process is smaller than or equal to a set threshold value, and complete the charging process when the open circuit voltage of the battery (402) is greater than or equal to a preset voltage threshold value.
A power source system (5) comprises a normal mode detecting and controlling circuit (52), a power-saving mode detecting and controlling circuit (51) and an output circuit (53), wherein the power-saving mode detecting and controlling circuit (51) further includes a non-continuous power-saving mode detecting and controlling circuit unit. A method for reducing standby power consumption of the power source system comprises the following step: bias currents in the non-continuous power-saving mode detecting and controlling circuit unit are increased in a first operating mode and decreased in a second operating mode according to the alternate of operating mode of non-continuous power-saving mode detecting and controlling circuit unit in the power-saving mode. Thus, average standby power consumption of the power source system is reduced and the product is energy saving.
A human voice distinguishing method and device are provided. The method involves: taking every n sampling points of the current frame of audio signals as one subsection, wherein n is a positive integer, judging whether two adjacent subsections have transition relative to a distinguishing threshold, wherein the sliding maximum absolute value of the two adjacent subsections is more and less than the distinguishing threshold respectively, if so, then determining the current frame to be human voice, where the sliding maximum absolute value of the subsection is obtained by the following method: taking the maximum value of absolute intensity of every sampling point in this subsection as the initial maximum absolute value of this subsection, and taking the maximum value of the initial maximum absolute value of this subsection and m subsections following this subsection as the sliding maximum absolute value of this subsection, wherein m is a positive integer.
A method and apparatus for recognizing hand-written symbols are disclosed, and the hand-written symbols include at least one basic hand-written symbol. The method includes: acquiring direction features of a sequence of sampling points of the input basic hand-written symbol, recognizing the basic hand-written symbol based on the direction features of the sequence of sampling points.
A method for realizing pin time-share multiplexing which can utilize at least one pin of a system-on-a-chip (SOC) for time-share multiplexing as a first interface mode or a second interface mode, said SOC including a first interface circuit, a first pin, a second interface circuit and a second pin. The first interface circuit includes the first bidirectional solder-pad unit, the first signal interface unit of the first interface mode and the interface unit of said second interface mode. The second interface circuit includes the second bidirectional solder-pad unit and the second signal interface unit of the first interface mode. The method includes: time-share selecting the output port of the first signal interface unit or the output port of the interface unit of the second interface mode to connect with the first pin via the first bidirectional solder-pad unit.
A testing method and system for Advanced High-performance Bus (AHB) in System-On-a-Chip are provided. The method includes the following steps: a microprocessor (11) generates an AHB transmitting signal and transmits it to an encoder (10); the encoder (10) converts the AHB transmitting signal into an interface transmitting signal and transmits it to a testing interface (9); the testing interface (9) converts the received interface transmitting signal into a testing signal to perform the AHB testing. The AHB testing system at least includes: a microprocessor (11) for generating an AHB transmitting signal and transmits it to an encoder (10); an encoder (10) for receiving the AHB transmitting signal, converting the AHB transmitting signal into an interface transmitting signal and transmitting it to a testing interface (9); a test interface (9) for converting the received interface transmitting signal into a testing signal to perform the AHB testing.
A method and a device are provided for correcting and obtaining a reference voltage. The method involves obtaining an actual reference voltage by decoding default codes set in a reference voltage register in a chip. An offset is obtained by comparing the actual reference voltage and a standard value, and a correction code is set according to the offset. The code is burned into a non-volatile storage medium.
A battery charge device and a control method. The battery charge device includes a charging circuit (211) for charging a battery (25) based on a value of a charging current on a charging current set terminal (ISET), a charging current control circuit (212) for gradually regulating the value of the charging current based on a value of an equivalent resistance, and a general purpose register circuit (2411). The value of the equivalent resistance is controlled by a value of an output of the general purpose register circuit (2411). The control method includes a step of setting the value of the output of the general purpose register circuit (2411) based on a maximal load capability of a charge power supply (23) and a charging current needed by the battery (25), and a step of gradually regulating a value of a charging current supplied to the battery (25) based on the value of the output of the general purpose register circuit (2411).
A signal output apparatus, a charge pump, a voltage doubler and a method to output current. They use the interior circuit of a chip to generate an oscillation signal whose swing is between 0 and 2×VIN, and use it to drive a charge pump type voltage doubler which uses a large capacitor outside the chip to output a large current.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
27.
METHOD AND DEVICE FOR INPUTTING THROUGH TOUCH SCREEN
The method and device relate to a data input and transmission technical, particular to an input method and device for inputting through a touch screen, for resolving the problem of prior art which can only calculate the line width according to the user's handwriting pressure and can not realize the user's personal input when inputting through the touch screen. The method comprises: respectively converting an absolute pressure value between the two points obtained through the touch screen and an absolute coordinate value of the two points into a display pressure value and a display coordinate value; calculating an absolute distance value between the two points according to the absolute coordinate value, and converting the absolute distance value into a relative speed value; and determining a display area according to the display coordinate value, display pressure value and relative speed value; coloring the display area. The method can realize the user's personable input.
A vector graphics acceleration method and multimedia player are disclosed, the method includes: decomposing the vector graphics into graphics primitive composed of flat bottom trapezoid or straight lines (S301), passing a decomposition result of the vector graphics to a hardware acceleration logic to process (S302).
The embodiment of the solution provides a method for performing wear leveling in a memory. The method includes: dividing the lifecycle of the memory which includes more than one physical blocks into at least one sampling interval; for each sampling interval, getting the first physical block by taking statistics of the degree of the wear leveling of each physical block in the memory in the current sampling interval; getting the second physical block by taking statistics of the updating times of each logical address in the current sampling interval; exchanging the logical addresses and data of the first physical block and the second physical block. The embodiment of the solution also provides an apparatus corresponding the method.
A playing method of digital right managing DRM multimedia is provided in which the basic unit for files of DRM multimedia to be played is page; when the operation of fast-forward/fast-reverse is trigerred, the method includes: determining the time of fast-forward/fast-reverse, determining the number of pages of fast-forward/fast-reverse based on the time of fast-forward/fast-reverse, determining the page of target playing position based on the number the pages of fast-forward/fast-reverse, calculating key stream of page of the target playing position based on the key data of the prestored first page, decrypting the ciphertext of the page of the target playing position based on the key stream of page of the target playing position, decoding the page of target playing position and playing the decrypted page of target playing position. A playing device is also provided. Therefore, effect of playing can be impoved.
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