A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. The switches are for example transistors or four-layer diodes (e.g. thyristors). The switches are connected to an overlying memory material, e.g. phase-change material, resistance-change material or one-time-programmable material.
H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 17/14 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
CAPACITOR BLOCK COMPRISING CAPACITORS THAT CAN BE CONNECTED TO EACH OTHER AND METHOD FOR CHARGING AND DISCHARGING THE CAPACITORS TO WRITE A PHASE CHANGE MATERIAL MEMORY
An information storage array includes a programmable material at a storage location and a capacitor set. A switching network puts the capacitor set in a first configuration wherein each capacitor of the capacitor set is charged to a first voltage, and puts after the capacitor set in a second configuration such that the capacitor set generates a second voltage. The second voltage is greater than the first voltage and it or a waveform derived therefrom is applied to the storage location to thereby change a state of the programmable material.
G11C 13/02 - Digital stores characterised by the use of storage elements not covered by groups , , or using elements whose operation depends upon chemical change
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
3.
METHOD FOR FORMING SELF-ALIGNED PHASE-CHANGE SEMICONDUCTOR DIODE MEMORY
A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
4.
DIODE DECODER ARRAY WITH NON-SEQUENTIAL LAYOUT AND METHODS OF FORMING THE SAME
In various embodiments, an electronic circuit includes an array of locations each corresponding to an intersection of a row and a column, and a plurality of devices each disposed proximate one of the locations, wherein no more than ten contiguous locations lack a proximate device. In one embodiment a decoder array comprises diodes as decoding elements at said intersections. The invention is to re-order the sequence of rows/columns such that the distribution of decoding elements is essentially regular over the matrix area in order to promote a uniform chemical-mechanical polishing manufacturing step.
In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measureable electrical property of the devices, and/or three-dimensional memory arrays of the same.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non- selected, and a low resistance when connected to the selected row and column.
The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.
G11C 17/06 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using diode elements
G11C 17/10 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 13/02 - Digital stores characterised by the use of storage elements not covered by groups , , or using elements whose operation depends upon chemical change
Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array, using, e.g., a switching element. Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit. Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array, such as a capacitive switching circuit.
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