Abstract

According to one embodiment, provided is a conduction wire including an electrically conductive flat wire, and an insulating film covering the flat wire. Portions of the insulating film covering ends in a width direction of the flat wire are thicker than a portion thereof covering a center in the width direction of the flat wire.

IPC Classes  ?

• H01B 7/02 - Disposition of insulation
• C23C 26/00 - Coating not provided for in groups
• H01B 12/06 - Films or wires on bases or cores
• H01F 5/00 - Coils
• H01F 5/06 - Insulation of windings
• H01F 6/06 - Coils, e.g. winding, insulating, terminating or casing arrangements therefor
• H01F 27/28 - CoilsWindingsConductive connections

Abstract

A solar cell (100) according to an embodiment includes a p-electrode(2), an n-electrode(5), a p-type light-absorbing layer (3) provided on the p-electrode and being mainly composed of a cuprous oxide compound, an n-type layer (4) disposed between the p-type light-absorbing layer (3) and the n-electrode (5), and a compound of first metal (6) provided between the p-type light-absorbing layer (3) and the n-type layer (4). Coverage of the compound of the first metal (6) covering the p-type light absorption layer (3) is 10% or more and less than 100%. The first metal is one or more elements selected from the group consisting of Al, Hf, Zr, and B. The cuprous oxide compound (3) is in direct contact with the compound of the first metal (6) and the n-type layer(4).

IPC Classes  ?

• H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
• H01L 31/072 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
• H01L 31/032 - Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups

Abstract

A sample identification method according to an embodiment includes setting a first reference sequence that includes a first sequence having a single base polymorphic site that is suggested to have a relationship with a disease based on a criterion, the single base polymorphic site being a first base, and a corresponding second reference sequence, outputting the number of first short-chain nucleic acids (the number of ID-2) having the first reference sequence and the number of second short-chain nucleic acids (the number of ID-1) having the second reference sequence, calculating a ratio R = (the number of ID-1/(the number of ID-1 + the number of ID-2)), obtaining a magnitude relationship between the R ratio and a threshold value, and determining, from the number of sequences in which the ratio R is greater than the threshold value, whether or not the sample is derived from a subject having the disease or at risk of developing the disease.

IPC Classes  ?

• C12Q 1/6809 - Methods for determination or identification of nucleic acids involving differential detection
• C12Q 1/6886 - Nucleic acid products used in the analysis of nucleic acids, e.g. primers or probes for diseases caused by alterations of genetic material for cancer
• G16B 30/10 - Sequence alignmentHomology search

Abstract

Provided is a semiconductor device capable of suppressing occurrence of dielectric breakdown. A semiconductor device according to an embodiment comprises a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a gate electrode, a second insulating layer, a third insulating layer, a first field plate electrode, and a fourth insulating layer. The first insulating layer is located between the first electrode and the second electrode in the first direction. The gate electrode is provided on the first insulating layer and includes a first portion and a second portion. A lower surface of the second portion is located above a lower surface of the first portion. The second insulating layer is provided between the first insulating layer and the second portion. The first and second insulating layers include a first insulating material. The third insulating layer is provided on the gate electrode, the first insulating layer, and the second insulating layer. The first field plate electrode is provided on the third insulating layer. The fourth insulating layer is provided on the third insulating layer and the first field plate electrode. The third and fourth insulating layers include a second insulating material.

IPC Classes  ?

• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
• H01L 21/338 - Field-effect transistors with a Schottky gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

A semiconductor device according to an embodiment comprises: a first electrode; a second electrode; and a silicon carbide layer which includes a first silicon carbide region of a first conductivity type, a second silicon carbide region, a third silicon carbide region, and a fourth silicon carbide region of a second conductivity type which are provided between the first silicon carbide region and a first surface, face a gate electrode, and are electrically connected to the first electrode, a fifth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode, and a sixth silicon carbide region of the first conductivity type which is provided between the first silicon carbide region and the first electrode and between the second silicon carbide region and the fourth silicon carbide region, is in contact with the first electrode, is shallower than the depth of the second silicon carbide region, and has a first conductivity type impurity concentration higher than that of the first silicon carbide region.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/8234 - MIS technology
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/872 - Schottky diodes

Abstract

This semiconductor device comprises: a silicon carbide layer that includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type, and a third silicon carbide region of the first conductivity type, and that has a first surface and a second surface; a first gate electrode and a second gate electrode that extend in a first direction; a first electrode located on the first surface side and including a first portion that is in contact with the second silicon carbide region and the third silicon carbide region at locations between the first gate electrode and the second gate electrode, and a second portion that is provided in the first direction of the first portion and is in contact with the first silicon carbide region at a location between the first gate electrode and the second gate electrode; and a second electrode on the second surface side. When the first conductivity-type impurity concentrations are indicated by a logarithmic scale, the distribution of the first conductivity-type impurity concentrations in a direction from the first surface toward the second surface of the third silicon carbide region includes a plurality of inflection points on the side closer to the first surface relative to a first position at which the maximum impurity concentration is shown in the distribution.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 21/8234 - MIS technology
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/47 - Schottky barrier electrodes
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 29/861 - Diodes
• H01L 29/868 - PIN diodes
• H01L 29/872 - Schottky diodes

Abstract

In deep neural network (DNN) speech synthesis, the present invention allows synthesized speech to be adjusted more efficiently with respect to similar adjustment locations. A speech synthesis device of the present embodiment is provided with an encoder, a decoder, and an adjusting unit. The encoder, by means of a first neural network, converts attribute information per speech unit into an intermediate representation. The decoder, by means of a second neural network, generates acoustic-feature volumes from the intermediate representations. The adjusting unit utilizes, with at least the attribute information per speech unit being a key, an adjustment dictionary in which adjustment instructions for the acoustic-feature volumes are made values, to determine a segment to which an adjustment instruction will be applied according to the key, and adjusts the acoustic-feature volume in the determined segment on the basis of the adjustment instruction.

IPC Classes  ?

• G10L 13/10 - Prosody rules derived from textStress or intonation
• G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks

Abstract

The present invention improves the reliability of a semiconductor device. A semiconductor device according to an embodiment comprises: at least one or more first transistors and at least one or more second transistors each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided between a gate end of the at least one or more first transistors and the second node; a sixth transistor provided between a gate end of the at least one or more second transistors and the second node; a seventh transistor provided between a gate end of the at least one or more third transistors and the third node; and an eighth transistor provided between a gate end of the at least one or more fourth transistors and the third node.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

To provide a silicon nitride substrate having improved long-term reliability. According to an embodiment, when a DC electric field of 5 kV/mm is applied to a silicon nitride sintered body at 25°C, the ratio Q25(600)/Q25(5) of the accumulated charge amount 600 seconds from the start of application to the accumulated charge amount 5 seconds from the start of application is 1.0-3.0. The silicon nitride sintered body has thermal conductivity of 65 W/m·K or more.

IPC Classes  ?

• C04B 35/587 - Fine ceramics
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H05K 1/03 - Use of materials for the substrate

Abstract

A semiconductor device according to this embodiment has a circuit board that has a first surface facing a first side and a second surface facing a second side on the reverse side from the first side. The semiconductor device has a chip that is mounted on the first surface. The semiconductor device has a heat transfer member that is bonded to the second surface with a first bonding layer interposed therebetween. The semiconductor device has a heat dissipation member that is bonded to a surface of the heat transfer member, said surface facing the second side, with a second bonding layer interposed therebetween. Each of the first bonding layer and the second bonding layer is a sintered body.

IPC Classes  ?

• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor device comprising: a substrate; a first conductive member provided on a part of the surface of the substrate; a plurality of nitride semiconductor layers provided on the substrate and on the first conductive member and separated from each other; a source electrode provided on the nitride semiconductor layers; a drain electrode provided on the nitride semiconductor layer; a gate electrode provided on the nitride semiconductor layers; and a second conductive member extending between the first conductive member and the source electrode in the nitride semiconductor layers, and electrically connected to the first conductive member and the source electrode.

IPC Classes  ?

• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
• H01L 21/338 - Field-effect transistors with a Schottky gate

Abstract

A film forming apparatus of an embodiment includes an application unit, a drying unit, and a conveyance unit. The application unit applies a raw material liquid to a surface of a substrate, and the drying unit dries the raw material liquid applied to the substrate. The conveyance unit includes a conveyance roll capable of supporting the substrate, and conveys the substrate while passing through an application area in which the raw material liquid is applied and a drying area in which the raw material liquid is dried in order from an upstream side. The conveyance unit conveys the substrate from an upstream end of the application area to a downstream end of the drying area in a state where the substrate does not contact the conveyance roll.

IPC Classes  ?

• B05C 13/02 - Means for manipulating or holding work, e.g. for separate articles for particular articles
• B05C 9/14 - Apparatus or plant for applying liquid or other fluent material to surfaces by means not covered by groups , or in which the means of applying the liquid or other fluent material is not important for applying liquid or other fluent material and performing an auxiliary operation the auxiliary operation involving heating

Abstract

This semiconductor device includes: a nitride semiconductor layer; a plurality of source electrodes extending in a second direction; a plurality of drain electrodes extending in the second direction; a gate electrode provided on the nitride semiconductor layer, located between the source electrode and the drain electrode adjacent to each other in the first direction, and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a source wiring part provided on the insulating layer, the source wiring part having a plurality of source pad parts located apart from each other in the first direction and electrically connected to the source electrode, and a source connection part connecting two source pad parts adjacent to each other in the first direction. The width of the source connection part in the second direction is smaller than the width of the source pad part in the second direction.

IPC Classes  ?

• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
• H01L 21/338 - Field-effect transistors with a Schottky gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

Provided is a semiconductor device capable of reducing leakage current. The semiconductor device according to an embodiment comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a second electrode, and a fifth semiconductor region of the second conductivity type. The first semiconductor region includes a first portion and a second portion provided around the first portion. The second semiconductor region is provided over the first portion. The fourth semiconductor region is provided over the second portion. The second electrode includes a first metal part and a second metal part. The first metal part is in contact with the first portion and the second semiconductor region. The second metal part is in contact with the second portion and the fourth semiconductor region. The first metal part and the second metal part include at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The fifth semiconductor region is provided below the fourth semiconductor region and is located directly below the second metal portion.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 21/8234 - MIS technology
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/47 - Schottky barrier electrodes
• H01L 29/872 - Schottky diodes

Abstract

A semiconductor device according to one embodiment of the present invention comprises: a first metal layer; a semiconductor chip that includes an upper electrode, a lower electrode, a semiconductor layer provided between the upper electrode and the lower electrode, and a first resin layer provided on the upper electrode and containing a first resin; a second metal layer that is provided between the first metal layer and the lower electrode and contains silver (Ag) or copper (Cu); a second resin layer that is annular, covers the outer peripheral part of the semiconductor chip, and contains a second resin different from the first resin; and a third resin layer that is provided between the first resin layer and the second resin layer and contains a third resin different from the first resin and the second resin.

IPC Classes  ?

• H01L 21/58 - Mounting semiconductor devices on supports
• H01L 21/52 - Mounting semiconductor bodies in containers

Abstract

The present invention provides a semiconductor device that can achieve improved characteristics. According to an embodiment, this semiconductor device includes first through third electrodes, first through fourth semiconductor members, and a first insulating member. The first semiconductor member is provided between the first and second electrodes, and is of a first conductivity type. The first semiconductor member includes first through third partial regions. A second direction stretching from the first partial region to the second partial region intersects a first direction stretching from the first electrode to the second electrode. The direction stretching from the first partial region to the third partial region aligns with the first direction. The second semiconductor member is of a second conductivity type. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member is of the first conductivity type. The second semiconductor region is provided between the second partial region and the fourth semiconductor member in the first direction. The fourth semiconductor member is of the first conductivity type or does not contain impurities of the second conductivity type. The third partial region is provided between the first partial region and the third electrode in the first direction.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/47 - Schottky barrier electrodes
• H01L 29/872 - Schottky diodes

Abstract

The present invention detects a problem that is difficult to sense by using a picking robot, and updates inventory information in a warehouse system in accordance with the problem.　An article inspection device according to an embodiment comprises: a reception unit that, on the basis of an order list, receives an inspection instruction including an article ID of an article picked up by a picking robot and the weight of the article; a weight sensor that measures the weight of the article; a determination unit that determines whether a problem occurs in the article on the basis of the weight of the article included in the inspection instruction and the measured weight of the article; a generation unit that generates an inspection result corresponding to the determination; and a transmission unit that transmits the result of inspection.

IPC Classes  ?

• B65G 1/137 - Storage devices mechanical with arrangements or automatic control means for selecting which articles are to be removed

Abstract

A semiconductor device according to this embodiment comprises: a substrate; first through fourth conductive parts that are provided on the substrate; a first transistor that has a drain connected to the first conductive part and a source connected to the second conductive part; and second and third transistors that each have a drain connected to the second conductive part, a source connected to the third conductive part, and a gate connected to the fourth conductive part. The second conductive part includes a first section and a second section that are respectively in contact with the second and third transistors. The third conductive part includes a third section and a fourth section to which the sources of the second and third transistors are respectively connected, and a fifth section that is electrically connected to the third and fourth sections. The fourth conductive part includes a sixth section and a seventh section to which the gates of the second and third transistors are respectively connected, and an eighth section that is electrically connected to the sixth and seventh sections. The shape of the eighth section is different from the shapes of the sixth section and the seventh section.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

According to an embodiment of the present invention, a semiconductor device includes: a first substrate provided with a first electrode, a second electrode, and a third electrode; a second substrate provided with a fourth electrode, a fifth electrode, and a sixth electrode and disposed side by side with the first substrate in a first direction; a first transistor having a drain connected to the first electrode, a gate connected to the second electrode, and a source connected to the third electrode; a second transistor having a drain connected to the fourth electrode, a gate connected to the fifth electrode, and a source connected to the sixth electrode; a first wiring connecting the second electrode and the fifth electrode in a meandering manner in a second direction; and a second wiring connecting the third electrode and the sixth electrode in a meandering manner in the second direction.

IPC Classes  ?

• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

[Problem] To provide a semiconductor device having a small output capacity. [Solution] A semiconductor device according to the present embodiment comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, and a third electrode. The first nitride semiconductor layer is provided on the substrate. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The substrate is configured in accordance with the position of the second electrode. The substrate includes at least one of a first insulating layer and a first air layer which are each a region having a dielectric constant lower than that of the substrate.

IPC Classes  ?

• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
• H01L 21/338 - Field-effect transistors with a Schottky gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

Provided is a semiconductor device capable of achieving high breakdown voltage while suppressing an increase in on-resistance. A semiconductor device according to an embodiment of the present invention comprises a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a third electrode, an electrode part, and a region. The second nitride semiconductor layer is provided on the first nitride semiconductor layer, and has a band gap larger than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The electrode part is electrically connected to at least one of the first electrode, the second electrode, and the third electrode, and is disposed above the third electrode. Said region is a region in which a fixed charge of negative charge separated from the third electrode is introduced into the second nitride semiconductor layer.

IPC Classes  ?

• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
• H01L 21/338 - Field-effect transistors with a Schottky gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

Abstract

Provided is a ceramic scribe substrate from which multiple parts having minimal burrs or chipping at the time of division can be obtained. The ceramic scribe substrate has a side scribe line and a corner scribe line, and an auxiliary scribe line crossing an intersection of the corner scribe line and the side scribe line along the side scribe line is formed in the vicinity of the intersection. The length of the auxiliary scribe line is 0.5 mm or more and 15.0 mm or less, and the side scribe line and the auxiliary scribe line are formed by dots.

IPC Classes  ?

• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H05K 1/02 - Printed circuits Details

Abstract

3222-type crystal phase.

IPC Classes  ?

• H01F 1/01 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials

Abstract

A method for filling a ceramic molded body according to an embodiment fills a plurality of pre-treatment molded bodies, which are molded bodies before CIP treatment, into a plurality of holes formed in a CIP rubber mold, and has a placement step, an input step, and an operation execution step. In the placement step, a fall prevention frame is placed on the edge of the CIP rubber mold. In the input step, the plurality of pre-treatment molded bodies are input into the CIP rubber mold with the fall prevention frame in place. The operation execution step executes an operation of fitting the pre-treatment molded bodies which are not fitted into any of the plurality of holes formed in the CIP rubber mold with the fall prevention frame in place, among the plurality of pre-treatment molded bodies.

IPC Classes  ?

• B28B 3/00 - Producing shaped articles from the material by using pressesPresses specially adapted therefor
• B28B 1/087 - Producing shaped articles from the material by vibrating or jolting by means acting on the mould
• B28B 7/34 - Moulds, cores, or mandrels of special material, e.g. destructible materials
• F16C 33/32 - Balls

Abstract

A method for producing a ceramic granulated powder according to an embodiment comprises a first slurry preparation step, a first granulation step, a cyclone recovery step, a spray-dry recovery step, a first slurry preparation step, and a first granulation step. In the first slurry preparation step, a first slurry comprising a first mixture that contains a first powder is prepared. In the first granulation step, a first ceramic granulated powder containing the first mixture is produced by granulating the first slurry. In the cyclone recovery step, a cyclone reuse powder is acquired during or after the first granulation step. In the spray-dry recovery step, a spray-dry reuse powder is acquired after the first granulation step. In the second slurry preparation step, a second slurry comprising a second mixture obtained by mixing both reuse powders is prepared. In the second granulation step, a second ceramic granulated powder containing the second mixture is produced by granulating the second slurry.

IPC Classes  ?

• C04B 35/626 - Preparing or treating the powders individually or as batches
• B01J 2/04 - Processes or devices for granulating materials, in generalRendering particulate materials free flowing in general, e.g. making them hydrophobic by dividing the liquid material into drops, e.g. by spraying, and solidifying the drops in a gaseous medium
• C04B 35/587 - Fine ceramics
• F16C 33/32 - Balls

Abstract

A semiconductor device comprising: a substrate; a gallium nitride layer that is provided on a non-polar surface of the substrate and has a plurality of fin parts that are positioned apart from each other in a first direction parallel to the c-axis direction, and extend in a second direction orthogonal to the first direction; an electron supply layer provided on the Ga-surface of the fin parts; a gate electrode positioned between the source finger part and the drain finger part in the second direction, and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 21/338 - Field-effect transistors with a Schottky gate
• H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate

Abstract

Provided are an inspection device, an inspection system, an inspection method, and a semiconductor device manufacturing method which are capable of improving efficiency. According to an embodiment, this inspection device includes a control unit electrically connected to a semiconductor device. The semiconductor device includes a semiconductor member, a transistor part, and a diode part. The transistor part includes a source electrode, a drain electrode, and a gate electrode. The control unit can perform a first operation, a first elapsed operation, a second operation, and a first determination operation. In the first operation, the control unit sets the gate electrode to an ON potential and detects the drain potential in a state in which a current source is connected to the drain electrode. In the first elapsed operation, the control unit sets the gate electrode to an OFF potential in a state in which the current source is connected to the drain electrode. In the second operation, the control unit sets the gate electrode to an ON potential and detects the drain potential. In the first determination operation, the control unit inspects the semiconductor device on the basis of the difference between detection values.

IPC Classes  ?

• G01R 31/26 - Testing of individual semiconductor devices

Abstract

The present invention provides a semiconductor device capable of improving characteristics. According to an embodiment, this semiconductor device includes first to third electrodes, first to fifth semiconductor members, and a first insulating member. The first semiconductor member is of a first conductivity type. A sixth partial region of the first semiconductor member comes into Schottky contact with the second electrode. The second semiconductor member is of a second conductivity type. The third semiconductor member is of the first conductivity type. The fourth semiconductor member is of the second conductivity type. The fifth semiconductor member is of the second conductivity type. A fifth impurity concentration of the second conductivity type in the fifth semiconductor member is lower than a fourth impurity concentration of the second conductivity type in the fourth semiconductor member.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

An electric power system according to an embodiment of the present disclosure is provided with one or more pieces of equipment connected to an electrical grid and a grid control device which is connected to the one or more pieces of equipment over a network and which controls the electrical grid, the electric power system comprising: a first processing unit that repeatedly acquires harmonic information over time or when the electrical grid or the equipment changes state, the harmonic information being information pertaining to harmonics of frequencies other than the fundamental frequency of the electrical grid, based on voltage or current in the equipment or the operation or control of the equipment; and an evaluation unit that evaluates the stability of the electrical grid with respect to the harmonics on the basis of the harmonic information.

IPC Classes  ?

• H02J 13/00 - Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the networkCircuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
• H02J 3/01 - Arrangements for reducing harmonics or ripples
• H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers

Abstract

An information processing device according to an embodiment generates a production plan representing a plan for producing a plurality of products by a production plant on the basis of a solution of a production planning problem, generates an energy planning problem on the basis of the production plan, and generates an energy supply plan representing a plan for operating an energy plant that consumes a first energy and supplies a second energy to the production plant on the basis of a solution of the energy planning problem. The production planning problem is a problem of minimizing the time-series energy difference between time-series target energy and time-series consumption energy consumed when the production plant produces the plurality of products, and a solution representing the production plan is obtained. The energy planning problem is a problem of minimizing the first energy under the condition that the second energy of the time series consumed when the production plant is operated according to the production plan is at least supplied to the production plant, and a solution representing the energy supply plan is obtained.

IPC Classes  ?

• H02J 3/00 - Circuit arrangements for ac mains or ac distribution networks
• G06Q 50/06 - Energy or water supply

Abstract

Provided is a gas-insulated bus in which reduction in bus diameter can be easily achieved. The gas-insulated bus according to an embodiment comprises a metal container, an energization conductor, and an insulating spacer. The metal container is formed into a tubular shape, and an insulating gas is sealed in the internal space thereof. The energization conductor is housed in the internal space of the metal container so as to extend along the axial direction of the metal container. The insulating spacer supports the energization conductor in the internal space of the metal container so that the metal container and the energization conductor are electrically insulated from each other. The metal container has: a first container body part; a second container body part installed so as to be aligned with the first container body part in the axial direction; and an intermediate ring member interposed between the first container body part and the second container body part in the axial direction. The insulating spacer is installed on the inner peripheral surface of the intermediate ring member, and the insulating spacer and the intermediate ring member are fastened to each other in the radial direction by using a fastening member.

IPC Classes  ?

• H02G 5/06 - Totally-enclosed installations, e.g. in metal casings
• H02B 13/045 - Details of casing, e.g. gas tightness

Abstract

A semiconductor device according to an embodiment comprises: a first conductor which is exposed at a first surface of a package; first and second transistors, drains of which are connected to the first conductor; an insulation substrate; a second conductor and a third conductor which are exposed at a second surface of the package and which are provided on a third surface of the insulation substrate; a first wiring layer which is embedded in the insulation substrate and which is connected to the second conductor; a fourth conductor which is connected to the third conductor and to a source of the first transistor; a fifth conductor which is connected to the third conductor and to a source of the second transistor; a sixth conductor which is connected to the second conductor and to a gate of the first transistor; and a seventh conductor which is provided on a fourth surface of the insulation substrate and which is connected to the first wiring layer and to a gate of the second transistor.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures

Abstract

A semiconductor device according to an embodiment of the present invention includes: a silicon carbide layer which has a first surface and a second surface; a first trench and a second trench, which extend in a first direction; a gate electrode; a gate insulating layer; an n-type first silicon carbide region; a p-type second silicon carbide region which is located between the first silicon carbide region and the first surface, and which is shallower than the trenches; a plurality of n-type third silicon carbide regions and a plurality of p-type fourth silicon carbide regions, which are located between the second silicon carbide region and the first surface, and which are alternately formed in the first direction; an n-type fifth silicon carbide region which is located between the first trench and the second trench and between the second silicon carbide region and the third silicon carbide region and the fourth silicon carbide region, and which is in contact with the first trench and extends in the first direction; and an n-type sixth silicon carbide region which is located so as to be separated from the fifth silicon carbide region in a second direction that is perpendicular to the first direction, and which is in contact with the second trench and extends in the first direction.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

Abstract

A granulated particle (100) for cold storage particles of an embodiment includes: a first region (10a) having a first void fraction; and a second region (10b) that is closer to an outer edge of the particle than the first region (10a) and has a second void fraction lower than the first void fraction.

IPC Classes  ?

• H01F 1/01 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials

Abstract

In an arbitrarily defined cross-section passing through the center of gravity of a ceramic sintered body according to an embodiment of the present invention, when a portion on the surface side is defined as a surface part and a portion centered at the center of gravity and existing within a radius of 1 mm is defined as a center-of-gravity part, and when an X-Ray Diffractometers (XRD) analysis is performed on the surface part and the center-of-gravity part, detection positions of the top four peaks in a descending order of the intensities of peaks detected within a diffraction angle range of 10-60° are the same between the surface part and the center-of-gravity part within a range of ±0.5°. The surface part is suitably set at a portion 0.5-1.0 mm from the surface.

IPC Classes  ?

• C04B 35/596 - Composites
• C04B 35/117 - Composites
• C04B 35/645 - Pressure sintering
• F16C 19/52 - Bearings with rolling contact, for exclusively rotary movement with devices affected by abnormal or undesired conditions
• F16C 33/32 - Balls

Abstract

An information processing device according to the present invention comprises a processing unit. The processing unit: selects a plurality of pieces of common data that are associated with feature information that is the same or similar to designated first feature information from a plurality of pieces of common data that are time-series data that indicate changes in the charging/discharging of a battery and are associated with different feature information that indicates features of the charging/discharging; and synthesizes the selected plurality of pieces of common data to generate first time-series data for the first feature information.

IPC Classes  ?

• G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
• G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
• G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health

Abstract

The present invention provides a semiconductor device which is capable of achieving stable characteristics. According to an embodiment of the present invention, a semiconductor device includes an element part. The element part includes a semiconductor member that includes a pad part semiconductor region and a cell semiconductor region, a gate electrode, and a gate pad part which is electrically connected to the gate electrode. The gate pad part includes a first conductive member and a first member that is provided between the pad part semiconductor region and the first conductive member. The first member includes a first region and a second region, which are aligned in a second direction that intersects with a first direction from the pad part semiconductor region to the first conductive member. At least a part of the first conductive member is located between the first region and the second region. A first surface of the at least a part of the first conductive member includes first irregularities.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

Provided is a portable electronic device on which a prescribed encryption algorithm can be installed using limited hardware resources.　A portable electronic device according to an embodiment comprises a memory, an interface, and a processor. The memory stores encryption information including an encryption algorithm. The interface communicates with an information processing device. The processor generates a random number. The interface transmits the encryption information to the information processing device, and receives a public key transmitted by the information processing device from among public keys and secret keys generated on the basis of the encryption algorithm. The processor generates an encrypted random number from the random number by means of encryption processing based on the aforementioned public key. The interface transmits the encrypted random number to the information processing device. The processor generates, on the basis of the random number, a session key to be used for communication with the information processing device.

IPC Classes  ?

• H04L 9/08 - Key distribution

Abstract

The present invention improves characteristics. According to one embodiment of the present invention, in a first semiconductor part of a semiconductor device, a second direction from a first partial region to a second partial region intersects with a first direction from a first electrode to a second electrode, a direction from the first partial region to a third partial region extends along the first direction, a third direction from the second partial region to a fourth partial region intersects with the first direction and a plane that includes the second direction, a direction from the fourth partial region to a fifth partial region extends along the first direction, a direction from the second partial region to a sixth partial region extends along the first direction, a direction from the fourth partial region to the sixth partial region extends along the third direction, the concentration of an impurity having a first conductivity type in the sixth partial region is higher than the concentration of the impurity having the first conductivity type in the first partial region, the second partial region, the third partial region, the fourth partial region, and the fifth partial region, and the fifth partial region and the second electrode are in a Schottky contact with each other.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/872 - Schottky diodes

Abstract

The present invention provides a semiconductor device that makes it possible to improve withstand voltage. A semiconductor device according to one embodiment comprises first to third electrodes and first and second semiconductor parts. The first semiconductor part is of a first conductivity type. The first semiconductor part includes first to third semiconductor regions. The concentration of impurities of the first conductivity type in the second and third semiconductor regions is higher than the concentration of impurities of the first conductivity type in the first semiconductor region. The second semiconductor part includes first to fourth portions. The first to third portions are provided to a cell part. The first portion and the third portion have a first depth. The second portion is provided between the first portion and the third portion. The second portion has a second depth which is shallower than the first depth. The first portion is provided on the second semiconductor region. The fourth portion is provided on the third semiconductor region.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/872 - Schottky diodes

Abstract

According to an embodiment, a portable electronic device comprises an interface, a memory, and a processor. The interface communicates with an external device. The memory stores setting information for each of a plurality of different processing methods for executing specific processing. The processor selects one processing method for executing specific processing in accordance with information supplied from the external device, and executes the specific processing using the selected processing method.

IPC Classes  ?

• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms

Abstract

A speech processing assistance device (10) comprises: an input reception unit (20B); and a recording unit (20F). The input reception unit (20B) receives input of parameters including at least a plurality of mutually different emotion types and a mixing ratio of a plurality of types of emotions during reproduction of speech data to be edited. The recording unit (20F) records the parameters, which have been received as the input, in association with a reproduction timing when the input of the parameters has been received in the speech data.

IPC Classes  ?

• G10L 13/10 - Prosody rules derived from textStress or intonation

Abstract

Provided are: an inspection processing device capable of improving efficiency; and a semiconductor device manufacturing method. According to an embodiment, an inspection processing device includes a storage unit and a processing unit. The storage unit is capable of storing a feature value distribution that includes first and second feature value distribution regions pertaining to a target device. The processing unit is capable of performing a current first inspection pertaining to the target device on the basis of the first and second feature value distribution regions which are stored in the storage unit. The feature value distribution pertains to a first past inspection result of a past first inspection pertaining to the target device, and to a second past inspection result. The second past inspection result is acquired by means of a second inspection which is subsequent to past first processing and which is performed after the past first inspection. A first defect rate of the second past inspection result corresponding to the first feature value distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature value distribution region.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

Provided are: a silicon nitride substrate produced by excellent lamination of green sheets; and a method for producing the same. The silicon nitride substrate according to one embodiment, when observed in cross section in a dark field of an optical microscope, includes a main layer and an intermediate layer that is darker than the main layer. The colour difference between the main layer and the intermediate layer is 0.1 or more. In the thickness direction, m+1 main layers and m intermediate layers are alternately arranged. The colour difference between the n-th (n is an integer) main layer and the n-th intermediate layer from one surface is defined as CDna. The colour difference between the (n+1)-th main layer and the n-th intermediate layer is defined as CDnb. A first condition and a second condition are satisfied with any value for n of 1 to m. The first condition is that, in a first direction parallel to the cross section and perpendicular to the thickness direction, a region where 0.1 ≤ CDna ≤ 1.4 is present over a range of 100 μm or more. The second condition is that, in the first direction, a region where 0.1 ≤ CDnb ≤ 1.4 is present over a range of 100 μm or more.

IPC Classes  ?

• C04B 35/587 - Fine ceramics
• B28B 3/12 - Producing shaped articles from the material by using pressesPresses specially adapted therefor wherein one or more rollers exert pressure on the material
• B32B 18/00 - Layered products essentially comprising ceramics, e.g. refractory products
• H05K 1/03 - Use of materials for the substrate

Abstract

A ceramic scintillator array 1 according to an embodiment of the present invention is provided with a plurality of scintillator segments 2 and a reflection layer. The amount of chlorine contained in the reflection layer is 3000 µg/g or less.

IPC Classes  ?

• G01T 1/20 - Measuring radiation intensity with scintillation detectors

Abstract

20.5°22.8°34.3°38.7°3433.6°36.1°233431.8°37.2°20.5°22.8°34.3°38.7°33.6°36.1°31.8°37.2°33.6°36.1°36.1°)≤0.100 is satisfied.

IPC Classes  ?

• C04B 35/596 - Composites
• F16C 19/06 - Bearings with rolling contact, for exclusively rotary movement with bearing balls essentially of the same size in one or more circular rows for radial load mainly with a single row of balls
• F16C 33/32 - Balls

Abstract

Provided is a gas insulated busbar for which it is possible to easily improve durability. A gas insulated busbar according to an embodiment includes: an A-axis extension portion extending along an A-axis; a B-axis extension portion extending along a B-axis different from the A-axis; and a C-axis extension portion extending along a C-axis different from the A-axis and the B-axis. The A-axis extension portion is provided at one end of the B-axis extension portion, and the C-axis extension portion is provided at the other end of the B-axis extension portion. The C-axis extension portion is provided with a C-axis rotary sliding part configured to rotate about the C-axis as a rotation center axis when the A-axis extension portion is thermally shrunk along the A-axis.

IPC Classes  ?

• H02G 5/08 - Connection boxes therefor
• H02B 13/045 - Details of casing, e.g. gas tightness

Abstract

This semiconductor device includes: a silicon carbide layer which has an element region and a termination region that surrounds the element region, the silicon carbide layer including a first semiconductor part that has a first conductivity type and includes a first portion in the element region, and a second semiconductor part that is provided on the first semiconductor part in a first direction and is adjacent to the first portion in a second direction that is orthogonal to the first direction; a gate electrode which faces the second semiconductor part in the element region; a first insulating film which is provided between the gate electrode and the silicon carbide layer; and a second insulating film which is provided on the first portion of the first semiconductor part, and which is thicker than the first insulating film.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/861 - Diodes
• H01L 29/868 - PIN diodes

Abstract

Provided is a semiconductor device capable of suppressing the occurrence of destruction. This semiconductor device is provided with a first electrode, a semiconductor layer, a second electrode, a gate electrode, and a third electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type, and contains silicon carbide. The gate electrode faces the second semiconductor region across a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The gate electrode includes a first portion additionally facing the third semiconductor region, a second portion located at an end portion of the gate electrode in a third direction perpendicular to the first direction and the second direction, and a third portion located between the first portion and the second portion in the third direction. The impurity concentration of the second portion is lower than the impurity concentration of the third portion. The third electrode is electrically connected to the gate electrode and is spaced apart from the second electrode.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

A laser welding method according to an embodiment comprises: a step for irradiating alternately an end portion of a first linear member and an end portion of a second linear member adjacent to the first linear member with laser light to form a first molten pool spreading over the end portion of the first linear member and the end portion of the second linear member; and a step for irradiating the first molten pool with the laser light. In the step for irradiating the first molten pool with the laser light, the center side of the first molten pool is set as a starting point of the irradiation of the laser light, and, as the irradiation position of the laser light rotates around the starting point, the irradiation position of the laser light gradually moves away from the starting point, or moves away from the starting point step-by-step.

IPC Classes  ?

• B23K 26/21 - Bonding by welding

Abstract

A method for producing a rotary electrical machine in accordance with an embodiment comprises: a step for providing, to each of a plurality of slots provided to a core, a segment which has a first conductor part and a first insulation part that is provided to the outer surface of the first conductor part; a step for providing, to the core, a terminal which has a second conductor part and a second insulation part that is provided to the outer surface of the second conductor part; a step for performing laser welding of end portions of a pair of adjacent first conductor parts so as to form a coil which is provided to each of the slots; and a step for performing laser welding of a plate-like bus bar to an end portion of the second conductor part. The bus bar has a hole which passes therethrough in the thickness direction. In the step for performing the laser welding of the bus bar, the end portion of the second conductor part is inserted into the hole in the bus bar.

IPC Classes  ?

• H02K 15/085 - Forming windings by laying conductors into or around core parts by laying conductors into slotted stators
• H02K 3/50 - Fastening of winding heads, equalising connectors, or connections thereto

Abstract

[Problem] To provide a semiconductor device having low inductance. [Solution] A semiconductor device according to an embodiment includes: a first circuit board having a plurality of first semiconductor elements; a second circuit board having a plurality of second semiconductor elements; and an output terminal that connects second output wiring of the second circuit board to first output wiring of the first circuit board and has a flat surface part, a first leg part, a second leg part, and a first bridge part, wherein the first leg part is connected to the first output wiring, the second leg part is connected to the second output wiring, and the first leg part and the second leg part are connected by the first bridge part.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

This method for manufacturing a semiconductor device comprises: a step for forming a SiC layer on a single crystal SiC layer of a substrate having a polycrystalline SiC substrate, which has a first surface and a second surface, and a single crystal SiC layer, which is provided on the second surface; a step for forming a first insulating film and a second insulating film on the SiC layer, the first insulating film and second insulating film being spaced a third width apart in a first direction parallel to the second surface; a step for removing a first portion, which extends in a second direction parallel to the second surface and crossing the first direction, and a second portion, which is provided on the first portion and extends in the second direction, of the SiC layer below the space between the first insulating film and the second insulating film, thereby forming a second groove which has a second width narrower than the third width in the first direction, extends in the second direction, and cuts the single crystal SiC layer and the SiC layer, and in which the polycrystalline SiC substrate is exposed at the bottom; and a step for forming, through dicing, a first groove which is provided below the second groove, has a first width narrower than the second width in the first direction, extends in the second direction, and cuts the polycrystalline SiC substrate.

IPC Classes  ?

• H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
• H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

In a communication device according to an embodiment, a signal reception unit converts an OFDM signal into an OFDM signal of a baseband. A time waveform computation unit extracts a part of a time-axis waveform signal and calculates the degree of similarity to a known signal. A carrier frequency correction unit corrects a carrier frequency of the time-axis waveform signal on the basis of the degree of similarity. An FFT unit performs Fourier transform on the time-axis waveform signal. A frequency waveform computation unit extracts a part of a frequency-axis waveform signal, and calculates the degree of similarity between the extracted signal and a known signal. A switching timing estimation unit estimates, on the basis of a result from the frequency waveform computation unit, a timing for switching between uplink communication and downlink communication in the device.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04B 7/022 - Site diversityMacro-diversity
• H04W 56/00 - Synchronisation arrangements

Abstract

2233 is present in the insulating gas in a measurement area of the sealed container.

IPC Classes  ?

• G01R 31/12 - Testing dielectric strength or breakdown voltage

Abstract

Provided is a cutoff device comprising sufficient withstand voltage performance and energization performance even when a vacuum circuit breaker is used. In a cutoff device according to an embodiment, a first cutoff contact is connected in parallel with an energization contact. A second cutoff contact is connected in parallel with the energization contact and is connected in series to the first cutoff contact. The resistance of the energization contact is less than the resistance of the first cutoff contact and the resistance of the second cutoff contact. In an energized state, the energization contact, the first cutoff contact, and the second cutoff contact are in a closed state, and a greater current flows through the energization contact than through the first cutoff contact and the second cutoff contact. In a cutoff state, after the energization contact is switched from the closed state to an open state, the first cutoff contact and the second cutoff contact are switched from the closed state to the open state. At least one of the first cutoff contact and the second cutoff contact is configured from a vacuum circuit breaker that switches between the closed state and the open state inside a vacuum container.

IPC Classes  ?

• H01H 33/42 - Driving mechanisms
• H01H 33/64 - Switches wherein the means for extinguishing or preventing the arc do not include separate means for obtaining or increasing flow of arc-extinguishing fluid wherein the break is in gas
• H01H 33/66 - Vacuum switches
• H02B 13/035 - Gas-insulated switchgear

Abstract

A semiconductor device according to one embodiment of the present invention includes a body part having: a substrate; and a chip mounted on a device surface, which is one of the outer surfaces of the substrate and faces one side in a first direction. Provided is a housing that accommodates the body part. Provided is a heat transfer pin. The housing has a lid member facing the device surface. The heat transfer pin is held by the lid member and extends from the lid member toward the chip.

IPC Classes  ?

• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation

Abstract

[Problem] To realize output control of a weather alert utilizing weather-related posted information that is posted by contributors. [Solution] A weather management system according to an embodiment of the present invention performs an analysis process for analyzing weather observation data and outputting, on the basis of prescribed criteria, precipitation particles that will fall onto the ground, and outputs alert information in accordance with the result of the analysis process. The prescribed criteria used in the analysis process can be changed on the basis of weather-related posted information that is posted from a contributor terminal. The system stores effective time periods and effective areas that have been set for each prescribed posting area in accordance with prescribed posting time windows. By performing, during an effective time period corresponding to the posting time of weather-related posted information, an analysis process in which changed prescribed criteria are applied to observation data that is located within an effective area from the posting location of the weather-related posted information, appropriate disaster prevention alerts accounting for the posting frequency of weather-related posted information can be provided.

IPC Classes  ?

• G06Q 50/10 - Services
• G01W 1/02 - Instruments for indicating weather conditions by measuring two or more variables, e.g. humidity, pressure, temperature, cloud cover or wind speed
• G01W 1/10 - Devices for predicting weather conditions
• G06Q 50/26 - Government or public services

Abstract

Provided is a method for manufacturing a semiconductor device by which characteristics can be improved. According to one embodiment, a method for manufacturing a semiconductor device involves forming a first metal layer containing a first metal element on a first surface of a structure including a substrate including SiC and including a first surface. The manufacturing method includes injecting a first element containing at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si to the first surface through the first metal layer. The manufacturing method involves irradiating the first surface with a laser through the first metal layer after the injection.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/45 - Ohmic electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a base substrate; a case provided on the upper surface of the base substrate; a first laminate provided inside the case on the upper surface of the base substrate; a second laminate provided apart from the first laminate on the upper surface of the base substrate; and a flat plate-like first conductor having a first part in contact with the first laminate and a second part in contact with the second laminate. The first laminate includes a first insulator, a second conductor provided on the upper surface of the first insulator and brought into in contact with the first part of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second laminate includes a second insulator and a third conductor provided on the upper surface of the second insulator and brought into contact with the second part of the first conductor, and does not include a semiconductor element.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

Provided is a highly reliable semiconductor device. A semiconductor device according to an embodiment comprises: pellets; a first conductor and a second conductor that sandwich the pellets in a first direction; a first joint material that joins the pellets and the first conductor; and a second joint material that joins the pellets and the second conductor, wherein a first surface of the first conductor facing the pellets has a plurality of projections overlapping with the pellets and a groove provided so as to surround the pellets when viewed in the first direction, a design value of the height of the plurality of projections is a first value, and the volume of the groove is based on the volume of a portion that is sandwiched between the pellets and the first conductor when a first height between the pellets and the first conductor is a second value that is greater than the first value.

IPC Classes  ?

• H01L 21/52 - Mounting semiconductor bodies in containers

Abstract

A semiconductor device manufacturing method according to an embodiment includes a first attaching step, a grinding step, a singulation step, and a support substrate separation step. The first attaching step is a step for attaching, to a support substrate, a device surface on which a circuit pattern of a base material made of a semiconductor material is formed. The grinding step is a step for grinding the surface on the opposite side to the device surface while the device surface is supported by the support substrate. The singulation step is a step for cutting the base material while the base material is supported by the support substrate, and singulating the base material. The support substrate separation step is a step for separating the support substrate from the base material.

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions

Abstract

[Problem] To provide a semiconductor device manufacturing method and a semiconductor substrate in which a mark of the semiconductor substrate can be identified with certainty. [Solution] A semiconductor device manufacturing method according to the present embodiment involves forming a first mark (10) that is recessed in a first direction approximately orthogonal to a first surface of an SiC substrate, is surrounded on the first surface by first and third sides, extending in a second direction orthogonal to the first direction, and second and fourth sides, extending in a third direction orthogonal to the first and second directions, and has, in the first side, at least one recessed pattern recessed in the third direction from the first side toward the third side opposite the first side. An SiC layer is epitaxially grown on the first mark (10) of the SiC substrate.

IPC Classes  ?

• G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
• C30B 29/36 - Carbides
• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/872 - Schottky diodes
• H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes

Abstract

The present invention provides a semiconductor device in which the occurrence of destruction can be suppressed. A semiconductor device according to an embodiment of the present invention includes a first electrode, a semiconductor layer, a second electrode, a first insulating part, and a second insulating part. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer and contains aluminum. The first insulating part includes a first portion and a second portion. The first portion is provided between the semiconductor layer and an outer peripheral part of the second electrode. The second portion is provided around the first portion along a first surface that is perpendicular to a first direction extending from the first electrode toward the semiconductor layer, and a protrusion is provided on the upper surface thereof. The second insulating part is provided on the outer peripheral part of the second electrode and the second portion.

IPC Classes  ?

• H01L 29/861 - Diodes
• H01L 29/868 - PIN diodes
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

Abstract

A semiconductor device according to an embodiment comprises: an insulating substrate having a circuit pattern; a semiconductor chip fixed onto the insulating substrate and electrically connected to the circuit pattern; and a power supply terminal containing a metal that is of the same type as the circuit pattern, the power supply terminal being electrically connected to the circuit pattern. The power supply terminal includes: a flat plate-form joint portion joined to the circuit pattern; a penetration portion penetrating the joint portion in the thickness direction of the joint portion; and an extension portion that is bent from one end portion of the joint portion and extends upward, the extension portion being configured to be capable of connecting the circuit pattern and an external device. The joint portion and the circuit pattern are joined by a bonding material containing metal particles of the same type as the power supply terminal and the circuit pattern.

IPC Classes  ?

• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates

Abstract

[Problem] To provide a semiconductor device in which the structure is simplified and the performance is improved. [Solution] A semiconductor device according to the present embodiment comprises a first insulating substrate having a first surface and a second surface that is on the opposite side from the first surface. First and second conductive layers are provided on the first surface side. A plurality of semiconductor chips include a third surface that faces the first surface, a fourth surface that is on the opposite side from the third surface, a first electrode that is on the third surface, and a second electrode that is on the fourth surface. The first electrode is electrically connected to the first conductive layer. A common electrode plate has a fifth surface that faces the fourth surface, is electrically connected to the second electrodes of the plurality of semiconductor chips, and is electrically connected to the second conductive layer. A second insulating substrate is provided on the second surface side of the first insulating substrate.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

This method for manufacturing a silicon carbide epitaxial wafer comprises: a step for epitaxially growing silicon carbide at a first growth rate of 0.5-2 μm/h on a silicon carbide wafer to form a first silicon carbide layer that has a film thickness of 1-100 nm and a bump density of a first density; and a step for epitaxially growing silicon carbide at a second growth rate of more than 2 μm/h but not more than 100 μm/h on the first silicon carbide layer to form a second silicon carbide layer that has a film thickness of 4-100 μm and a bump density of a second density lower than the first density.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
• C30B 29/36 - Carbides

Abstract

[Problem] To provide a semiconductor device that makes it possible to improve a yield. [Solution] A semiconductor device according to an embodiment comprises: a first insulating plate; a first metal plate that is provided on a first surface of the first insulating plate; a second metal plate that is provided on a second surface on the opposite side from the first surface of the first insulating plate; a semiconductor chip that is provided on the second metal plate; and a resin member that encapsulates the semiconductor chip. In this semiconductor device, only one semiconductor chip is provided on the second metal plate.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates

Abstract

The purpose of the present invention is to provide a semiconductor device capable of suppressing a decrease in thermal conductivity, and to provide a method of manufacturing the same. According to one embodiment, the semiconductor device includes a semiconductor chip, a substrate, and an adhesive layer. The substrate supports the semiconductor chip. The adhesive layer is disposed between the semiconductor chip and the substrate. The adhesive layer bonds the semiconductor chip and the substrate. The adhesive layer has a first portion and a plurality of second portions. The first portion is formed of a first material. The plurality of second portions are formed of a second material. The second material has a higher elastic modulus and a higher thermal conductivity than the first material. The plurality of second portions are located inside the first portion. Each of the plurality of second portions is connected in contact with the semiconductor chip and the substrate.

IPC Classes  ?

• H01L 21/52 - Mounting semiconductor bodies in containers
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks

Abstract

A semiconductor device according to an embodiment is one having a first surface, which faces a first side, and a second surface, which faces a second side that is opposite from the first side. The semiconductor device according to an embodiment comprises: a semiconductor device main body; a lead frame to which the semiconductor device main body is electrically connected; electroconductive bumps electrically connected to the semiconductor device main body or the lead frame; and a resin part which covers and holds at least a part of the semiconductor device main body and at least a part of the lead frame. At least some of the electroconductive bumps are exposed to the outside of the resin part.

IPC Classes  ?

• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A method for manufacturing a semiconductor device according to one embodiment of the present invention involves processing a base material that has a first surface and a second surface opposite to the first surface. The method for manufacturing a semiconductor device according to the embodiment of the present invention comprises: forming a first trimming part by performing trimming on the base material from the first surface side; forming a second trimming part by performing trimming on the base material from the first surface side; forming an adhesive layer on the first surface by using a spin coating method that includes rotating the base material about a rotation axis line; fixing the base material to a support member via the adhesive layer; and grinding the base material from the second surface side to reduce the thickness-direction dimension of the base material. The second trimming part has a portion that is located on the inner side of the first trimming part in the radial direction centered about the rotation axis line.

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method for manufacturing a semiconductor device according to an embodiment includes a mark forming step, a first affixing step, a grinding step, and a processing step. The mark forming step is a step for forming a recess in a device surface on which there is formed a circuit pattern of a base material composed of a semiconductor material. The first affixing step is a step for affixing the device surface to a support substrate. The grinding step is a step for forming a ground surface by grinding the surface of the base material on the opposite side from the device surface in a state of being supported by the support substrate. The processing step is a step for processing the base material from the ground-surface side in a state of being supported by the support substrate. In the method for manufacturing a semiconductor device according to an embodiment, in the grinding step, the recess is exposed to the ground surface to form a mark, and in the processing step, the processing is performed with reference to the mark.

IPC Classes  ?

• H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

A semiconductor device according to one embodiment comprises a first transistor and a second transistor on a substrate, a first terminal, and a complex including a second terminal and a first insulator partially covering the second terminal. A first end of the first transistor and a second end of the second transistor are connected to each other. The first terminal includes a first portion that contacts a first conductor connected to a third end of the first transistor, a second portion connected to the first portion, and a third portion connected to the second portion. The second terminal includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion contacts a second conductor connected to a fourth end of the second transistor. The fifth portion is connected to the fourth portion and is aligned with the second portion of the first terminal. The sixth portion is connected to the fifth portion. The first insulator covers the fifth portion.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A semiconductor device according to an embodiment of the present invention comprises a semiconductor chip 10 and a first conductive layer 12B provided on a first surface side of the semiconductor chip 10. The first conductive layer 12B includes an intermetallic compound layer containing copper (Cu), tin (Sn), and silver (Ag), and the concentration of silver relative to tin in the first conductive layer 12B is 1.0 at% to 7.9 at%.

IPC Classes  ?

• H01L 21/52 - Mounting semiconductor bodies in containers
• B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
• C22C 13/00 - Alloys based on tin
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor device (1) according to an embodiment of the present invention comprises: a chip (11) that has a first surface (S1) and a second surface (S2); a first electrode pad (12) that is provided on the first surface of the chip; a first conductive layer (14) that is provided above the first electrode pad; a first joining material (13) that is provided between the first electrode pad and the first conductive layer and that contacts the first electrode pad and the first conductive layer; and a second electrode pad (15) that is provided on the second surface of the chip. A third surface (S3) of the first joining material which faces the first electrode pad has a contact part (CP1) that contacts the first electrode pad and a cutout (NP) that surrounds the contact part. An edge of the contact part is positioned inward of an end surface of the first conductive layer.

IPC Classes  ?

• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

A method of manufacturing a semiconductor device according to this embodiment includes a first film formation step of forming a first electrode layer on a base material rear surface facing a side opposite a device surface on the outer surfaces of the base material on which a circuit part is formed. The method includes a second film formation step of forming a second electrode layer on a surface of a film formation target member. The method includes a joining step of joining the first electrode layer and the second electrode layer. The method includes a film formation target member removal step for removing the film formation target member from the second electrode layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
• H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions

Abstract

According to an embodiment of the present invention, a semiconductor device comprises: a semiconductor chip in which a source electrode and a gate electrode are provided on a first surface, and a drain electrode is provided on a second surface on the opposite side from the first surface; a source terminal which has a fourth surface that is exposed from a third surface of the package and a fifth surface that is connected to the source electrode and that has a different shape from the fourth surface; a gate terminal which has a sixth surface that is exposed from the third surface of the package and a seventh surface that is connected to the gate electrode and that has a different shape from the sixth surface; and a drain terminal which is connected to the drain electrode and has an eighth surface that is exposed from the third surface of the package.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A silicon nitride sintered compact according to an embodiment contains 15-20 mass% of a grain boundary phase containing a lanthanoid element, and in a diffraction pattern when a prescribed cross-section is subjected to X-ray diffraction (XRD) measurements, the silicon nitride sintered compact has, in addition to an α-silicon nitride peak and a β-silicon nitride peak, four peaks resulted from a grain boundary crystal phase and an α-sialon phase in a diffraction angle range from 29° to 35°. In the silicon nitride sintered compact, the four peaks are positioned within a range of ±0.2° of each of the diffraction angles of 29.6°, 31.0°, 31.3°, and 34.4°, and when A1 to A4 are respectively the four peak areas for the four peaks, and A5 is the integrated intensity of the peak detected at the diffraction angle of 27.0°, it is preferable that 1.0 ≤ (A1+A2+A3+A4)/A5 ≤ 3.5.

IPC Classes  ?

• C04B 35/596 - Composites
• B23K 20/12 - Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating the heat being generated by frictionFriction welding

Abstract

Provided is a gas circuit breaker that allows for easy miniaturization and reduction of driving force. In the gas circuit breaker according to an embodiment, an insulation nozzle is a tubular body that includes a nozzle large diameter portion, a nozzle small diameter portion, and a nozzle inclination portion, and is disposed coaxially with an opposite-side arc contact in an axial direction. The nozzle small diameter portion is positioned closer to the opposite-side contact portion than the nozzle large diameter portion, and has a smaller outer diameter than that of the nozzle large diameter portion. The nozzle inclination portion is positioned closer to the opposite-side contact portion than the nozzle small diameter portion, and the outer peripheral surface thereof is inclined with respect to the axial direction so that the outer diameter increases from the nozzle small diameter portion toward the opposite-side contact portion side. Here, a deformation ring is provided so as to surround at least one of the nozzle small diameter portion and the nozzle inclination portion, such that an electric field that is generated around the tip of the opposite-side arc contact during a separation process is relaxed by the deformation ring.

IPC Classes  ?

• H01H 33/70 - Switches with separate means for directing, obtaining, or increasing flow of arc-extinguishing fluid
• H01H 33/915 - Switches with separate means for directing, obtaining, or increasing flow of arc-extinguishing fluid the flow of arc-extinguishing fluid being produced or increased by movement of pistons or other pressure-producing parts this movement being effected by, or in conjunction with, the contact-operating mechanism the arc-extinguishing fluid being air or gas with closed circuit of air or gas

Abstract

A method for manufacturing a semiconductor device according to an embodiment includes a first film formation step, a second film formation step, and an oxidation step. In the first film formation step, a first coating film that is formed of silicon is formed on the surface of a base material that is formed of silicon carbide. In the second film formation step, a second coating film is formed on the surface of the first coating film. In the oxidation step, the first coating film is thermally oxidized from the surface side so as to form a third coating film. In the second film formation step, the second coating film is not formed on a part of the first coating film so as to expose the part. Alternatively, in the second film formation step, the film thickness of the second coating film formed on a part of the first coating film is less than the film thickness of the second coating film formed on the other parts.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
• H01L 21/316 - Inorganic layers composed of oxides or glassy oxides or oxide-based glass
• H01L 21/318 - Inorganic layers composed of nitrides
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

This method for manufacturing a semiconductor device comprises: a step for forming, in a first region on an upper surface of a first silicon carbide layer of a first conductivity type, a second silicon carbide layer which has a first conductivity-type impurity density different from that of the first silicon carbide layer and has a first film thickness D2; a step for forming, in a second region on the upper surface, a third silicon carbide layer of a second conductivity type which has a film thickness D4; a step for forming, on the first silicon carbide layer, a fourth silicon carbide layer which has a first conductivity-type impurity density lower than that of the second silicon carbide layer and has a film thickness D1; a step for measuring, after forming the fourth silicon carbide layer, a second film thickness D3 of the second silicon carbide layer and the film thickness D1 of the fourth silicon carbide layer in a direction from the first silicon carbide layer toward the fourth silicon carbide layer; and a step for forming a trench which has a predetermined depth, and penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer, on the basis of the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

Provided are a remote-control device, a control device, a remote-control system, and a control method which make it possible to more stably perform control which is executed over a network.　A remote-control device according to the present embodiment is for processing a plurality of identical signals transmitted over a network having a number of transmission paths, and comprises: a communication unit; a control order determination unit; and a control program execution unit. The communication unit asynchronously receives the plurality of signals with which identifiers are associated. The control order determination unit determines, on the basis of the identifiers, whether the order of input values included in the signals corresponds to a predetermined order. When the control order determination unit determines the order corresponds to the predetermined order, the control program execution unit executes a control program of a control device using the input values.

IPC Classes  ?

• G05B 19/04 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers

Abstract

A connected solar-cell structure (10) according to an embodiment includes solar cell elements (1) and wiring lines (17, 18). Each solar cell element (1) has a monolithic structure and has extraction electrodes (7, 8) at both ends along a first direction (Y). The wiring lines (17, 18) are connected to the extraction electrodes (7, 8) and extend in a second direction (X) crossing the first direction (Y). A plurality of solar cell elements (1) are arranged side by side in the first direction (Y). Solar cell elements (1) adjacent to each other in the first direction (Y) are arranged so that the extraction electrodes (7, 8) having the same polarity are adjacent to each other along the first direction (Y). The wiring lines (17, 18) are connected to both the extraction electrodes (7, 8) having the same polarity which are adjacent to each other along the first direction (Y).

IPC Classes  ?

• H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
• H01L 31/0465 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module

Abstract

Provided are a control device, a control system, and a control method capable of more stably performing control via a virtual network.　According to the present embodiment, a control device periodically executes control using a plurality of virtual networks, and comprises a memory unit, a selecting unit, and a communication unit. The memory unit stores control data used for control. The selecting unit selects a virtual network to be used for control from among the plurality of virtual networks in accordance with an attribute of the control data. The communication unit transmits the control data using the virtual network selected by the selecting unit.

IPC Classes  ?

• H04L 45/64 - Routing or path finding of packets in data switching networks using an overlay routing layer
• H04L 41/0895 - Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
• H04L 41/5041 - Network service management, e.g. ensuring proper service fulfilment according to agreements characterised by the time relationship between creation and deployment of a service

Abstract

According to an embodiment, an embedded magnet-type rotor (30) is provided with: a rotor shaft; a rotor core (10) attached to the outer periphery of the rotor shaft; and permanent magnets (3) provided in the rotor core (10) and disposed so as to form a pair or a plurality of pairs with each other at each magnetic pole part. The rotor core (10) is provided with: an inner iron core (12) attached to the outer periphery of the rotor shaft; a fan-shaped outer iron core in each magnetic pole part; a filling member that fills the space between the inner iron core and the outer iron core; and a positioning member capable of maintaining the relative positions of the inner iron core and the respective outer iron cores. The inner iron core and the outer iron core are formed so as to be engaged with each other via the filling member.

IPC Classes  ?

• H02K 1/276 - Magnets embedded in the magnetic core, e.g. interior permanent magnets [IPM]

Abstract

According to an embodiment, a foamed adhesive flat wire (10) is provided with: a flat conductor (11) having a substantially rectangular cross section; an enamel layer (12) provided on the outer surface of the flat conductor (11); and a foamed adhesive layer (13) provided on the outer surface of the enamel layer (12) and capable of foaming and bonding at a predetermined temperature or higher. When the foamed adhesive layer (13) is not adjacent to another member at each side surface of the foamed adhesive flat wire (10), the thickness of the foamed adhesive layer side surface (13c, 13d) may be reduced or zero as compared with a case in which the foamed adhesive layer (13) is adjacent to another member.

IPC Classes  ?

• H02K 3/38 - Windings characterised by the shape, form or construction of the insulation around winding heads, equalising connectors, or connections thereto
• H02K 15/085 - Forming windings by laying conductors into or around core parts by laying conductors into slotted stators

Abstract

The purpose of the present invention is to specify a user using a PKCS#11-based HSM.　A key management device according to an embodiment comprises: a first acquisition unit that acquires pre-authentication information including a user ID, authentication information, and encrypted authentication information; a storage unit that securely stores a DB key; a first authentication unit that decrypts the encrypted authentication information using the DB key and performs authentication using the decrypted authentication information and the authentication information; a generation unit that generates a ticket associated with the user ID on the basis of an authentication result, and generates a pre-authentication response including the ticket; a first output unit that outputs the pre-authentication response; a second acquisition unit that acquires session information including the ticket; a second authentication unit that authenticates the session information on the basis of the ticket included in the session information and generates a cipher key corresponding to the ticket; and a second output unit that outputs an authentication result from the second authentication unit.

IPC Classes  ?

• H04L 9/10 - Arrangements for secret or secure communicationsNetwork security protocols with particular housing, physical features or manual controls
• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

Provided is an opening and closing device diagnosis system capable of easily and precisely identifying an abnormal site in addition to a sign of abnormality in an opening and closing device. In an opening and closing device diagnosis system according to an embodiment, an abnormality occurrence estimation unit obtains abnormality occurrence estimation data by estimating the presence or absence of abnormality occurrence in an opening and closing device on the basis of measurement data stored in a storage unit. On the basis of the measurement data stored in the storage unit, an abnormal site estimation unit obtains abnormal site estimation data by estimating an abnormal site where an abnormality is occurring in a plurality of opening and closing device components. An estimation result integration unit obtains integrated data by integrating the abnormality occurrence estimation data obtained by the abnormality occurrence estimation unit and the abnormal site estimation data obtained by the abnormal site estimation unit. An output unit outputs the integrated data obtained by the estimation result integration unit.

IPC Classes  ?

• H01H 33/00 - High-tension or heavy-current switches with arc-extinguishing or arc-preventing means

Abstract

Provided is a wafer support device capable of suppressing damage during recovery of a wafer guide. The present invention has a support base, a wafer guide portion, a first chamfered portion, and a second chamfered portion. The support base has a support surface for supporting a wafer. The wafer guide portion has an annular shape surrounding the periphery of the wafer supported on the support surface around a central axis extending in the normal direction of the support surface. The first chamfered portion connects an inner peripheral surface and an upper surface of the wafer guide portion, and extends upward from the inner peripheral surface toward an outer peripheral side. The second chamfered portion connects an outer peripheral surface and the upper surface of the wafer guide portion, and extends upward from the outer peripheral surface toward an inner peripheral side.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

Abstract

A susceptor according to an embodiment is provided to a vapor-phase growth device. A wafer is placed on the susceptor. The susceptor has a wafer-supporting part. The wafer-supporting part supports the wafer. The wafer-supporting part is annular. The wafer-supporting part has a supporting surface. The supporting surface supports the wafer from beneath. The supporting surface has an inclined surface. The inclined surface extends to the inner edge of the wafer-supporting part. The inclined surface rises toward the radial-direction outer periphery of the wafer-supporting part.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The present invention provides a semiconductor device capable of improving characteristics. According to an embodiment, this semiconductor device includes first to third electrodes, and first to fourth semiconductor members. The third electrode extends along a second direction intersecting a first direction heading from the first electrode toward the second electrode. The first semiconductor member is a first conductivity type. A fifth partial region of the first semiconductor member is in Schottky contact with the second electrode. The second semiconductor member is a second conductivity type. The third semiconductor member is the second conductivity type. A third semiconductor section of the third semiconductor member is electrically connected to the second electrode. The impurity concentration of the third semiconductor member is higher than the impurity concentration of the second semiconductor member. The fourth semiconductor member is the first conductivity type. A second semiconductor region of the fourth semiconductor member is electrically connected to the second electrode. The impurity concentration of the fourth semiconductor member is higher than the impurity concentration of the first semiconductor member.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/872 - Schottky diodes

Abstract

A semiconductor device according to one embodiment includes a semiconductor element, a first conductor, a first electrode, a second conductor, a second electrode, and a cover.　The semiconductor element extends over a first plane, and includes a first surface, a second surface opposing the first surface, and a third surface spanning between an end of the first surface and an end of the second surface. The semiconductor element includes a first electrode pad provided in a region including the first surface, and a second electrode pad provided in a region including the second surface.　The first conductor is in contact with the first electrode pad.　The first electrode is in contact with the first conductor.　The second conductor is in contact with the second electrode pad.　The second electrode is in contact with the second conductor.　The cover is a resin cover including a first portion, a second portion, and a third portion.　The first portion covers the third surface.　The second portion is connected to the first portion and faces the first surface.　The third portion is connected to the first portion, faces the second surface, and sandwiches the semiconductor element together with the second portion.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

Abstract

A semiconductor device according to an embodiment of the present invention includes: a pellet 60 that has a first surface provided with a plurality of pads 618; a first bonding material that is provided on the first surface; and a first metal plate 20 that is provided on the first bonding material, is electrically connected to the plurality of pads 618, and includes a second surface, which faces the first surface, and a plurality of protrusions 211 provided on the second surface. The plurality of protrusions 211 respectively face a pad 618A at one end and a pad 618B at another end in a direction in which a plurality of pads from among the plurality of pads 618 are arranged.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

Abstract

The present invention provides a semiconductor device capable of improving characteristics. According to an embodiment, this semiconductor device includes first to third electrodes, first to fourth semiconductor members, and a first insulating member. The first semiconductor member is provided between the first electrode and the second electrode, and is a first conductivity type. The first semiconductor member includes a fifth partial region. The second semiconductor member is a second conductivity type. The second semiconductor member includes a first semiconductor region and a second semiconductor region. The fifth partial region is between the first semiconductor region and the second semiconductor region in a third direction. The third semiconductor member is the second conductivity type. The fourth semiconductor member is the first conductivity type.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/872 - Schottky diodes

Abstract

The present invention improves reliability. A semiconductor device according to an embodiment which comprises a first member having a side wall surrounding an opening part for housing an electronic component and a receiving part provided so as to protrude from the side wall toward the opening part, and a second member which extends in a first direction, has an engagement part for mating with the receiving part, and covers at least part of the opening part, wherein: the engagement part has an extension part extending in the first direction, and a pair of engaging claws which project from the extension part at the bottom end thereof toward one end side and another end side in a second direction orthogonal to the first direction; each of the engaging claws has a first engagement surface that is angled relative to the first direction and is continuous with a side surface of the extension part that intersects the first direction; the receiving part has a pair of projecting parts that are provided so as to face each of the first engagement surfaces and include a projection surface which is angled relative to the first direction; and the lower side of the first engagement surfaces and the lower side of the projection surfaces are angled so as to become increasingly higher in a direction toward the side wall in a third direction which is orthogonal to both the first direction and the second direction.

IPC Classes  ?

• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H05K 7/12 - Resilient or clamping means for holding component to structure

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a substrate 10; a case 20 that is provided on the substrate 10 and that includes a resin layer 200 and a terminal 210; and a circuit board 100 that is provided on the substrate 10 and that includes a semiconductor chip 110 and wiring 109 electrically connected to the semiconductor chip 110 and the terminal 210. The terminal 210 includes a first portion 211 extending from the resin layer 200 toward the circuit board 100, a second portion 212 joined to the wiring 109, and a third portion 213 between the first portion 211 and the second portion 212. The third portion 213 is recessed to a side opposite to the substrate 100 side relative to the second portion 212.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A semiconductor device according to one embodiment of the present invention involves: a step for forming, by an epitaxial growth method and on a first silicon carbide layer, a second silicon carbide layer which has a lower first conductivity type impurity concentration than the first silicon carbide layer, in which the first conductivity type impurity concentration is 1×1014-1×1017atoms/cm3, and which has a film thickness of 0.001-0.1 µm; a step for forming, by an epitaxial growth method and on the second silicon carbide layer, a third silicon carbide layer which has a first conductivity type impurity concentration of not less than 5×1017atoms/cm3but less than 1×1020atoms/cm3, and which has a film thickness of 0.5-20 µm; a step for forming, by an epitaxial growth method and on the third silicon carbide layer, a fourth silicon carbide layer which has a lower first conductivity type impurity concentration than the third silicon carbide layer; and a step for heating the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A ceramic circuit board according to an embodiment of the present invention comprises a ceramic substrate and a metal circuit. The metal circuit is bonded to a first surface of the ceramic substrate via an active metal brazing material layer. The thickness of the metal circuit is 1 mm or more. The metal circuit has a through hole penetrating the metal circuit along a first direction perpendicular to the first surface. A section of the first surface overlaps the through hole in the first direction. The active metal brazing material layer is provided on the aforementioned section of the first surface.

IPC Classes  ?

• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal

Abstract

[Problem] To provide a semiconductor device capable of reducing the risk of thermal destruction. [Solution] This semiconductor device comprises: a first electrode; a second electrode facing the first electrode in a first direction; a semiconductor layer of a first conductivity type provided between the first electrode and the second electrode; a plurality of first semiconductor regions of a second conductivity type provided on a first electrode side in the semiconductor layer and extending in a second direction orthogonal to the first direction; a plurality of second semiconductor regions provided on a surface side of the plurality of first semiconductor regions and having an impurity concentration of the second conductivity type higher than that of the first semiconductor regions; and a plurality of PIN diode regions provided on the first electrode side in the semiconductor layer, extending in a third direction orthogonal to the first direction and the second direction, and electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions.

IPC Classes  ?

• H01L 29/861 - Diodes
• H01L 29/868 - PIN diodes
• H01L 29/872 - Schottky diodes