A laser circuit includes a temperature sensor, a temperature compensating circuit having an input coupled to the temperature sensor, a video digital-to-analog converter, and a laser with a first and a second terminal. The first terminal of the laser is coupled to the temperature compensating circuit and to the video digital-to-analog converter. Moreover, a method for operating a laser circuit is described.
In an embodiment a laser circuit includes a video digital-to-analog converter configured to provide a video signal current having a pulse form, a bias digital-to-analog converter configured to provide a bias current and a laser with a first and a second terminal, wherein the first terminal of the laser is coupled to the video digital-to-analog converter and to the bias digital-to-analog converter, wherein a value of the bias current is smaller than a laser threshold value of the laser, wherein a laser current includes the video signal current and the bias current, wherein, in case of a pulse of the video signal current, the laser current is higher than the laser threshold value, and wherein steps between consecutive setable current values of the laser current are smaller in the video digital-to-analog converter than in the bias digital-to-analog converter.
An image sensor includes a pixel array having a first pixel group and a second pixel group. Each pixel group includes a plurality of pixels, with each pixel having a photosensitive element, a sense node and a sample-and-hold stage. A driver circuit of the image sensor, during an exposure phase, is configured to operate the pixels of the first pixel group to perform a first exposure of a first duration, and to operate the pixels of the second pixel group to perform a second exposure of a second duration followed by a third exposure of a third duration. An output circuit of the image sensor, during a readout phase, is configured to read out a first photo signal from each pixel of the first pixel group, and to read out a second photo signal and a third photo signal from each pixel of the second pixel group.
H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
4.
IMAGING DEVICE, OPTOELECTRONIC DEVICE AND METHOD FOR OPERATING AN IMAGING DEVICE
An imaging device includes a plurality of pixels. The pixels include: a photosensitive stage, including a photodetector and a diffusion node electrically coupled to the photodetector via a transfer switch; a sample-and-hold stage including a first source follower, wherein a gate terminal of the first source follower is electrically connected to the diffusion node, and further including a pair of switchable capacitors that are electrically coupled to an output terminal of the first source follower; a readout stage, wherein an input of the readout stage is electrically coupled to an output of the sample-and-hold stage; and an electrical interconnection including an gain switch, that is electrically connected to the diffusion node and to a first terminal of one of the capacitors.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
5.
IMAGE SENSOR, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING AN IMAGE SENSOR
An image sensor (10) comprises a semiconductor substrate (100) comprising a photodiode (105) comprising a first doped portion (111) of a first conductivity type and a second doped portion (112) of a second conductivity type. The image sensor (10) further comprises a transfer gate (107) for transferring charges from the second doped portion (112) to a floating diffusion portion (108). The transfer gate (107) and the floating diffusion portion (108) are arranged at a first main surface (101) of the semiconductor substrate (100) opposite to a second main surface (102) being an incidence surface for electromagnetic radiation (15). The transfer gate (107) comprises a gate trench (114) extending from the first main surface (101) in a depth direction. The image sensor (10) further comprises a reflecting metasurface (117) at the first main surface (101) of the semiconductor substrate (100).
A laser circuit includes a video digital-to-analog converter, a laser with a first and a second terminal, a first supply terminal which is coupled via the video digital-to-analog converter to the first terminal of the laser, and a second supply terminal which is coupled to the second terminal of the laser. A first supply voltage provided at the first supply terminal is higher than a ground potential. A second supply voltage provided at the second supply terminal is lower than the ground potential. Moreover, a method for operating a laser circuit is described.
A system (10) for actively aligning a lens module (100) and an image sensor (105) comprises a movable, rotatable stage (101) for supporting the lens module (100), a stage (107) for supporting the image sensor (105), an illumination source (115), and a camera (120). The illumination source (115) is configured to illuminate a main surface (106) of the image sensor (105) via the lens module (100). The camera (120) is configured to take a picture of the illuminated main surface (106) of the image sensor (105) via the lens module (100). The sys- tem further comprises a control device (125) configured to determine a movement of the movable stage ((101) based on the picture taken by the camera (120).
An image sensor (10) comprises a carrier (100) having a curved surface portion (101), an opening (105) extending from the curved surface portion (101) to a second main surface (102) of the carrier (100). The image sensor (10) further comprises a curved sensor chip (110) arranged in the curved surface portion (101), a second main surface (112) of the curved sensor chip (110) being adjacent to the curved surface portion (101), and an electrical contact element (107) arranged in the opening (105) and extending from the curved surface portion (101) to the second main surface (102) of the carrier (100).
A chip-scale package (10) includes a semiconductor sensor device (15), the semiconductor sensor device (15) comprising a substrate (110) and a sensing region (113) arranged over a central portion (117) of a first main surface (111) of the substrate (110), wherein the sensing region (113) is absent from an edge portion (115) of the substrate (110). The chip-scale package (10) further comprising a transparent carrier (too) and an adhesive (105). The sensing region (113) is arranged between the substrate (110) and the adhesive (105). The chip-scale package (10) further comprises a portion of a masking layer (120) between the transparent carrier (too) and the adhesive (105), the portion of the masking layer (120) being arranged in the edge portion (115) of the substrate (110).
An image sensor system comprises a pixel array with a plurality of pixels, a buffer memory and a matrix memory configured to store a unity matrix and at least one edge detection matrix. A control block effects readout and digitizing of at least four signal values during at least four integration periods, storing the signal values of a selected subsection of the pixel array into the respective pluralities of memory cells of the buffer memory, selects a coefficient matrix from the matrix memory, and effects generation of respective processed signal values corresponding to the pixels of the selected subsection by applying the selected coefficient matrix onto the stored digitized signal values. A computation block determines at least one derivative pixel value based on a difference between at least two values selected from the respective processed signal values and on a duration of at least one of the integration periods.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
The present disclosure relates to a photomask (20) for use in a photolithography stepper. The photomask (20) comprises a step field (111). The step field (111) comprises a first alignment mark (107) in a first edge portion (101) of the step field (111). The first alignment mark (107) defines a comb pattern comprising a first line (121) and a plurality of parallel second lines (122) between the first line (121) and a first boundary (110) of the step field (111) in a first direction, a distance between the first line (121) and the first boundary (110) being smaller in the first direction than in a second direction opposite to the first direction. The first line (121) runs parallel to the first boundary (110), and the second lines (122) run perpendicular to the first boundary (110). The second lines (122) are connected to the first line (121).
In an embodiment a pixel arrangement includes a photodiode, a circuit node, a transfer transistor coupled to the photodiode and to the circuit node, an amplifier with an input coupled to the circuit node, a first capacitor and a second capacitor, a first transistor coupled to an output of the amplifier and to the first capacitor, a second transistor coupled to the first transistor and to the second capacitor, a supply terminal, a reset transistor coupled to the supply terminal, a coupling transistor coupled to the circuit node and to the reset transistor and a third capacitor with a first electrode coupled to a node between the reset transistor and the coupling transistor.
A CMOS sensor (10) comprises a plurality of pixels (100), each of the pixels (100) comprising a photodiode (111, 112) and a switch (114, 115), the photodiodes (111, 112) being arranged in rows and columns, respectively. The CMOS sensor (10) further comprises a processing circuit (105) for activating the switches (114, 115). The processing circuit (105) is configured to simultaneously bias a first photodiode (111) and a second photodiode (112) to accomplish readout, to obtain a first readout result. The processing circuit (105) is further configured to bias the first photodiode (111) to accomplish readout while the second photodiode (112) is not biased to accomplish readout, to obtain a second readout result. The processing circuit is further configured to bias the second photodiode (112) to accomplish readout while the first photodiode (111) is not biased to accomplish readout, to obtain a third readout result. The processing circuit (105) further is configured to determine a spatial distribution of incoming photons on the basis of a difference between the first readout result and the second readout result and a difference between the first readout result and the third readout result.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
In an embodiment a method for operating a pixel arrangement includes, during an exposure period, accumulating, by a photodetector, in a first integration period, charge carriers, pulsing, at an end of the first integration period, a transfer transistor to a first voltage level for transferring a portion of the accumulated charge carriers to a diffusion node, wherein the portion is configured to be drained to a supply voltage, continuing, by the photodetector, to accumulate, in a second integration period, charge carriers, after the second integration period, pulsing the transfer transistor to a respective further voltage level with at least one additional pulse, wherein, with each additional pulse, an additional portion of the accumulated charge carriers is configured to be drained to the supply voltage, and wherein each additional pulse is followed by an additional continued accumulation of charge carriers in a respective additional integration period with the photodetector.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/703 - SSIS architectures incorporating pixels for producing signals other than image signals
15.
ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION METHOD
An ADC circuit includes a comparator with a first input for receiving an analog signal and with a second input for receiving a ramp signal, a first output of the comparator, a second output of the comparator, a first counter connected to the first output, a second counter connected to the second output, a first clock connected to the first counter, and a second clock connected to the second counter. The first clock provides a first clock signal to the first counter, the second clock provides a second clock signal to the second counter, the first counter is configured to count with the frequency of the first clock signal, the second counter is configured to count with the frequency of the second clock signal. The frequency of the first clock signal is lower than the frequency of the second clock signal.
An imaging pixel to mitigate cross-talk effects comprises a voltage supply node to receive a supply voltage, and an output node to provide a pixel output signal. The imaging pixel further comprises a photosensitive element, and a source follower transistor having a control node coupled to the photosensitive element. The source follower transistor is interposed between the voltage supply node and the output node. The imaging pixel comprises a clamping circuit being interposed between the voltage supply node and the output node.
H04N 25/625 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
17.
ANALOG-TO-DIGITAL CONVERTER WITH SHARED COMPARATOR READOUT
The present technology relates an analog-to-digital converter, ADC (100), comprising : a comparator (110) comprising a first comparator branch (110A) and second comparator branch (HOB), the first comparator branch (110A) comprising a plurality of stages (112A), each of the stages (112A) being configured to be sequentially connected to the second comparator branch (HOB), each stage (112A) comprising: a first input transistor (114A), and a capacitor (116A), a first terminal of the capacitor (116A) being configured to be directly connected to a pixel array (12), a second terminal of the capacitor (116A) being configured to be connected to a gate electrode of the first input transistor (H4A), wherein the second comparator branch (HOB) comprises a second input transistor (114B), a reference voltage (Vref) being connectable to the gate electrode of the second input transistor (114B), and a source region of the second input transistor (114B) is configured to be sequentially connected to a source region of the first input transistor (114A) of each of the stages (112A) so as to connect the second comparator branch (HOB) to a respective stage (112A).
Disclosed herein is a ramp circuit for an analogue to digital converter, ADC. The ramp circuit includes a ramp unit configured to provide a ramp signal usable for sampling an analogue signal. The ramp circuit also includes a hold unit connected to the ramp unit, the hold unit is configured to hold a reference voltage for resetting the ramp signal between subsequent samplings of the analogue signal.
A pixel arrangement (10) comprises a photodiode (20), a circuit node (35), a transfer transistor (30), an amplifier (60), a supply terminal (17) and a reset transistor (50). The transfer transistor (30) is coupled to the photodiode (20) and to the circuit node (35). The amplifier (60) is coupled to the circuit node (35). The reset transistor (50) is coupled to the supply terminal (17) and to the circuit node (35). In a reset phase (RE), charge (Q) of the photodiode (20) flows via the transfer transistor (30) being set in a first conducting state and via the reset transistor (50) to the supply terminal (17) and further charge (Q) of the photodiode (30) flows via the transfer transistor (30) being set in a second conducting state and via the reset transistor (50) to the supply terminal (17). A method for operating a pixel arrangement is provided.
H04N 25/583 - Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
20.
OPTICAL SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME
An optical sensor includes an array of pixels, wherein each pixel includes a photodiode configured to receive an optical signal and a floating node coupled to the photodiode. At least one sensing path is capacitively coupled to the floating node of at least one of the pixels. An evaluation unit is coupled to the at least one sensing path to generate an electrical signal dependent on the optical signal received by the photodiode.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
, …, 110<2i-1>), each ADC circuit (110<0>, …, 110, …, 110, …, 110<2i-1>) being associated to a pixel group of an pixel array and comprising a storage circuit (120<0>, …, 120, …, 120, …, 120<2i-1>) comprising a plurality of storage cells (122, 124), a shared counter circuit (130) having a counter control connection (C131, C133) to apply a clock signal (S2) and a plurality of counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F), the shared counter circuit (130) being configured to generate a respective counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF) in response to a counter state of the counter circuit (130), wherein a respective one of the storage cells (122, 124) is connected to a respective one of the counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F) for storing the respective counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF), wherein the shared counter circuit (130) comprises a Gray ripple counter (132, 134), and a delay circuit (140), the delay circuit being arranged on at least one of the counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F) between the counter circuit (130) and a corresponding storage cell (122, 124) and being configured to add to at least one counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF) a bit-specific delay (b_D) to account for a ripple delay introduced by the Gray ripple counter (132, 134)., …, 110<2i-1>), each ADC circuit (110<0>, …, 110, …, 110, …, 110<2i-1>) being associated to a pixel group of an pixel array and comprising a storage circuit (120<0>, …, 120, …, 120, …, 120<2i-1>) comprising a plurality of storage cells (122, 124), a shared counter circuit (130) having a counter control connection (C131, C133) to apply a clock signal (S2) and a plurality of counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F), the shared counter circuit (130) being configured to generate a respective counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF) in response to a counter state of the counter circuit (130), wherein a respective one of the storage cells (122, 124) is connected to a respective one of the counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F) for storing the respective counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF), wherein the shared counter circuit (130) comprises a Gray ripple counter (132, 134), and a delay circuit (140), the delay circuit being arranged on at least one of the counter output connections (CO_130R<0>, …, CO_130R, CO_130F<0>, …, CO_130F) between the counter circuit (130) and a corresponding storage cell (122, 124) and being configured to add to at least one counter bit (CNTR<0>, …, CNTR, CNTF<0>, …, CNTF) a bit-specific delay (b_D) to account for a ripple delay introduced by the Gray ripple counter (132, 134).
A low-dropout regulator with inrush current limiting capabilities may include an output terminal to provide an output signal, a first current branch comprising a pass device connected to the output terminal, and a second current branch comprising a driver transistor and a current generator. The low-dropout regulator may further include an error amplifier to control the driver transistor. The error amplifier may have a first input node to apply a reference signal, and a second input node coupled to the output terminal. The low-dropout regulator may include a current mirror to couple the second current branch to the first current branch. The current mirror is configured to mirror a current in the second current branch to the output current branch.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
23.
Sensor arrangement and method of producing a sensor arrangement
A sensor arrangement includes a first, second, third and fourth group of receiving elements for detecting light in the red, green, blue and infrared wavelength range. At least one first sub-arrangement is formed by arranging one receiving element of the first group, two receiving elements of the second group and one receiving element of the third group in a first Bayer-like pattern. At least one second sub-arrangement is formed by arranging two receiving elements of the second group, one receiving element of the fourth group and one receiving element of the first or the third group in a second Bayer-like pattern. The at least one first sub-arrangement and the at least one second sub-arrangement are arranged adjacent to each other in a main plane of extension of the sensor arrangement.
H04N 25/131 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
H04N 23/11 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
24.
PIXEL STRUCTURE AND METHOD FOR MANUFACTURING A PIXEL STRUCTURE
A pixel structure includes a substrate body having a light entrance surface, a plurality of first photodiodes formed in the substrate body at a first depth with respect to the light entrance surface, and a second photodiode formed in the substrate body at a second depth with respect to the light entrance surface. The first depth corresponds to a photon absorption length in a material of the substrate body at a first wavelength range, and the second depth corresponds to a photon absorption length in the material of the substrate body at a second wavelength range that is different from the first wavelength range.
A laser circuit (10) comprises a video digital-to-analog converter (23), a bias digital-to-analog converter (70) and a laser (20) with a first and a second terminal (21, 22). The first terminal (21) of the laser (20) is coupled to the video digital-to-analog converter (23) and to the bias digital-to-analog converter (70). The video digital-to-analog converter (23) is configured to provide a video signal current (IVS) having a pulse form. The bias digital-to-analog converter (70) is configured to provide a bias current (IB). A value of the bias current (IB) is smaller than a laser threshold value (ITH) of the laser (20). A laser current (I1) comprises the video signal current (IVS) and the bias current (IB). In case of a pulse of the video signal current (IVS), the laser current (I1) is higher than the laser threshold value (ITH). Moreover, a method for operating a laser circuit (10) is described.
A laser circuit (10) comprises a video digital-to-analog converter (23), a laser (20) with a first and a second terminal (21, 22), a first supply terminal (11) which is coupled via the video digital-to-analog converter (23) to the first terminal (21) of the laser (20), and a second supply terminal (12) which is coupled to the second terminal (22) of the laser (20). A first supply voltage (VCC) provided at the first supply terminal (11) is higher than a ground potential (GND). A second supply voltage (VCA_R) provided at the second supply terminal (12) is lower than the ground potential (GND). Moreover, a method for operating a laser circuit (10) is described.
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
27.
LASER CIRCUIT WITH SWITCHED-CAPACITOR CIRCUIT AND METHOD FOR OPERATING A LASER CIRCUIT
A laser circuit (10) comprises a switched-capacitor circuit (110), a video digital-to-analog converter (23) and a laser (20) with a first and a second terminal (21, 22). The first terminal (21) of the laser (20) is coupled to the switched- capacitor circuit (110) and to the video digital-to-analog converter (23). Moreover, a method for operating a laser circuit (10) is described.
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
28.
LASER CIRCUIT WITH TEMPERATURE SENSOR AND METHOD FOR OPERATING A LASER CIRCUIT
A laser circuit (10) comprises a temperature sensor (85), a temperature compensating circuit (86) having an input coupled to the temperature sensor (85), a video digital-to-analog converter (23) and a laser (20) with a first and a second terminal (21, 22). The first terminal (21) of the laser (20) is coupled to the temperature compensating circuit (86) and to the video digital-to-analog converter (23). Moreover, a method for operating a laser circuit (10) is described.
The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.
H04N 23/80 - Camera processing pipelinesComponents thereof
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
30.
IMAGING DEVICE, OPTOELECTRONIC DEVICE AND METHOD FOR OPERATING AN IMAGING DEVICE
An imaging device (200) comprising a plurality of pixels (10) is provided. The pixels (10) comprise: a photosensitive stage (20), comprising a photodetector (22) and a diffusion node (24) electrically coupled to the photodetector (22) via a transfer switch (26); a sample-and-hold stage (30) comprising a first source follower (32), wherein a gate terminal of the first source follower (32) is electrically connected to the diffusion node (24), and further comprising a pair of switchable capacitors (34, 36) that are electrically coupled to an output terminal of the first source follower (32); a readout stage (40), wherein an input of the readout stage (40) is electrically coupled to an output of the sample-and-hold stage (30); and an electrical interconnection (50) comprising an gain switch (52), that is electrically connected to the diffusion node (24) and to a first terminal of one of the capacitors (34, 36). Further, an optoelectronic device (300) and a method for operating an imaging device (200) is provided.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
31.
IMAGE SENSOR, OPTOELECTRONIC DEVICE INCLUDING THE IMAGE SENSOR AND METHOD FOR OPERATING THE IMAGE SENSOR
An image sensor (IS) comprising a pixel array (ARR) having a first pixel group (G1) and a second pixel group (G2) is provided. Each pixel group (G1, G2) comprises a plurality of pixels (PXL), with each pixel (PXL) having a photosensitive element (PD), a sense node (FD) and a sample-and-hold stage (SHS). A driver circuit (DRV) of the image sensor (IS), during an exposure phase, is configured to operate the pixels (PXL) of the first pixel group (G1) to perform a first exposure of a first duration (T1), and to operate the pixels (PXL) of the second pixel group (G2) to perform a second exposure of a second duration (T2) followed by a third exposure of a third duration (T3). An output circuit (OUT) of the image sensor (IS), during a readout phase, is configured to read out a first photo signal from each pixel (PXL) of the first pixel group (G1), and to read out a second photo signal and a third photo signal from each pixel (PXL) of the second pixel group (G2).
H04N 25/533 - Control of the integration time by using differing integration times for different sensor regions
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/583 - Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
32.
Pixel, electric device and method having a transfer gate and sample stages configured to be operated in conjunction with a light source in response to a control signal
A pixel includes a transfer gate, and a sample structure having a first sample stage and a second sample stage. The transfer gate and the first and the second sample stages are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage is configured to sample a first sample value that depends on radiation incident on the photosensitive element from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage is configured to sample a second sample value that depends on radiation incident on the photosensitive element from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.
H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
H04N 25/532 - Control of the integration time by controlling global shutters in CMOS SSIS
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
A voltage ramp generator with low-noise offset injection comprises an output node (0) to output an output voltage (VRAMP) of the voltage ramp generator, a current source (110) coupled to the output node (0), and an array of capacitors (120). Each of the capacitors (120a,..., 120n) has a respective first node (121) being coupled to the output node (0), and a respective second node (122). The voltage ramp generator is configured to selectively couple the respective second node (122) of at least a portion of the capacitors (120a, 120m) of the array of capacitors (120) to one of a first voltage reference (VOFF, VOFF1) and a second voltage reference (GND, VOFF2).
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H03M 1/56 - Input signal compared with linear ramp
34.
ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION METHOD
An analog-to-digital converter circuit (20) is provided, the analog-to-digital converter circuit (20) comprising a comparator (21) with a first input (22) for receiving an analog signal (AS) and with a second input (23) for receiving a ramp signal (RS), a first output (24) of the comparator (21), a second output (25) of the comparator (21), a first counter (26) connected to the first output (24), a second counter (27) connected to the second output (25), a first clock (28) connected to the first counter (26), and a second clock (29) connected to the second counter (27), wherein the first clock (28) is configured to provide a first clock signal (FC) to the first counter (26), the second clock (29) is configured to provide a second clock signal (SC) to the second counter (27), the first counter (26) is configured to count with the frequency of the first clock signal (FC), the second counter (27) is configured to count with the frequency of the second clock signal (SC), and the frequency of the first clock signal (FC) is lower than the frequency of the second clock signal (SC). Furthermore, an analog-to-digital conversion method is provided.
A pixel cell comprises a plurality of pixels, each pixel comprising a photodiode, a readout circuit comprising a first readout component and a second readout component, wherein a first group of the pixels is configured to detect electromagnetic radiation in a first wavelength range, a second group of the pixels is configured to detect electromagnetic radiation in a second wavelength range, the first readout component is connected with the first group of pixels, the second readout component is connected with the second group of pixels, the first wavelength range is different from the second wavelength range, and the second readout component comprises a plurality of storage capacitors, wherein each pixel of the second group of pixels is assigned to at least one of the storage capacitors, or the second readout component comprises a memory element. Furthermore, a method for operating a pixel cell is provided.
H04N 23/11 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
36.
PIXEL ARRANGEMENT, IMAGE SENSOR AND METHOD OF OPERATING A PIXEL ARRANGEMENT
A pixel arrangement (10) is provided that is configured for high and low sensitivity mode, respectively. A photodiode (20) is configured to convert electromagnetic radiation into a respective charge signal, and a transfer gate (30) is configured to transfer the respective charge signal to a capacitance (40). A reset gate (50) is configured for resetting the capacitance. An amplifier (60) is configured to generate a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. A first capacitor (70) coupled to a first switch (90) is configured to store the high sensitivity signal and a second capacitor (80) coupled to a second switch (100) is configured to store the low sensitivity signal. Further, an image sensor (200), an optoelectronic device (300) and a method for operating a pixel arrangement is provided.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
37.
PIXEL ARRANGEMENT AND METHOD FOR OPERATING A PIXEL ARRANGEMENT
A pixel arrangement (10) comprises a photodiode (20), a circuit node (35), a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35), an amplifier (60) coupled to the circuit node (35), a first transistor (90) coupled to the amplifier (60) and a first capacitor (70), a second transistor (100) coupled to the first transistor (90) and a second capacitor (80), a reset transistor (50) coupled to a supply terminal (17), a coupling transistor (105) coupled to the circuit node (35) and the reset transistor (50), and a third capacitor (85) coupled to a node between the reset transistor (50) and the coupling transistor (105). Furthermore, a method for operating a pixel arrangement is described.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
38.
SELF CALIBRATING BARRIER MODULATION PIXEL WITH MULTIPLE BARRIERS, DUAL CONVERSION GAIN, AND LOW AREA
A pixel arrangement is provided, the pixel arrangement comprising a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage, a sample-and-hold stage comprising at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers. Further, a method of operating a pixel arrangement and an image sensor comprising the pixel arrangement are provided.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
39.
Pixel arrangement, image sensor and method of operating a pixel arrangement
In an embodiment a pixel arrangement includes at least one photodiode configured to convert electromagnetic radiation into a respective charge signal, a transfer gate between the photodiode and a capacitance for transferring the respective charge signal to the capacitance, a reset gate electrically coupled to the capacitance, the reset gate configured to reset the capacitance, an amplifier electrically connected to the capacitance and configured to generate, based on the respective charge signal and on a sensitivity mode, a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level, a first capacitor configured to store the high sensitivity signal, a second capacitor configured to store the low sensitivity signal, a first switch between an output terminal of the amplifier and the first capacitor and a second switch between the output terminal of the amplifier and the second capacitor.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/585 - Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/583 - Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
In an embodiment a pixel arrangement includes a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage and a sample-and-hold stage including at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, wherein at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/583 - Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
H04N 25/585 - Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
A pixel arrangement is provided, the pixel arrangement comprising a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage, a sample-and-hold stage comprising at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers. Further, a method of operating a pixel arrangement and an image sensor comprising the pixel arrangement are provided.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
42.
PIXEL ARRANGEMENT, IMAGE SENSOR AND METHOD OF OPERATING A PIXEL ARRANGEMENT
A pixel arrangement (10) is provided that is configured for high and low sensitivity mode, respectively. A photodiode (20) is configured to convert electromagnetic radiation into a respective charge signal, and a transfer gate (30) is configured to transfer the respective charge signal to a capacitance (40). A reset gate (50) is configured for resetting the capacitance. An amplifier (60) is configured to generate a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. A first capacitor (70) coupled to a first switch (90) is configured to store the high sensitivity signal and a second capacitor (80) coupled to a second switch (100) is configured to store the low sensitivity signal. Further, an image sensor (200), an optoelectronic device (300) and a method for operating a pixel arrangement is provided.
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
An imaging pixel (2) to mitigate cross-talk effects comprises a voltage supply node (VN) to receive a supply voltage (VDD), and an output node (ON) to provide a pixel output signal. The imaging pixel (2) further comprises a photosensitive element (10), and a source follower transistor (31) having a control node coupled to the photosensitive element (10). The source follower transistor (31) is interposed between the voltage supply node (VN) and the output node (ON). The imaging pixel (2) comprises a clamping circuit (20) being interposed between the voltage supply node (VN) and the output node (ON).
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/359 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
A ramp circuit for an analogue to digital converter, ADC. The ramp circuit comprises a ramp unit (6) configured to provide a ramp signal usable for sampling an analogue signal, and a hold unit (18) connected to the ramp unit (6) and configured to hold a reference voltage for resetting the ramp signal between subsequent samplings of the analogue signal.
H03M 1/56 - Input signal compared with linear ramp
H03K 4/50 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
45.
SENSOR ARRANGEMENT, IMAGE SENSOR, IMAGING DEVICE AND METHOD OF PROVIDING A SENSOR ARRANGEMENT
In one embodiment a Sensor arrangement comprises a first receiving element (11) configured to detect light in a first wavelength range, a second receiving element (12) configured to detect light in the first wavelength range or in a second wavelength range, a third receiving element (13) configured to detect light in one of the first wavelength range, the second wavelength range or a third wavelength range, a fourth receiving element (14) configured to detect light in a fourth wavelength range, the fourth wavelength range comprising at least part of the infrared wavelength range, and an enhancement layer (16). Therein the first, the second and the third wavelength ranges are different from each other. The enhancement layer (16) is configured to cover a top surface (15) of only the fourth receiving element (14), such that the enhancement layer is arranged between said top surface of the fourth receiving element and a source of incident electromagnetic radiation to increase a quantum efficiency of the fourth receiving element.
An image sensor arrangement (1) comprises a first sensor layer (2) comprising a first group of pixels (3), each pixel (3) of the first group comprising a photodiode (14, 15, 16, 17) configured to detect electromagnetic radiation in a first wavelength range. It further comprises a second sensor layer (4) comprising a second group of pixels (5), each pixel (5) of the second group comprising a photodiode (13) configured to detect electromagnetic radiation in a second wavelength range. It further comprises a readout layer (6) comprising a readout circuit (7) being configured to read out electrical signals from the pixels (3, 5) of the first and the second group. The second sensor layer (4) is arranged between the first sensor layer (2) and the readout layer (6). The second wavelength range is outside a wavelength range detectable by the first sensor layer (2).
An optical sensor (100) comprises an array of pixels, wherein each pixel comprises a photodiode (111) configured to receive an optical signal and a floating node (113) coupled to the photodiode (111). At least one sensing path (114) is capacitively coupled to the floating node (113) of at least one of the pixels (110). An evaluation unit (115) is coupled to the at least one sensing path (114) to generate an electrical signal (CTRL) dependent on the optical signal received by the photodiode (111).
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
48.
LOW-DROPOUT REGULATOR WITH INRUSH CURRENT LIMITING CAPABILITIES
A low-dropout regulator (1, 1') with inrush current limiting capabilities comprises an output terminal (O) to provide an output signal (Out), a first current branch (10) comprising a pass device (30) being connected to the output terminal (O), and a second current branch (20) comprising a driver transistor (40) and a current generator (70). The low-dropout regulator (1, 1') further comprises an error amplifier (50) to control the driver transistor (40). The error amplifier (50) has a first input node (I50a) to apply a reference signal (Vref), and a second input node (I50b) coupled to the output terminal (O). The low-dropout regulator (1, 1') comprises a current mirror (60) to couple the second current branch (20) to the first current branch (10). The current mirror (60) is configured to mirror a current in the second current branch (20) to the output current branch (10).
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
49.
Readout circuit, readout stage, image sensor, electronic device and method for reading out an image sensor
A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a plurality of pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.
A sensor arrangement (1) comprises at least three types of receiving elements (4), wherein the receiving elements (4) of a particular type are configured to detect light in a respective wavelength range. The receiving elements (4) are arranged in a matrix (2), wherein columns (3, 3') of the matrix comprise receiving elements (4) of the at least three types which are arranged in predefined sequences (6, 6') such that the sequence (6') of at least one column (3') of the matrix (2) is formed by the sequence (6) of a respective preceding column (3), which is cyclically shifted by at least one receiving element (4) in a predefined direction.
An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
52.
Image sensor system, electronic device and method for operating an image sensor
An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
53.
PIXEL STRUCTURE AND METHOD FOR MANUFACTURING A PIXEL STRUCTURE
A pixel structure (1) comprises a substrate body (10) having a light entrance surface (2), a plurality of first photodiodes (11) formed in the substrate body (10) at a first depth (d1) with respect to the light entrance surface (2), and a second photodiode (12) formed in the substrate body (10) at a second depth (d2) with respect to the light entrance surface (2). The first depth (d1) corresponds to a photon absorption length in a material of the substrate body (10) at a first wavelength range, and the second depth (d2) corresponds to a photon absorption length in the material of the substrate body (10) at a second wavelength range that is different from the first wavelength range.
A sensor arrangement (1) comprises a first, second, third and fourth group of receiving elements (2, 3, 4, 5) for detecting light in the red, green, blue and infrared wavelength range. At least one first sub-arrangement (6) is formed by arranging one receiving element (2) of the first group, two receiving elements (3) of the second group and one receiving element (4) of the third group in a first Bayer-like pattern. At least one second sub-arrangement (7, 7') is formed by arranging two receiving elements of the second group (3), one receiving element of the fourth group (5) and one receiving element (2, 4) of the first or the third group in a second Bayer-like pattern. The at least one first sub-arrangement (6) and the at least one second sub-arrangement (7, 7') are arranged adjacent to each other in a main plane of extension of the sensor arrangement (1).
A pixel with enhanced quantum efficiency comprises a semiconductor body that has a first surface configured as an entrance surface and a light capturing region configured for capturing light that is incident on the first surface. The pixel further comprises a structured interface, isolation layers on at least two surfaces of the semiconductor body that are perpendicular to the first surface, and a filter element that is arranged at a distance from the first surface such that light that is incident on the first surface at an angle of incidence smaller than a critical angle impinges on the filter element.
An image sensor comprises an array comprising rows and columns of pixels, a first number N of connection lines connected to a first number N of pixels of the array, a voltage regulating circuit having an output, a first terminal, and a driver circuit. The driver circuit has a first number N of switches coupled to the first number N of connection lines and to the output of the voltage regulating circuit, and a first number N of further switches coupled to the first number N of connection lines and to the first terminal. The first number N is at least two.
The present disclosure relates to a processing arrangement (3) for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement (3) for determining a digital output value (OUT) from a digital input value (IN) based on a linear function (1) and a square root function (2). The processing arrangement (3) comprises a first calculation block (6) configured to determine a first output value (y1) of the linear function (1), a second calculation block (7) configured to determine a second output value (y2) of the square root function (2). A selector (14) is configured to select, based on a comparison between the digital input value (IN) and a threshold value (XLIN), whether the digital output value (OUT) is determined by the first calculation block (6) or by the second calculation block (7).
A pixel (1) comprises a transfer gate (11), and a sample structure (20) having a first sample stage (21) and a second sample stage (22). The transfer gate (11) and the first and the second sample stages (21, 22) are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage (21) is configured to sample a first sample value that depends on radiation incident on the photosensitive element (10) from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage (22) is configured to sample a second sample value that depends on radiation incident on the photosensitive element (10) from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A pixel cell includes a pixel set with a plurality of pixels, with each pixel of the pixel set being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell further includes a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set and to operate the pixel set in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel is used to generate individual rolling shutter output signals.
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
60.
PIXEL CELL, IMAGE SENSOR AND METHOD FOR OPERATING A PIXEL CELL
A pixel cell (10) comprises a plurality of pixels (11), each pixel (11) comprising a photodiode (12), a readout circuit (13) comprising a first readout component (14) and a second readout component (15), wherein a first group of the pixels (11) is configured to detect electromagnetic radiation in a first wavelength range, a second group of the pixels (11) is configured to detect electromagnetic radiation in a second wavelength range, the first readout component (14) is connected with the first group of pixels (11), the second readout component (15) is connected with the second group of pixels (11), the first wavelength range is different from the second wavelength range, and the second readout component (15) comprises a plurality of storage capacitors (16), wherein each pixel (11) of the second group of pixels (11) is assigned to at least one of the storage capacitors (16), or the second readout component (15) comprises a memory element (17). Furthermore, a method for operating a pixel cell (10) is provided.
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
An analog-to-digital converter for an image sensor comprises a counter circuit (110) to generate a respective counter bit (CNT<0>, CNT<1>,..., CNT) in response to a counter state of the counter circuit (110), and a storage circuit (130) for storing a respective storage state in response the respective counter bit (CNT<0>, CNT<1>,..., CNT). The converter further comprises a comparator circuit (150) for generating a level of a comparison signal (COMP), and a synchronization circuit (160) to generate a write control signal (WRITE) for controlling the storing of the respective storage state in the respective storage cell (140a, 140b,..., 140n). The counter circuit (110) is configured to change the counter state, when a first edge (E1) of a cycle (CY) of the clock signal (CLK) is applied to the counter circuit (110), and to generate the write control signal (WRITE), when a second edge (E2) of the cycle (CY) of the clock signal (CLK) being subsequent to the first edge (E1) of the cycle (CY) of the clock signal (CLK) is applied to the synchronization circuit (160).
A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a pluralityof pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.
An image sensor system has a pixel array (PIX1) with a plurality of pixels (PXL1, PXL2, …, PXLN), each of the pixels comprising a photodiode (PD), a pixel buffer (SF) and a transfer gate (TX) coupled between the photodiode (PD) and an input of the pixel buffer (SF). A voltage supply block (VSB) is configured to generate a pixel supply voltage (VDDPIX) from an input voltage (VDD) based on a first reference voltage (VR1) and to provide the pixel supply voltage (VDDPIX) to the pixel array (PIX1). A calibration processing block (PROC) is configured to determine an average pixel signal (VPA) based on an average of individual pixel signals at outputs of the pixels of the pixel array (PIX1) and to determine a correction value (∆V) based on the average pixel signal (VPA) and a reference pixel signal (VPR). A correction processing block (CORR) is configured to determine the first reference voltage (VR1) based on a combination of a second reference voltage (VR2) and the correction value (∆V).
A pixel (1) with enhanced quantum efficiency comprises a semiconductor body (2) that has a first surface (3) configured as an entrance surface and a light capturing region (4a) configured for capturing light that is incident on the first surface (3). The pixel further comprises a structured interface (5), isolation layers (6) on at least two surfaces (7) of the semiconductor body that are perpendicular to the first surface (3), and a filter element (8) that is arranged at a distance from the first surface (3) such that light that is incident on the first surface (3) at an angle of incidence (α) smaller than a critical angle (αc) impinges on the filter element (8).
An image sensor (10) comprises an array (11) comprising rows (51, 52) and columns (71 to 73) of pixels (30), a first number N of connection lines (58 to 60) connected to a first number N of pixels (30) of the array (11), a voltage regulating circuit (15) having an output (61), a first terminal (66), and a driver circuit (12). The driver circuit (12) has a first number N of switches (62 to 64) coupled to the first number N of connection lines (58 to 60) and to the output (61) of the voltage regulating circuit (15), and a first number N of further switches (67 to 69) coupled to the first number N of connection lines (58 to 60) and to the first terminal (66). The first number N is at least two.
A pixel cell (10) comprises a pixel set with a plurality of pixels (11-14), with each pixel of the pixel set (11-14) being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell (10) further comprises a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set (11-14) and to operate the pixel set (11-14) in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel (11-14) is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel (11-14) is used to generate individual rolling shutter output signals.
H04N 5/347 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by combining or binning pixels in SSIS
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer ≥2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer ≥2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
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