A set potential (Vref) is inputted to the control terminal (G) of a voltage controlled current source (RUref) included in a reference current generating part (10), while a ground potential (Vss) is inputted to the reference terminal (S) thereof. A detecting part (20) includes voltage controlled current sources (RU1-RU4) that are series connected in four stages. The control terminal (G) of the voltage controlled current source (RU1) receives a ground potential (Vss), while the output terminal (D) thereof is connected to the output terminal of a current mirror circuit (30) via a first node (ND1). The control (G) and output (D) terminals of each of the voltage controlled current sources (RU2-RU4) are connected in common to the reference terminal (S) of a respective one of the voltage controlled current sources (RU1-RU3). The reference terminal (S) of the voltage controlled current source (RU4) is connected to the output node of a negative voltage generating circuit (NEGP). The voltage controlled current source (RUref) and voltage controlled current sources (RU1-RU4) each comprise the same voltage controlled current source (RU). A voltage (PG1), which is a detection result, is outputted from the first node (ND1).
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
2.
NONVOLATILE STORAGE DEVICE AND ITS ERASE CONTROL METHOD
A nonvolatile storage device includes a plurality of blocks as erase operation units and continuously performs a plurality of erase operations. The nonvolatile storage device includes: volatile memory cell array for storing erase setting information on whether each block is to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first read amplifier for reading the erase setting information on an object block from the volatile memory cell array according to the erase operation; and a second read amplifier for reading the erase setting information on the object block from the volatile memory cell array in response to the read operation. Since the read amplifier for reading the erase setting information stored in the volatile memory cell array is provided separately for the erase operation and the read operation, it is possible to read independently for each operation and store the erase setting information with a high storage density by using a minimum storage capacity.
A semiconductor device and a control method of the semiconductor device comprising bit lines (BL) each connected to a respective memory cell (12); a voltage control circuit (36) for controlling a voltage to be supplied from a power supply (Vcc) to the bit line (BL); a differential amplifier circuit (32) for supplying a control voltage (Vo) to the voltage control circuit (36) in accordance with both a voltage (DATAB) at a node coupled to the bit line (BL) and a reference voltage (CASBIAS); and a current source (34) for supplying a current to the differential amplifier circuit (32); wherein the current source (34) supplies a larger current to the differential amplifier circuit during a first interval, which includes a precharge, than during a second interval following the precharge.
An exhaust system includes: an exhaust pressure controller interposed in an exhaust passage and including: a pipe body including a side peripheral wall in which at least one port is formed; and a gas introduction wall for introducing an exhaust gas flowing from an upstream side of the pipe body so that the exhaust gas flows downstream without coming into direct contact with the port and vicinity thereof, one face of the gas introduction wall forming a pressure control path together with an inner face of the side peripheral wall while another face of the gas introduction wall forming an exhaust gas path along which the exhaust gas flows. The port communicates with the pressure control path, and the pressure control path communicates with the exhaust gas path at part downstream of the port.
A semiconductor device comprising semiconductor substrate (10); bit line (12) disposed therein; disposed in the bit line (12), silicide layer (22) having its side faces and bottom face surrounded by the bit line (12); ONO film (20) disposed on top of the semiconductor substrate (10); and side walls (24) with phosphorated silicon oxide film, disposed on the bit line (12) on both sides of the silicide layer (22), the side walls (24) disposed in contact with a side face of trap layer (16) within the ONO film (20). Further, there is provided a process for producing the semiconductor device.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
6.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided with a substrate (10); a semiconductor chip (20) mounted on the substrate (10); an upper connecting terminal (18) arranged on the side of the semiconductor chip (20) on the substrate (10); and a resin sealing section (24), which has an upper connecting terminal (18) penetrating the resin sealing section and seals the semiconductor chip (20) and the upper connecting terminal (18). An upper plane of the upper connecting terminal (18) is arranged lower than an upper plane of the resin sealing section (24). Such semiconductor device is stacked. A semiconductor device wherein semiconductor devices are stacked, and a method for manufacturing such semiconductor device are provided.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
7.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor device is provided with a step of arranging a sheet-like resin (33a) on the side opposite to a chip mounting section (10) of semiconductor chips (22, 24) mounted on the chip mounting section (10), and a step of forming a resin sealing section (30a) for sealing the semiconductor chips (22, 23) between the seat-like resin (33a) and the chip mounting section (10). A semiconductor device manufactured by such method is also provided. In the semiconductor device, generation of an unfilled portion or a filler dropped portion in the resin sealing section or exposure of a wire from the resin sealing section is suppressed. The semiconductor device which can reduce the sizes of a package and the method for manufacturing such semiconductor device are provided.
In a semiconductor device and a method of controlling the semiconductor device, the total number of writing bits in ones divided from data which should be programmed in a memory cell array is detected in steps (S10, S20), and the total number of the bits is compared with the number of predetermined bits in steps (S12, S22). The divided data are inverted or not inverted in response to a compared result in steps (S14, S24) or (S15, S25). The inverted or non-inverted data are programmed in the memory cell array in a step (S18). During a period of time in which the inverted or non-inverted data are programmed in the memory cell array in the step (S18), the total number of writing bits in next divided data is detected in the step (S20), and the total number of the bits is compared with the number of predetermined bits in the step (S22).
A nonvolatile storage where a memory cell including an insulating trap layer has a storage mode for storing one-bit data according to the presence of an electric charge in a first trap region, and a method of controlling the nonvolatile storage. In the initialization of first and second dynamic reference cells, charge accumulation as a presetting operation for the initialization is performed on second trap regions of the first and second dynamic reference cells synchronously with charge accumulation performed on a second trap region of the memory cell. In data rewriting, preprogram verification and preprogram operation are performed on the first trap region. In this manner, the time required for the initialization and rewriting can be shortened.
A semiconductor device includes a memory cell array (10) having a non-volatile memory cell (12), a first selection circuit (20) for connecting or disconnecting the source/drain of a transistor constituting the memory cell to/from DATAB connected to a first power supply, and a second selection circuit (30) for connecting or disconnecting the source/drain to/from ARVSS connected to a second power supply. The first selection circuit and the second selection circuit are arranged in different sides so as to sandwich the memory cell array. A semiconductor control method is also disclosed.
A semiconductor manufacturing device in which a plurality of process parameters that are processing conditions in processing a wafer using the semiconductor manufacturing device and target parameters measured from the wafer are obtained (S14, S16), multivariate analysis is carried out using the process parameters and the target parameters, a model formula describing the target parameters by using the process parameters is calculated (S18), the predicted values of the target parameters of the wafer being processed using the model formula during the execution of the processing in the semiconductor manufacturing device (S26), the process parameters of the processing are changed on the basis of the predicted values (S28), and the processing is continued (S30). A system for controlling the same and a method for controlling the same are also disclosed.
A semiconductor device comprising a stack (30) of semiconductor chips (10) each having a semiconductor substrate (12) and a first insulating layer (16) provided on the side surface of the semiconductor substrate (12) and having a recessed part (54) in the side surface thereof, and a second metal layer (24) for connecting first metal layers (20) provided in the central parts of the side surfaces in the recessed parts (54) to first metal layers (20) provided in the recessed parts (54) and provided on each semiconductor chip (10). A method for manufacturing the same is also disclosed.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A fabrication method of a semiconductor device comprises steps of forming an insulating film (12a) on a semiconductor substrate (10), forming a contact hole (14) in the insulating film (12a), forming a metal layer (18) in the contact hole (14), polishing the top part of the insulating film (12a) below the upper surface of the top part of the metal layer (18), and polishing the top part of the metal layer (18). According to the semiconductor device and its fabrication method, the size of a contact hole or the space between contact holes can be reduced.
A semiconductor device and a method for controlling such semiconductor device are provided. The semiconductor device is provided with a memory cell array having a nonvolatile memory cell; and a control circuit for programming data in the memory cell array by (b) programming a first level in a plurality of memory cells in which data is to be written, and then (c) programming a second level in the memory cells in which data is to be written. A data write time can be shortened by shortening a time for the first level programming. Furthermore, a required data storage time can be ensured by performing the second level programming.
A bias voltage supplied to a memory cell array is selected between a boosted voltage boosted from an external voltage and a non-boosted voltage. In the period during which a DC-DC converter circuit supplies the boosted voltage boosted from the external voltage to an internal bias line for supplying the bias voltage to the memory cell array, a non-boosted voltage supply circuit for supplying the non-boosted voltage not exceeding the external voltage is put into the halt state. In the period during which the non-boosted voltage supply circuit supplies the non-boosted voltage to the internal bias line, the DC-DC converter circuit is put into the halt state. Sufficient power supply ability is ensured by using the DC-DC conversion circuit in the period during which the boosted voltage is supplied to the internal bias line, and the DC-DC converter circuit is maintained in the halt state in the period during which the non-boosted voltage is supplied to the internal bias line. In the period during which the boosted voltage is not required, the power consumption of the DC-DC converter circuit can be reduced.
A semiconductor device comprises a first substrate (semiconductor chip 20), an anisotropic conducting film (22), and a second substrate (semiconductor chip). The anisotropic conducting film (22) is provided on the first substrate and has a wiring pattern (24) having at least a conductive portion through the front and back. The second substrate is provided on the anisotropic conducting film (22) and is electrically connected through the wiring pattern (24) of the anisotropic conducting film (22) to the first substrate. A fabrication method of the semiconductor device and a film of the semiconductor device are also disclosed. According to the semiconductor device, its fabrication method, and film fabrication method, it is possible to reduce the manufacturing cost for electrically connecting different portions of the upper and lower substrates.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
17.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Disclosed is a semiconductor device comprising a first semiconductor chip (20) arranged on a substrate (10), a first encapsulation resin portion (26) for sealing the first semiconductor chip (20), a built-in semiconductor device (30) arranged on the first encapsulation resin portion (26), and a second encapsulation resin portion (36) which seals the first encapsulation resin portion (26) and the built-in semiconductor device (30) while covering a side face (S) of the substrate (10). This semiconductor device can be reduced in size and cost while having good quality. Also disclosed is a method for manufacturing such a semiconductor device.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor device comprises a first sector (12), a second sector (14), a sector selection circuit (16), and an SRAM array (30) (memory device). The first sector (12) has a plurality of flash memory cells whose data are all erased. The second sector (14) has a plurality of flash memory cells whose data are all held. The sector selection circuit (16) selects both the first and the second sector from a plurality of sectors when erasing the data in the first sector. The SRAM array (30) is used for holding the data stored in the second sector. A control method of the semiconductor device is also disclosed. The semiconductor device and its control method can reduce the sector selection circuits and accordingly the area of the memory cell array.
A semiconductor device is provided with a groove section (11) formed on a semiconductor substrate (10); first ONO films (18) arranged on both side planes of the groove section (11); and first word lines (22) arranged on side planes of the first ONO films (18) and extend in the longitudinal direction of the groove section (11). A method for manufacturing such semiconductor device is also provided. By the semiconductor device and the method for manufacturing the same, high storage capacity can be achieved.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
20.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor device comprises trenches (11) formed in a semiconductor substrate (10), a first ONO film (18a) provided on both sidewalls of the trenches (11), a second ONO film (18b) provided on the semiconductor substrate (10) between the trenches (11), a first word line (22) provided on a sidewall of the first ONO film (18a) and extending in the longitudinal direction of the trenches (11), and a second word line (24) provided on the second ONO film (18b), extending in the longitudinal direction of the trenches (11), and electrically isolated from the first word line (22). A fabrication method of the semiconductor device is also disclosed. Thus, a semiconductor device having an improved memory capacity and its fabrication method are provided.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
21.
MEMORY DEVICE, CONTROL METHOD OF MEMORY DEVICE, AND CONTROL METHOD OF MEMORY CONTROL APPARATUS
When a memory cell area as a unit of erasing, is defined as a sector (S) and units of reading and/or writing are defined as blocks (B0 to B3) in the section, a block address (BA) selecting one of the blocks (B0 to B3) is held in a block address buffer (BAB) (3). The holding operation is performed prior to a reading or writing operation, and according, the block address need not be input again in the following reading or writing operation. One of selection signals (YDn) (n = 0 to 3) is selected according to the held block address (BA), and one of the blocks is selected according to the selection signals (YDn). Since this condition is maintained until the block address (BA) held in the block address buffer (BAB) (3) is rewritten, the block address (BA) need not be input and decoded each time reading or writing operation is performed and the access operation can be performed at a high speed and with a low current consumption.
In a memory device having a memory cell array divided into a plurality of blocks and a redundancy repairing function performed on a block basis, a block address (BA) for specifying a block is input prior to an access operation to an individual cell in the block, and a block redundancy decision is performed on the input block address (BA). Therefore, it is not required to input a block address (BA) and perform a redundancy decision thereon each time access operation is performed. The time required to start the access operation to a memory cell can be shortened, thereby improving the access speed.
A semiconductor device comprises a resistor (R11) (a first resistive element) and an FET (15) (a second resistive element) connected in series between a power supply (Vcc) (a first power supply) and a ground potential (a second power supply), an output node (N11) provided between the resistor (R11) and the FET (15) and outputting a reference voltage, a feedback node (N12) provided between the power supply (Vcc) and resistor (R11), and a voltage control circuit (19) receiving the voltages of the output node (N11) and the feedback node (N12) and controlling the voltage of the feedback node to be maintained constant. The semiconductor device can have a reference voltage generating circuit capable of generating a reference voltage with a small dependence on the power supply. A control method of this semiconductor device is also disclosed.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
H03F 1/34 - Negative-feedback-circuit arrangements with or without positive feedback
24.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided with an insulating layer (14) arranged on a semiconductor substrate (12); a P-type semiconductor region (16) arranged on the insulating layer; an element isolating region (18), which surrounds the P-type semiconductor region and is electrically isolated up to the insulating layer; an N-type source region (20) and an N-type drain region (22) arranged on the P-type semiconductor region; and a charge storage region (30) arranged on the P-type semiconductor region between the N-type source region and the N-type drain region. In the charge storage region, a charge status of four values or more can be programmed, and in the P-type semiconductor region, different voltages are applied for programming each charge status. In a flash memory for storing multiple values, Vth control of a transistor constituting a memory cell can be easily performed.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device and a method for controlling the same, the semiconductor device comprising a memory cell array including, in different areas in a charge storage layer, a plurality of nonvolatile memory cells into which first and second bits are written; an SRAM array (first storage device) that holds data to be written into the memory cell array; and a WR sense amplifier block (second storage device) that holds first and second divided data into which the data is divided in a predetermined unit and which are to be written into the first and second bits, respectively; wherein the first divided data is written into the memory cell array (Step S22), and thereafter, the second divided data is written into the memory cell array (Step S22). According to the present invention, the write time can be shortened.
A semiconductor device is provided with an insulating layer (14) arranged on a semiconductor substrate (12); a P-type semiconductor region (16) arranged on the insulating layer; an element isolating region (18) which surrounds the P-type semiconductor region and reaches the insulating layer; an N-type source region (20) and an N-type drain region (22) arranged on the P-type semiconductor region; a charge accumulating region (30) arranged on the P-type semiconductor region between the N-type source region and the N-type drain region; and a voltage applying section for applying a different voltage to the P-type semiconductor region at the time of programming or erasing or reading the data of a memory cell having the charge accumulating region.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
There is provided a semiconductor device including; a pump circuit (10) for boosting an output node connected to a memory cell array; an oscillator (12) for outputting clock to the pump circuit; and a detection circuit (16) for operating the oscillator if the voltage of an output node (17) of the pump circuit is lower than a first reference voltage and stopping the oscillator if the voltage of the output node is higher than a second reference voltage. A control method of the semiconductor device is also disclosed. The oscillator is stopped when the voltage of the output node of the pump circuit is equal to or greater than a target voltage. For this, the pump circuit is also stopped. Accordingly, there is no case that unnecessary charge flows to the ground. Thus, it is possible to reduce power consumption of the boosting circuit.
A semiconductor device is provided with a bit line (12) arranged in a semiconductor substrate (10); an ONO film (14) arranged on the semiconductor substrate (10); a word line (16) which is arranged on the ONO film (14) and extends in a width direction of the bit line (12); and a dummy layer (44) which extends in a longitudinal direction of the bit line (12) and is arranged in a bit line contact region (40) wherein a contact hole (32) is formed for connecting the bit line (12) with a wiring layer (34). Distribution of the word line width and distribution of the width and shape of a side wall layer can be suppressed or a leak current between the bit line and the semiconductor substrate can be suppressed.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
29.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Disclosed is a semiconductor device comprising a lower wiring layer (first metal layer) (16) formed on a semiconductor substrate, an interlayer insulating film (22) formed on the lower wiring layer (16), a plug metal (26) which is formed in a contact hole (opening) formed in the interlayer insulating film (22) in contact with the lower wiring layer (foundation layer) (16) and connected with the lower wiring layer (16), and a first barrier layer (24) formed between the plug metal (26) and the interlayer insulating film (22) and having a chemical composition different from that of the lower wiring layer (foundation layer). Also disclosed is a method for manufacturing such a semiconductor device. In this semiconductor device, the contact resistance between the plug metal (26) and the lower wiring layer (16) can be reduced.
Storage areas for general and control information are assigned in a memory cell array. The storage area for control information comprises a predetermined number of control information storage memory cells provided for each single bit. The predetermined number of control information storage memory cells store data for the same bit and are simultaneously read out. Since each bit of the control information is read out simultaneously from the predetermined number of memory cells, the drivability of a read path activated during a read operation is enhanced. It is possible to reduce the time required to read the control information during the initial setting period when power-on and reset operations are performed and therefore to quickly enter a normal access operation.
A semiconductor device includes MOS transistors formed by doping a p-type substrate (4) with an impurity from its surface of. The semiconductor device comprises first and second MOS devices (1A, 1B) each having the p-type substrate (4) having the region directly below a gate layer (5) not doped with the impurity and an n-type diffusion region formed on the surface of the p-type substrate (4) circumscribed to the gate layer (5). The gate layer of the first MOS device (1A) is connected to the n-type diffusion layer of the second MOS device (1B), and the n-type diffusion layer of the first MOS device (1A) is connected to the gate layer of the second MOS device (1B), thereby constituting a first capacitance element.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8236 - Combination of enhancement and depletion transistors
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
32.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), an insulation film line (18) continuously arranged on the bit lines (14) in the longitudinal direction of the bit line (14), a gate electrode (16) arranged between bit lines (14) on the semiconductor substrate (10), a word line (20) arranged on the gate electrode (16) and extending in the width direction of the bit lines (14), and a trench portion (22) formed between the bit lines (14) and the word lines (20) on the semiconductor substrate. A method for fabricating the semiconductor device is also disclosed. It is possible to provide a semiconductor device and a fabrication method thereof capable of separating elements between the word lines (14) and making a fine memory cell.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device comprises a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected through a reference data line (24) to a reference cell (22), a sense amplifier (18) for sensing the outputs of the first and second current-voltage conversion circuits, a comparison circuit (28) for comparing the voltage value at the reference cell data line with a predetermined voltage value, and a charging circuit (30) for charging the reference cell data line during the precharge period thereof if the voltage value at the reference cell data line is lower than the predetermined voltage value. A control method of the semiconductor device is also disclosed. The semiconductor device and its control method can reduce the precharge time of the reference cell data line and therefore the data read time.
A method of producing a semiconductor device comprising the step of forming stopper layers (32) including oxide/nitride silicon films on part of a semiconductor substrate, the step of forming a cover film (34) having a surface higher than the surface of the stopper layers between and on the stopper layers, and the step of grinding the cover layer down to the stopper layers using ceria slurry as an abrasive. A semiconductor device comprising metal layers (30) provided on part of a semiconductor substrate, oxide/nitride silicon films (32) provided on the metal layers, and a buried layer (36) provided between metal layers on the semiconductor substrate and having a surface practically flush with the surfaces of the oxide/nitride silicon films. Accordingly, the semiconductor device having films excellent in surface flatness, and a production method therefor can be provided.
Disclosed is a semiconductor device comprising an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) which is formed in contact with the bit line (20) so as to extend in the longitudinal direction of the bit line and contains a polycrystalline silicon layer or a metal layer. In this semiconductor device, deterioration in write/erase characteristics and transistor characteristics such as junction leakage can be suppressed and the bit line resistance (the resistance of two layers, namely the bit line (20) and the conductive layer (32)) can be decreased. Also disclosed is a method for manufacturing such a semiconductor device.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
36.
SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing apparatus includes an upper die, a lower die, and a plate, which includes a cavity wherein a resin is injected and which specifies an outer shape and a thickness of a resin sealing section, and a gate for guiding the resin to the cavity, and is inserted between the upper die and the lower die. The plate further includes a resin film fixed by either cohesion or adhesion on a side which comes into contact with a substrate electrode. A semiconductor device having no resin burr generated on the substrate at an end plane portion of a molding can be provided. In the plate, pluralities of thin plates are bonded in layers by welding.
A semiconductor device includes a normal cell array unit (30), a redundant cell array unit (31) for the normal cell array unit (30), and a PGM/ER state machine (20) used when programming to a sector of the normal cell array unit (30) has failed, for re-programming the data which has failed to be programmed and data already written in the sector of the normal cell array unit (30) in the redundant cell array unit (31). When programming has failed, data which has failed to be programmed and the data already written in the sector is re-programmed in the redundant cell array unit (31). Accordingly, it is possible to prevent loss of data and guarantee data. This improves the reliability of the system.
The conduction/non-conduction control of a first switch circuit (T1) is periodically performed in accordance with an error amplifying circuit (A1), thereby discharging a power, which has been stored from an input voltage (VIN) into an inductance circuit (L1), to a memory cell array (11) via a rectifying circuit (D1) to supply a bias voltage (VPP) that has been boosted up to a set value. At this moment, a voltage adjusting part (13) directly adjusts the voltage value of the bias voltage (VPP) by operating the error amplifying circuit (A1) of a boosted voltage supplying part (12) in accordance with counter information (COUNT) and positional information (AD) of target memory cells to which the bias voltage (VPP) is to be applied. In this way, even if the storage capacity is to be enlarged, a bias voltage, which has been boosted by a sufficient supply capability, can be supplied to the memory cell array. Moreover, the set voltage can be adjusted in accordance with the positions of target memory cells, thereby supplying thereto the suitable boosted voltage regardless of the positions and number of the target memory cells.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
39.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Disclosed is a semiconductor device comprising a bit line (14) embedded in a semiconductor substrate (10), a first wiring (24) formed on and connected to the bit line, and a second wiring (30) formed on the first wiring for connecting the first wiring with a transistor in a peripheral circuit region. In this semiconductor device, the first wiring is connected with the transistor in the peripheral circuit region only through the second wiring. Also disclosed is a method for manufacturing such a semiconductor device. Further disclosed are a semiconductor device comprising a first wiring connecting a bit line with a transistor in a peripheral circuit region and a dummy contact hole (44) located between the bit line and the transistor, and a method for manufacturing such a semiconductor device. The present invention enables to provide a highly reliable flash memory wherein loss of electric charge from an ONO film (12) is suppressed.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device is provided with a regular cell (16) which is arranged in a regular sector (10) and connected to a word line (14); and a plurality of reference cells (26) to be used at the time of reading data from the regular cell (10). In the semiconductor device, one of the reference cells (26) is selected corresponding to a word line distance of the regular cell (16) which reads data. A difference between output delay times to a sense amplifier (30) from the regular cell (16) and the reference cell (26) is reduced, and a chip area is reduced or a speed of sense operation is increased.
A semiconductor device is provided with a semiconductor substrate (10); a high concentration diffusion region (22) formed in the semiconductor substrate (10); a first low concentration diffusion region (24) arranged under the high concentration diffusion region (22) with an impurity concentration lower than that of the high concentration diffusion region (22); and a bit line (30b) which includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves also as a source region and a drain region. A method for manufacturing such semiconductor device is also provided. Deterioration of the source/drain withstand voltage of a transistor can be suppressed, and the low-resistance bit line (30b) can be formed. Thus, the semiconductor device having a microminiaturized memory cell and the method for manufacturing such semiconductor device are provided.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
42.
SEMICONDUCTOR DEVICE, DATA READ OUT METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device includes a pair of metal wirings; a program layer formed on the metal wirings with an opening selectively formed in accordance with writing information; and a read out circuit for reading out information decided by the capacitance, which changes between the pair of metal wirings depending on whether the opening is formed on the program layer or not. The program layer is formed of, for instance, a material having a dielectric constant higher than that of air. The program layer is formed of, for instance, a material and a conductor having a dielectric constant lower than that of air. Thus, by detecting the information decided by the capacitance which changes depending on whether there is an opening or not, trimming information and information of device ID and the like can be stored, even in a logic device not having a memory transistor.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
43.
SEMICONDUCTEUR DEVICE AND METHOD FOR MANUFACTURING SAME
Disclosed is a semiconductor device comprising a gate electrode (31) formed on a semiconductor substrate (10), an ONO film (18) which is formed between the gate electrode and the semiconductor substrate and has a charge storage region located below the gate electrode (31), and a bit line (28) which is buried in the semiconductor substrate (10) and includes a low-concentration diffusion region (24), a high-concentration diffusion region (22) formed in the central portion of the low-concentration diffusion region (24) and having a higher impurity concentration than the low-concentration diffusion region (24), a source region and a drain region. In this semiconductor device, the source/drain withstand voltage is improved and fluctuation of electrical characteristics or junction current between the bit line and the semiconductor substrate is suppressed.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
44.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided with a bit line (14) embedded in a semiconductor substrate (10); a word line (16) which crosses over the bit line (14) and extends in a width direction of the bit line; a wiring layer (22) which crosses over the word line (16) and extends in a longitudinal direction of the bit line; and a bit line contact region (28) which extends in a longitudinal direction of the word line and is arranged between word line regions (26) wherein the plurality of word lines are arranged. In the bit line contact region, the wiring layer is connected with every other bit line. A method for manufacturing such semiconductor device is also provided. The semiconductor device wherein an alignment margin for the contact hole and the bit line is ensured and a memory cell is microminiaturized, and the method for manufacturing such semiconductor device are provided.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device is provided with a gate electrode (12) formed on a semiconductor substrate (20); two source and drain regions (14) formed in the semiconductor substrate on the both sides of the gate electrode; a transistor having two or more charge accumulating regions; a bit line (10) connected to the source and drain regions; and a word line (12) connected to the gate electrode. The direction of a current flowing between the two source and drain regions is in the direction of the width of the word line. Since the direction of the current flowing between the source and drain regions is in the direction of the width of the word line, the bit line can be formed separately from the source and drain regions. Thus, the semiconductor device wherein a memory cell is microminiaturized is provided.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
46.
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SAME
A semiconductor device includes a nonvolatile memory cell array; a write/read circuit for writing and reading on and from the nonvolatile memory cell array; a data input/output circuit; and a volatile memory cell array, which includes a first latch circuit connected to the write/read circuit for holding first data, and a second latch circuit connected to the data input/output circuit for holding second data. Furthermore, the semiconductor device includes an inverting circuit, which inverts the first write data corresponding to the number of bits for performing a program in the first write data, and a control circuit, which controls the second write data to be latched by the second latch circuit while the first write data is being written in the nonvolatile memory cell. The semiconductor device having a small circuit area is provided by shortening a write time.
A stacked type semiconductor device is provided with a semiconductor element (1) mounted on a substrate (4); a first sealing resin (12) for sealing the semiconductor element (1); a chip (9) arranged on the first sealing resin (12); and a second sealing resin (13) for sealing the semiconductor element (1) sealed with the first sealing resin (12) and the chip (9). In such package structure, since there exists no external connecting terminal such as a bump between the chip (9) and the substrate (4), sealing can be easily performed with the second sealing resin (13). Furthermore, since the chip (9) is directly arranged on the first sealing resin (12), a heat conducting path is wider than a conventional one, and wiring by wire bonding can be stably performed.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
48.
SEMICONDUCTOR DEVICE AND REFERENCE VOLTAGE GENERATING METHOD
A semiconductor device is provided with a first internal reference cell (4), a second internal reference cell (5), an external reference cell (6), and at least two current mirror circuits. The semiconductor device has cascode circuits (15, 16, 8), which output a reference voltage from a current flowing in the reference cell by corresponding to the current to at least two output paths, and switches (SWAR1, SWAR2, SWBR1, SWBR2, SWXR1, SWXR2), which are provided at least on each of the two output paths and select the output path for outputting the reference voltage. Therefore, the number of outputs of the reference voltage can be increased and reduced without increasing the number of reference cells. Thus, a judgment voltage obtained from such reference voltages can be easily adjusted, and reading can be performed without reducing a margin at the time of reading data from a core cell (3).
A semiconductor device is provided with a plurality of transistors (11, 13, 15, 17), which have a gate electrode (18) formed on a semiconductor substrate (30), source/drain regions (10, 12, 14, 16) formed on both sides of the gate electrode (18), and a charge accumulating layer (38) formed between the gate electrode (18) and the semiconductor substrate (30). The source/drain regions of the adjacent transistors are connected in series, and the plurality of transistors form a closed loop. The semiconductor device is a logical circuit which can reconfigure a circuit function in a nonvolatile manner, has wide selectivity in circuit design and excellent design efficiency and permits a nonvolatile memory to be manufactured in a same chip.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
50.
IC CARRIER, IC SOCKET AND METHOD FOR TESTING IC DEVICE
An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a package. The IC device has, on a second surface opposite the first surface, (a) a central protrusion (30), (b) a peripheral portion (32) lower than the protrusion by one step, and (c) upper electrodes (18) formed on the peripheral portion of the IC device. The IC carrier is provided with a frame (36), a cover (40), and a holding means (42). The frame forms a device reception space (38) for receiving the IC device. The cover can cover the upper electrodes while in contact with the periphery of the IC device held on the IC carrier. The holding means can hold the IC device on the IC carrier with the cover covering the upper electrodes of the IC device. The IC device can be set in an IC socket while being mounted on the IC carrier.
H01R 33/76 - Holders with sockets, clips or analogous contacts, adapted for axially-sliding engagement with parallely-arranged pins, blades, or analogous contacts on counterpart, e.g. electronic tube socket
51.
STORAGE APPARATUS AND STORAGE APPARATUS CONTROL METHOD
An access discriminating circuit (4) discriminates between a first access operation, in which a column address (CADD), which is a burst address, is detected, a word line is updated, a new memory cell (MC) is selected and then stored data is read, and a second access operation, in which memory cells (MC) connected commonly to an already selected word line are selected by sequentially switching column selection switches, to output an discrimination signal (S). Operation condition information (Dx (DAx or/and DBx)), which is used for establishing a load condition in a dummy load circuit (5) or/and for establishing a pulse width of an equalization signal (EQ) in an amplifying control circuit (6), is stored in first and second storing parts (1,2) for each of the first and second access operations, and selected by a selector circuit (3) in accordance with the discrimination signal (S) for application to the dummy load circuit (5) or/and the amplifying control circuit (6). Operational conditions suitable for the respective access operations are selected.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
52.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Disclosed is a semiconductor device comprising a semiconductor substrate (10) having a bit line (14), an ONO film (16) formed on the semiconductor substrate and having an opening (46), and an interlayer insulating film (30) formed on the ONO film and having a contact hole (40) which is arranged in the opening and connected with the bit line. In this semiconductor device, the ONO film and the contact hole are separated from each other and the insulating film intervenes between the ONO film and the contact hole. When the contact hole is formed in the interlayer insulating film, formation of damaged areas in the ONO film can be prevented since the ONO film is separated from the contact hole. Consequently, loss of electric charges from the trap layer due to a damaged area is suppressed, thereby making the semiconductor device highly reliable.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
53.
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME
A nonvolatile semiconductor memory comprises a first decoder that includes a pull-up transistor for selecting and driving a word line connected to memory cells; a first voltage generating circuit that generates a first voltage to be applied to the source terminal of the pull-up transistor; a second voltage generating circuit that generates a second voltage, higher than the first voltage, to be applied to the gate terminal of the pull-up transistor; vertical word lines each of which connects a plurality of sectors in the vertical direction and supplies the first voltage to the source terminal of the pull-up transistor; global word lines each of which connects a plurality of sectors in the horizontal direction and supplies the second voltage to the gate terminal of the pull-up transistor; a second decoder that selects and drives a global word line; and a third decoder that selects and drives a vertical word line. The size of the transistor of a word line driver can be reduced.
A BIST control circuit (1) performs a test by selecting bit lines sequentially against a selected word line, thereby to detect a defective position at the unit of a fundamental column area discriminated with the least significant address signal (An). The completion of the bit line selection on the word line selected with a maximum column address signal (MAXCA) is grasped to raise a column redundancy flag (RCOL), in case the defect is detected in a single fundamental column area, and to raise a sector redundancy flag (RSEC) in case a defective portion exists in a plurality of fundamental column areas. In accordance with the completion of the test on the selected word line, therefore, the column redundancy or the sector redundancy is selected to perform an efficient redundancy relief.
A semiconductor device is provided with a semiconductor substrate (10); an ONO film (16) formed on the semiconductor substrate; a bit line (14) formed in the semiconductor substrate; and a connecting section (40) electrically connected to the bit line (14). The semiconductor substrate is provided with trench isolating regions (50) arranged on the both sides of the bit line so as to sandwich the connecting section. Thus, even when overlapping of the bit line with the connecting section is shifted in a vertical direction, since the connecting section is formed on the trench isolating region, the bit line and the semiconductor substrate are prevented from leaking through the connecting section. A margin for overlapping the bit line with the connecting section is reduced, and the semiconductor device by which a memory cell can be miniaturized and a method for manufacturing such semiconductor device are provided.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
An extended sector enable signal (RS_SEL) is a test target control signal for switching the test target between a normal sector and a redundant sector. During a testing of the redundant sector, if a bad redundant sector signal (RSECF) is at a high level (a selected redundant sector is a bad sector), then a forcing signal (FMATCH) is rendered at a high level. In response to the forcing signal (FMATCH) at the high level, a coincidence signal (MATCH) is rendered at a high level by force. Then, the verify operation is skipped for the bad sector. In this way, an address signal that identifies a normal memory block can be utilized for identifying a redundant memory block.
Disclosed is a semiconductor device comprising a semiconductor substrate (10) having source/drain diffusion regions (14), and a control gate (20) formed on the semiconductor substrate (10). The surface of the semiconductor substrate is provided with a groove portion (18) which is positioned below the control gate (20) while being arranged between the source/drain diffusion regions (14). By lengthening the effective channel length, a certain channel length for storing electric charges can be secured in this semiconductor device, while enabling miniaturization of memory cells. Also disclosed is a method for manufacturing such a semiconductor device.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
A semiconductor device is provided with an ONO film (17) formed on a semiconductor substrate (15), a first gate (14) formed on the ONO film, a source (10) and a drain (12) formed on a side section which the first gate faces, and a second gate (16). The second gate is a side gate formed on the side sections other than the side section which the first gate faces. Thus, a desired circuit characteristic can be obtained by a nondestructive means in a nonvolatile manner, and a number of trial manufactures for IC development can be reduced.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
patents