Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
Topologies for analog processors may include cells comprising at least portions of qubits and couplers. Qubits and couplers may be shared among or extend across multiple cells. A cell may include four sets of partial qubits, and partial qubits may form whole qubits with partial qubits in adjacent cells. First and second sets of partial qubits may include partial qubits that extend substantially parallel to one another and along a first direction. Third and fourth sets may include partial qubits that extend substantially parallel to one another and along a second direction. Each partial qubit in the first and second sets may cross, and be substantially orthogonal to, at least one partial qubit from each of the third and fourth sets. A cell may include first and second sets of intra-cell couplers, and partial couplers that form inter-cell couplers with partial couplers in adjacent cells.
A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
Systems and methods for optimization algorithms, updating samples, and penalizing constraint violations are discussed. A method for updating samples includes receiving a problem definition with an objective function and constraint functions, an initial sample, and a value for a progress parameter. For each variable a total energy change is determined based on an objective energy change based on the sample value for the variable and one or more terms of the objective function that include the variable and a constraint energy change based on the sample value for the variable and each of the constraint functions defined by the variable. A sampling distribution is selected based on the variable type and an updated value is sampled based on the total energy change and the progress parameter. An updated sample is returned with an updated value for each variable of the set of variables. Such may improve operation of processor-based systems.
A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.
Systems and methods for operating a computer system to generate samples having improved diversity are discussed. A processor receives a problem definition with a problem Hamiltonian defined over a set of variables and samples one or more values for the set of variables from the problem Hamiltonian, the one or more values for the set of variables comprising a first set of samples. At least a subset of the first set of samples is selected, and a diversity Hamiltonian based on the at least a subset of the first set of samples is generated. The problem Hamiltonian and the diversity Hamiltonian are combined to generate a combined Hamiltonian, and one or more values for the set of variables are sampled from the combined Hamiltonian, the one or more values for the set of variables comprising a second set of samples.
Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
Systems and methods for random number generation are discussed. A first processor is in communication with a quantum processor, the quantum processor having an array of superconducting qubits. The first processor instructs the quantum processor to selectively communicatively couple the superconducting qubits to embed a quantum system having a highly entangled nontrivial ground state. The highly entangled nontrivial ground state comprising a uniform distribution of classical ground states. One or more distortions are introduced to the uniform distribution by one or more random variations based on an input value. The quantum processor evolves over the embedded quantum system. A set of one or more random numbers is received from the quantum processor.
Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
Systems and methods for operation of a computing system to direct a search space for an optimization problem are described. One or more processors initialize an optimization algorithm, and iteratively until a termination criteria is met: receive a sample solution from the optimization algorithm, evaluate quality and feasibility of the sample solution, and where the sample solution is feasible and has the best quality so far, freeze one or more penalty parameters for a set number of iterations. Where the sample solution is not feasible or does not have the best quality so far, the one or more penalty parameters are updated based on a finite state machine, the updated one or more penalty parameters are returned to the optimization algorithm, the optimization algorithm is incremented, the termination criteria is evaluated, and when the termination criteria is met, one or more sample solutions are returned.
There is provided a system and methods of training and predicting an outcome using quantum annealing-assisted reservoir computing. The methods are performed by a digital computer in communication with a quantum processor including a plurality of qubits. Methods include: receiving input data; initializing first states of the qubits; and, for each input: determining values of Hamiltonian parameters based on the input, programming the quantum processor based on the determined Hamiltonian parameters, performing an annealing protocol to evolve the qubits to second states, and applying a linear transformation to the second states to determine a predicted output. During training, a set of linear parameter weights are optimized using linear regression. As part of the annealing protocol, reverse annealing is performed to a point in the quantum critical region having maximally complex dynamics, therefore measured second states are highly separable in the higher dimensional space for providing high-accuracy predicted outputs.
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/04847 - Interaction techniques to control parameter settings, e.g. interaction with sliders or dials
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
G06F 16/901 - Indexing; Data structures therefor; Storage structures
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
G06T 11/20 - Drawing from basic elements, e.g. lines or circles
15.
Systems and methods for tuning capacitance in quantum devices
Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.
A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.
Methods and systems for calibrating quantum processors are discussed. A model of a portion of the processor to be calibrated has one or more determinable parameters and an uncertainty for the determinable parameter(s). A measurement procedure is iteratively performed by selecting a subset of possible measurements and generating predicted measurement outcomes and predicted uncertainties for the determinable parameter for each measurement in the subset of possible measurements. Based on the predicted reduction in uncertainty for the determinable parameter, one or more measurements is selected. Instructions are transmitted to the quantum processor to perform the selected measurements, and the results are returned to update the model of the portion of the processor to be calibrated. Once a termination criteria is met, a calibrated value is generated for the determinable parameter. Compensating signals can be applied to devices of the quantum processor to calibrate the devices.
G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
19.
THERMALLY ISOLATING CABLING ASSEMBLIES, SYSTEMS USING THERMALLY ISOLATING CABLING ASSEMBLIES, AND METHODS OF FABRICATING THERMALLY ISOLATING CABLING ASSEMBLIES
Thermally isolating cable assemblies, systems using the assemblies, and methods for fabricating the assemblies are discussed. A cable assembly includes a first shielding cable comprising a first solderable material interleaved with a section of a second shielding cable comprising an exterior material that is a second solderable material and an inner material that is superconductive at and below a critical temperature. The cable assembly may be fabricated during the assembly of an apparatus, and, following assembly of the apparatus, a segment of the second shielding cable is etched to expose a portion of the inner material. Following fabrication of the cable assemblies, the apparatus may be installed in a cryogenic environment in which the inner material may be operable as a superconductor and may thermally isolate the cabling assembly distal to the exposed portion to reduce heat load to a superconducting circuit.
In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
Systems and methods for measuring noise in discrete regions of multi-layer superconducting fabrication stacks are described. Methods for measuring noise in spatial regions of a superconducting fabrication stacks may include the use of resonators, each having a different geometry. As many resonators as spatial regions are fabricated. Data collected from the resonators may be used to calculate fill fractions and spin densities for different spatial regions of the superconducting fabrication stack. The data may be collected via on-chip electron-spin resonance. The superconducting fabrications may be part of a fabrication stack for a superconducting processor, for example a quantum processor, and the spatial region studied may be proximate to qubit wiring layers.
Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
In a superconducting quantum processor, inductance is a characteristic of superconducting flux qubits and used to achieve coupling between qubits. In general, higher qubit energy scale results in better quantum processor performance. Energy scale of qubits can be increased by reducing inductance. For each Ising spin problem, qubit energy scale can be increased by determining the unused inductance-tuner range for each qubit and the minimum homogenized inductance achievable across all qubits, then adjusting the inductance-tuner to achieve the minimum homogenized inductance. When the inductance of a qubit is changed, there is a shift in the CCJJ bias at which quantum annealing is performed for that qubit. The variation in CCJJ bias shift can be compensated by computing the shift in CCJJ bias due to the applied inductance and applying a compensating CCJJ bias via the CCJJ offset DAC.
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
A heuristic solver is wrapped in a meta algorithm that will perform multiple sub-runs within the desired time limit, and expand or reduce the effort based on the time it has taken so far and the time left. The goal is to use the largest effort possible as this typically increases the probability of success. In another implementation, the meta algorithm iterates the time-like parameter from a small value, and determine the next test-value so as to minimize time to target collecting data at large effort only as necessary. The meta algorithm evaluates the energy of the solutions obtained to determine whether to increase or decrease the value of the time-like parameter. The heuristic algorithm may be Simulated Annealing, the heuristic algorithm may run on a quantum processor, including a quantum annealing processor or a gate-model quantum processor.
A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.
Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.
Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.
In an implementation, a tunable traveling wave parametric amplifier (TWPA) includes a T-stage that includes a first DC-SQUID and a first interface inductively communicatively coupled to the first DC SQUID operable to apply a first bias to the first DC SQUID. The T-stage also includes a second DC-SQUID electrically communicatively coupled to the first DC-SQUID in series via a center node, and a second interface inductively communicatively coupled to the second DC-SQUID operable to apply a second bias to the second DC-SQUID. The TWPA also includes a shunting resonator communicatively coupled to the center node via a coupling capacitance. The shunting resonator includes a third DC-SQUID, and a third interface inductively communicatively coupled to the third DC SQUID operable to apply a third bias to the third DC SQUID. The first, second, and third biases are adjustable to improve a bandwidth of the tunable TWPA.
Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
G06F 17/18 - Complex mathematical operations for evaluating statistical data
G06F 18/21 - Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
G06F 18/23213 - Non-hierarchical techniques using statistics or function optimisation, e.g. modelling of probability density functions with fixed number of clusters, e.g. K-means clustering
35.
SYSTEMS AND METHODS FOR QUANTUM COMPUTING USING FLUXONIUM QUBITS WITH KINETIC INDUCTORS
A superconducting device may have a body loop comprising a body loop comprising a Josephson junction structure and a kinetic inductor. The superconducting device can be a qubit in a quantum processor for performing gate-model quantum computation. The superconducting device may be fabricated with a single wiring layer embedded in a single-crystalline substrate trench. The superconducting device may be fabricated with a wiring layer and an insulating layer in a single-crystalline substrate trench. The superconducting device may be fabricated with multiple wiring layers embedded in a single-crystalline substrate trench. The device may be fabricated by defining trenches in the single-crystalline substrate, with the trenches having a depth matching the desired numbers of wiring layers and insulating layers.
A superconducting flux qubit readout system may include an input-output system connected to at least one shift register, the shift register comprising a first set, a second set, and a third set of shift register stages arranged in series, the first set of shift register stages coupled to a first set of qubits by a first plurality of latches, and the second set of shift register stages coupled to a second set of qubits by a second plurality of latches. Reading out states of a first set of qubits may include: shifting qubit state information to first holding latches communicatively coupled to a shift register; obtaining, by each shift register stage of the first set of shift register stages, state information from the first holding latches; and, propagating information along the shift register.
A temperature stabilization technique for a digital-to-analog converter (DAC). The DAC is kept operating while a load, for example an analog computer, is disconnected from the DAC in order to reduce temperature changes that otherwise occur when the DAC is idle. The DAC may be supplied with adjusted input to compensate for changes in dissipation caused by the removal of the load.
A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4 -qubit even-parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing super-conducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.
Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb2O5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 27/18 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components exhibiting superconductivity
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
40.
SYSTEMS AND METHODS OF HYBRID ALGORITHMS FOR SOLVING DISCRETE QUADRATIC MODELS
Methods for solving discrete quadratic models are described. The methods compute an energy of each state of each variable based on its interaction with other variables, exponential weights, and normalized probabilities proportional to the exponential weights. The energy of each variable is computed as a function of the magnitude of each variable and a current state of all other variables, exponential weights, the feasible region for each variable, and normalized probabilities, proportional to the exponential weights and respecting constraints. Methods executed via a hybrid computing system obtain two candidate values for each variable; constructs a Hamiltonian that uses a binary value to determine which candidate values each variable should take, then constructs a binary quadratic model based on the Hamiltonian. Samples from the binary quadratic model are obtained via a quantum processor. The methods can be applied to solve resource scheduling optimization problems and/or for side-chain optimization for proteins.
Topologies for analog processors may include cells comprising at least portions of qubits and couplers. Qubits and couplers may be shared among or extend across multiple cells. A cell may include four sets of partial qubits, and partial qubits may form whole qubits with partial qubits in adjacent cells. First and second sets of partial qubits may include partial qubits that extend substantially parallel to one another and along a first direction. Third and fourth sets may include partial qubits that extend substantially parallel to one another and along a second direction. Each partial qubit in the first and second sets may cross, and be substantially orthogonal to, at least one partial qubit from each of the third and fourth sets. A cell may include first and second sets of intra-cell couplers, and partial couplers that form inter-cell couplers with partial couplers in adjacent cells.
An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.
A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
45.
SYSTEMS AND METHODS FOR COUPLING A SUPERCONDUCTING TRANSMISSION LINE TO AN ARRAY OF RESONATORS
A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.
An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.
G06N 10/80 - Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
G06N 10/60 - Quantum algorithms, e.g. based on quantum optimisation, or quantum Fourier or Hadamard transforms
47.
User interface, programmer and/or debugger for embedding and/or modifying problems on quantum processors
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/048 - Interaction techniques based on graphical user interfaces [GUI]
G06F 3/04847 - Interaction techniques to control parameter settings, e.g. interaction with sliders or dials
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
G06T 11/20 - Drawing from basic elements, e.g. lines or circles
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
G06F 16/901 - Indexing; Data structures therefor; Storage structures
48.
SYSTEMS AND METHODS FOR IMPROVING COMPUTATIONAL EFFICIENCY OF PROCESSOR-BASED DEVICES IN SOLVING CONSTRAINED QUADRATIC MODELS
Systems and methods for optimization algorithms, updating samples, and penalizing constraint violations are discussed. A method for updating samples includes receiving a problem definition with an objective function and constraint functions, an initial sample, and a value for a progress parameter. For each variable a total energy change is determined based on an objective energy change based on the sample value for the variable and one or more terms of the objective function that include the variable and a constraint energy change based on the sample value for the variable and each of the constraint functions defined by the variable. A sampling distribution is selected based on the variable type and an updated value is sampled based on the total energy change and the progress parameter. An updated sample is returned with an updated value for each variable of the set of variables. Such may improve operation of processor-based systems.
G06N 10/60 - Quantum algorithms, e.g. based on quantum optimisation, or quantum Fourier or Hadamard transforms
G06N 10/80 - Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
49.
SYSTEMS AND METHODS FOR IMPROVING COMPUTATIONAL EFFICIENCY OF PROCESSOR-BASED DEVICES IN SOLVING CONSTRAINED QUADRATIC MODELS
Systems and methods for optimization algorithms, updating samples, and penalizing constraint violations are discussed. A method for updating samples includes receiving a problem definition with an objective function and constraint functions, an initial sample, and a value for a progress parameter. For each variable a total energy change is determined based on an objective energy change based on the sample value for the variable and one or more terms of the objective function that include the variable and a constraint energy change based on the sample value for the variable and each of the constraint functions defined by the variable. A sampling distribution is selected based on the variable type and an updated value is sampled based on the total energy change and the progress parameter. An updated sample is returned with an updated value for each variable of the set of variables. Such may improve operation of processor-based systems.
G06N 10/60 - Quantum algorithms, e.g. based on quantum optimisation, or quantum Fourier or Hadamard transforms
G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
G06N 10/80 - Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
50.
Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity
Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 39/22 - Devices comprising a junction of dissimilar materials, e.g. Josephson-effect devices
H01L 39/06 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the current path
52.
SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS WITH IMPROVED COHERENCE
A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 29/22 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.
Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti-ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.
A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.
H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
H01L 39/22 - Devices comprising a junction of dissimilar materials, e.g. Josephson-effect devices
In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
H01G 5/16 - Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
61.
SYSTEMS, ARTICLES, AND METHODS FOR A TUNABLE CAPACITOR
In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
H01G 5/16 - Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
62.
Kinetic inductance for couplers and compact qubits
A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples may be used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.
A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior.
A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
67.
METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
H01L 39/06 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the current path
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H01L 27/18 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components exhibiting superconductivity
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
A superconducting integrated circuit is fabricated by depositing a ground plane to at least partially overlie a substrate, depositing an insulating layer to at least partially overlie the ground plane, depositing a superconducting layer to at least partially overlie the insulating layer, and forming a superconducting feature in the superconducting layer. An inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane. The ground plane is electrically communicatively coupleable to an electrical ground. Depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material. A second critical current density of the second superconducting material is higher than a first critical current density of the first superconducting material.
H01F 6/06 - Coils, e.g. winding, insulating, terminating or casing arrangements therefor
H01F 21/00 - Variable inductances or transformers of the signal type
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
69.
DISCRETE VARIATIONAL AUTO-ENCODER SYSTEMS AND METHODS FOR MACHINE LEARNING USING ADIABATIC QUANTUM COMPUTERS
A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior. Unsupervised learning can include generating samples of a prior distribution using the quantum processor. Generating samples using the quantum processor can include forming chains of qubits and representing discrete variables by chains.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
71.
Systems and methods for operation of a frequency multiplexed resonator input and/or output for a superconducting device
A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.
A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4-qubit even- parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing superconducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.
A system and method of implementing finite element modeling on a quantum processor is discussed. A representation of a computational problem including a boundary value problem and problem grid points is received by one or more processors. The problem grid points are mapped to a Hilbert space of the qubits of the quantum processor. The boundary value problem is transformed into a problem Hamiltonian. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the problem Hamiltonian. The wavefunction amplitudes of the final state are measured, and the wavefunction amplitudes of the final state are mapped onto the problem grid points based on the Hilbert space of the qubits.
A digital processor runs a machine learning algorithm in parallel with a sampling server. The sampling sever may continuously or intermittently draw samples for the machine learning algorithm during execution of the machine learning algorithm, for example on a given problem. The sampling server may run in parallel (e.g., concurrently, overlapping, simultaneously) with a quantum processor to draw samples from the quantum processor.
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/048 - Interaction techniques based on graphical user interfaces [GUI]
G06F 3/04847 - Interaction techniques to control parameter settings, e.g. interaction with sliders or dials
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
G06T 11/20 - Drawing from basic elements, e.g. lines or circles
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
G06F 16/901 - Indexing; Data structures therefor; Storage structures
76.
SYSTEMS AND METHODS FOR OPTIMIZING ANNEALING PARAMETERS
A quantum annealing schedule for a computational problem can be adjusted by methods and systems involving one or more processors. The one or more processors proceed by receiving a representation of the computation problem, the representation including a plurality of problem values. These problem values are transformed based on a plurality of trained parameters of a machine learning model to generate at least a portion of an annealing schedule including at least one annealing parameter. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the computational problem and the at least a portion of an annealing schedule, the final state producing a result for the computational problem.
Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.
A quantum annealing schedule for a computational problem can be adjusted by methods and systems involving one or more processors. The one or more processors proceed by receiving a representation of the computation problem, the representation including a plurality of problem values. These problem values are transformed based on a plurality of trained parameters of a machine learning model to generate at least a portion of an annealing schedule including at least one annealing parameter. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the computational problem and the at least a portion of an annealing schedule, the final state producing a result for the computational problem.
A filter multiplexer for variable bandwidth annealing selection is described. The filter multiplexer has multiple pathways, where each pathway comprises a switch and a filter. Each filter has a different cutoff frequency from the other filters. Switches may be cryogenic switches. Each pathway may be communicatively coupled to an external annealing line. Upon receiving a problem, an annealing bandwidth can be selected, set or configured via the multiplexer to operate a quantum processor with a desired annealing schedule. The multiplexer may be used for calibration of a quantum processor by performing a calibration with a large annealing bandwidth, then calibrating the quantum processor by iterating through all available annealing bandwidths from the multiplexer.
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
H01L 39/06 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the current path
81.
Systems and methods for addressing devices in a superconducting circuit
Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
Methods for solving discrete quadratic models are described. The methods compute an energy of each state of each variable based on its interaction with other variables, exponential weights, and normalized probabilities proportional to the exponential weights. The energy of each variable is computed as a function of the magnitude of each variable and a current state of all other variables, exponential weights, the feasible region for each variable, and normalized probabilities, proportional to the exponential weights and respecting constraints. Methods executed via a hybrid computing system obtain two candidate values for each variable; constructs a Hamiltonian that uses a binary value to determine which candidate values each variable should take, then constructs a binary quadratic model based on the Hamiltonian. Samples from the binary quadratic model are obtained via a quantum processor. The methods can be applied to solve resource scheduling optimization problems and/or for side-chain optimization for proteins.
An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
H01L 39/08 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the shape of the element
85.
Systems and methods for collaborative filtering with variational autoencoders
Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
G11C 11/44 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using super-conductive elements, e.g. cryotron
H03K 3/38 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of superconductive devices
H03K 17/92 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of superconductive devices
G11C 8/00 - Arrangements for selecting an address in a digital store
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
Systems, methods and article provide the services of heterogeneous resources, for example the services analog processors, e.g., quantum processors, in a robust manner that can include high availability, failover, and load balancing of the heterogeneous resources. A virtual solver is selected based at least in part on a first set of requirements, a first set of analog processors is identified based at least in part on the first set of requirements, and a first handle returned to the first virtual solver. A load balancer may balance loads. Failure over may be implemented.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
In many cases after degaussing the field distribution in a magnetic material there may be regions within the magnetic material that have ordered domains that contribute a remnant field. There is the need to reduce or eliminate non-uniform fields within a volume of interest left after degaussing a magnetic shield. Degaussing coils surrounding a metal shield can be used to favorably order magnetic domains within the material to counteract the remnant fields left behind following imperfect degaussing. The remnant field value can be measured and a small current may be applied through the degaussing coils. After removing the current, the field can be measured again and a higher current may be applied again through the coils. Repeated applications of currents and field measurement will progressively order domains in the direction of the applied field, resulting in a reduction of the net field and lower field gradient across the volume of interest.
H01F 7/06 - Electromagnets; Actuators including electromagnets
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H03H 3/00 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01F 13/00 - Apparatus or processes for magnetising or demagnetising
H01F 41/076 - Forming taps or terminals while winding, e.g. by wrapping or soldering the wire onto pins, or by directly forming terminals from the wire
H03H 1/00 - Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H01L 39/02 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
A hybrid computer comprising a quantum processor can be operated to perform a scalable comparison of high-entropy samplers. Performing a scalable comparison of high-entropy samplers can include comparing entropy and KL divergence of post-processed samplers. A hybrid computer comprising a quantum processor generates samples for machine learning. The quantum processor is trained by matching data statistics to statistics of the quantum processor. The quantum processor is tuned to match moments of the data.
A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.
A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.
Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton. Also, for example, a quantum processor may be summarized as including a first loop of superconducting material, a first compound Josephson junction interrupting the first loop of superconducting material, a first coupler inductively coupled to the first loop of superconducting material, a second coupler inductively coupled to the first loop of superconducting material, and a second loop of superconducting material proximally placed to the first loop of superconducting material inductively coupled to the first coupler and the second coupler.
A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H01L 39/24 - Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group or of parts thereof
A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
B32B 15/00 - Layered products essentially comprising metal
B32B 38/10 - Removing layers, or parts of layers, mechanically or chemically
C23F 1/44 - Compositions for etching metallic material from a metallic material substrate of different composition
H05K 1/09 - Use of materials for the metallic pattern
96.
INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES
e.g.e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
Calibration techniques for devices of analog processors to remove time-dependent biases are described. Devices in an analog processor exhibit a noise spectrum that spans a wide range of frequencies, characterized by 1/f spectrum. Offset parameters are determined assuming only a given power spectral density. The algorithm determines a model for a measurable quantity of a device in an analog processor associated with a noise process and an offset parameter, determines the form of the spectral density of the noise process, approximates the noise spectrum by a discrete distribution via the digital processor, constructs a probability distribution of the noise process based on the discrete distribution and evaluates the probability distribution to determine optimized parameter settings to enhance computational efficiency.
G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks
G01R 29/26 - Measuring noise figure; Measuring signal-to-noise ratio
G01R 33/24 - Arrangements or instruments for measuring magnetic variables involving magnetic resonance for measuring direction or magnitude of magnetic fields or magnetic flux
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
B82Y 35/00 - Methods or apparatus for measurement or analysis of nanostructures
98.
Systems and methods for calibrating devices using directed acyclic graphs
A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
