A pixel processing circuit, a reading method thereof and an image sensor are provided. The pixel processing circuit includes a pixel array comprising a plurality of pixel units arranged in a Bayer array, an Analog-to-Digital Converter (ADC) module comprising a plurality of analog-to-digital converters and a plurality of switch selection modules. The analog-to-digital converters are respectively located on the opposite first side and second side of the pixel array. The switch selection modules are set between the pixel array and the analog-to-digital converters to switch the connectivity between the pixel units and the analog-to-digital converters on the opposite sides of the pixel array so that signals of green pixel units are read by first analog-to-digital converters located at the first side of the pixel array, and signals of remaining color pixel units are read by second analog-to-digital converters that are located at the second side of the pixel array.
A read circuit for an image sensor includes: a first analog-to-digital conversion unit configured to perform successive approximation high-bit analog-to-digital conversion on collected pixel data to obtain high-bit conversion data and residual pixel data; and a second analog-to-digital conversion unit electrically connected to the first analog-to-digital conversion unit and configured to perform single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data, wherein a sum of a first conversion accuracy of the first analog-to-digital conversion unit and a second conversion accuracy of the second analog-to-digital conversion unit is equal to a preset conversion accuracy for the pixel data. In accordance with the read circuit, a high image conversion frame rate of the pixel data can be achieved with lower power consumption and less circuit area, and the conversion cycle of the pixel data is effectively shortened.
A method and a system for reducing column noise of an image sensor are provided. The method includes: reading dark pixel data in each image frame and reading initial effective pixel data in each image frame, where dark pixels and initial effective pixels are both arranged in N columns; sequentially calculating the dark pixel data to obtain an average value of each column of dark pixels and an entire average value of the dark pixels in each image frame; obtaining a corrected value of each column according to the average value of each column of dark pixels and the entire average value of the dark pixels; and calculating the corrected value of each column and the corresponding initial effective pixel data in each image frame to obtain target effective pixel data. In the method, the dark pixel data is pre-processed.
The present invention disclosures an image sensor structure and a formation method thereof, wherein comprising: a pixel unit array, a peripheral circuit set at the periphery of the pixel unit array, and a composite shield structure around the pixel unit array and between the pixel unit array and the peripheral circuit, the composite shield structure comprises a light shield structure and a heat shield structure; wherein, the light shield structure comprises a metal isolation structure around the pixel unit array for isolating light emitted by the peripheral circuit, and the heat shield structure comprises a cavity set inside the metal isolation structure, the cavity is filled with a thermal isolation medium for preventing heat transfer to the pixel unit array. The present invention can avoid image quality deterioration and distortion caused by light and heat of the peripheral circuit of the image sensor.
Provided in the present invention are an image signal detection circuit, a control method, and a motion detection method. The image signal detection circuit comprises an acquisition module, the acquisition module comprising an acquisition sub-module, the acquisition sub-module comprising a capacitor, for acquiring the difference between consecutive two pixel signals with a reference voltage as the origin. The image signal detection circuit and a motion detection circuit are structurally simple and easy to implement, obviate the need for analog-to-digital conversion, increase the speed of difference detection, and implement motion detection.
SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO. (China)
SHANGHAI IC R&D CENTER CO., LTD. (China)
CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD. (China)
Inventor
Zhou, Yang
Abstract
Provided are a backside illumination image sensor and a preparation method. An isolation ring surrounds a photodiode and a channel region, and penetrates a semiconductor substrate and an epitaxial layer; a source region and a drain region respectively extend from the surface of the channel region into the channel region, and surround a charge accumulation region; and the channel region isolates the source region from the charge accumulation region. An isolation ring of the backside illumination image sensor is compatible with a conventional CMOS process flow, and a photodiode and a source region, which are vertically distributed, are formed in the isolation ring by means of multiple instance of injection, thereby reducing the parasitic capacitance of a charge transport tube, increasing the transmission rate, and improving the image frame rate of an image sensor chip.
Disclosed are a run-length decoding circuit, a control method, an electronic device and a readable storage medium. The run-length decoding circuit comprises a storage unit, a control module, a first storage buffer zone, a second storage buffer zone, and a decoding module; the control module is used to obtain encoded data from the storage unit, and store the encoded data into the first storage buffer zone; the decoding module is used to obtain the encoded data from the first storage buffer zone, decode same to obtain decoded data, and store the decoded data in the second storage buffer zone; and the decoding module is further used to obtain the decoded data from the second storage buffer zone so as to obtain superimposed image information and output same. The superimposed image information obtained according to the present invention is continuous in time sequence, and an OSD function of an image signal is ensured during the process of superimposing the images.
Disclosed are an image sensor structure and a forming method. The image sensor structure comprises: a pixel unit array, a peripheral circuit located on the periphery of the pixel unit array, and a composite shielding structure located between the pixel unit array and the peripheral circuit and arranged around the pixel unit array. The composite shielding structure comprises a light-shielding structure and a heat-shielding structure, wherein the light-shielding structure is provided with a metal isolation structure that surrounds the pixel unit array and is used for isolating light emitted by the peripheral circuit; and the heat-shielding structure comprises a cavity arranged inside the metal isolation structure, and the cavity is filled with a heat isolation medium for preventing heat from being transmitted to the pixel unit array. The present invention can prevent the problems of imaging quality degradation and distortion caused by the light emission and heat generation of a peripheral circuit of an image sensor.
The present invention discloses a motion detection circuit applied to CIS and a motion detection method. Through the current frame pixel signal sampling branch and the previous frame pixel signal sampling branch, the sampling of the current frame and the previous frame pixel signal is respectively controlled, and the previous frame pixel signal is transmitted to the first end of the first capacitor and the second capacitor connected in series, and then the first error reference signal and the second error reference signal related to the pixel signal of the previous frame, which are respectively output by the second ends of the first capacitor and the second capacitor that are not connected, are transmitted to the first comparator branch and the second comparator branch of the comparator branch respectively, by judging the high and low-state of the comparison signals of the current frame pixel signal and the first error reference signal, and the current frame pixel signal and the second error reference signal respectively output by the first comparator branch and the second comparator branch, so as to determine whether an image point reflected by the pixel points of the pixels connected with the motion detection circuit has moved or not.
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
H04N 5/14 - Picture signal circuitry for video frequency region
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Provided is a method for removing fixed pattern noise. The method comprises the following steps: S01, performing single-frame segmented exposure on a pixel array; and S02, performing signal reading on the pixel array. Step S02 specifically comprises: S021, performing a soft reset: setting a reset signal in a pixel unit to be of an intermediate voltage, and reading a differential reset signal; S022, performing a hard reset: setting the reset signal in the pixel unit to be of a high voltage; and S023, turning on a transmission MOS tube to enable an exposure signal in a photodiode to be transmitted to a suspension diffusion region, and reading a differential pixel transmission signal. The method further comprises: S03, subtracting the differential pixel transmission signal from the differential reset signal to obtain an exposure signal from which fixed pattern noise is removed. According to the method for removing fixed pattern noise on the basis of a differential reset, fixed pattern noise that is the same as that of an exposure signal is introduced when a reset signal is read, and the fixed pattern noise in an image is removed through subtraction processing.
H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 5/345 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled by partially reading an SSIS array
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
11.
Image sensor for real time calibration of dark current and calibration method
The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration. The present invention discloses an image sensor for real-time calibration of dark current, which can make the dark current calibration completed directly within the pixel, and can better cover the dark pixel part, so as to make calibration value of dark current and dark noise more accurate.
A MIPI D-PHY circuit comprises a main control module, a controlled module, an internal data source generating module, and a configuration register. The main control module and the controlled module are respectively connected to the configuration register, and the main control module is connected to the internal data source generating module. The main control module and the controlled module comprise a clock channel and a data channel respectively. The clock channel and the data channel in the main control module and the data channel and the clock channel in the controlled module both comprise an error detection unit. The MIPI D-PHY circuit provided by the present disclosure adopts the error detection unit to detect the signals of the main control module and the controlled module.
Disclosed in the present invention are a stacked image sensor pixel structure and a preparation method. A first silicon wafer, a second silicon wafer, and a third silicon wafer are stacked up and down in a bonding manner. A first photosensitive diode array is provided on the first silicon wafer at the middle layer, and a second photosensitive diode array is provided on the second silicon wafer at the upper layer; and the surfaces of the second photosensitive diodes in the second photosensitive diode array are aligned and bonded with the surfaces of the corresponding first photosensitive diodes in the first photosensitive diode array, so that the formed stacked image sensor chip has a very deep junction depth and is particularly suitable for near-infrared light sensing, being able to effectively improve the quantum efficiency in near-infrared wavelength bands. Furthermore, a back-lighting process can be used to enable incident light irradiated onto the photosensitive diodes not to be affected by metal interconnection, so that the sensitivity is high, the filling factor is high, and the photosensitive property is very good, especially for small-size image elements, thereby taking into account both the near-infrared quantum efficiency and the small pixel size.
A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip. It not only brings convenience to the subsequent packaging and application, but also reduces the size of circuit such as the PGA and the ADC on one side of the pixel array, and overcomes the problem that the capacity of circuit such as the PGA and the ADC cannot be increased when the height of the circuits such as the PGA and the ADC cannot exceed the height of the pixel array.
The present disclosure provides a FINFET device integrated with a TFET and its manufacturing method. Two end portions of the fin structure respectively form an N-type doped drain and a source which is consisted by a top P-type doped region and a bottom N-type doped region. As a result, the bottom N-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the surface of the sidewall of the fin structure form a MOS FINFET device, and the top P-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the top surface of the fin structure form the TFET device. The integration of the TFET and the FINFET is achieved, which decreases the cost.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.
The present disclosure refers to a multispectral image sensor and a manufacturing method thereof. The multispectral image sensor comprises a front-end structure used for photoelectric conversion and processing, and a pixel layer provided on the front-end structure. The pixel layer comprises N pixel units, and N≥4, the pixel units are arranged in a plurality of arrays, a photosensitive wavelength of each pixel unit in each array is different. Whereby, multispectrals can be detected simultaneously, and therefore the efficiency is improved, costs are reduced, and miniaturization is achieved.
Disclosed in the present invention is an image sensor for real-time calibration of dark current, comprising a pixel array consisting of at least one pixel unit. The pixel unit comprises a pixel photosensitive portion, a pixel light-shielding portion, and a subtraction circuit. The phototubes in the pixel photosensitive portion and pixel light-shielding portion are isolated by deep isolation trenches. A light-shielding layer covers the surface of the pixel light-shielding portion. Both the pixel photosensitive portion and the pixel light-shielding portion are controlled by using the same voltage and timing. Generated light ambient voltage signal and light-free ambient voltage signal are input to both ends of the subtraction circuit, so as to implement the subtraction and dark current calibration between the light ambient voltage signal and the light-free ambient voltage signal. The present image sensor for real-time calibration of dark current enables dark current calibration to be completed directly in pixels, and can better shield a dark pixel portion, so that dark current and dark noise calibration values are more accurate.
Disclosed are a motion detection circuit and a motion detection method applied to a CIS. The method comprises: a current frame pixel signal sampling shunt circuit and a previous frame pixel signal sampling shunt circuit respectively controlling the sampling of a current frame pixel signal and a previous frame pixel signal; first transmitting the previous frame pixel signal to first ends, connected to each other, of a first capacitor and a second capacitor connected in series and then respectively transmitting a first error reference signal and a second error reference signal, that are respectively output from second ends, not connected to each other, of the first capacitor and the second capacitor and are related to the previous frame pixel signal, to a first comparator branch and a second comparator branch of a comparator shunt circuit; and determining the level states of comparison result signals, that are respectively output by the first comparator branch and the second comparator branch, for the current frame pixel signal and the first error reference signal and for the current frame pixel signal and the second error reference signal, such that an image point reflected by a pixel point of a pixel connected to a motion detection circuit moves can be determined.
A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate. Compared with the existing polyline mode, the present disclosure has better linearity; and it can be easily extended to cascade multistage integrators.
A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Disclosed in the present invention is a D-PHY circuit for a mobile industry processor interface (MIPI), comprising a master control module, a controlled module, an internal data source generation module and a configuration register, wherein the master control module and the controlled module are connected to a configuration register respectively; the master control module is connected to the internal data source generation module; the master control module and the controlled module each comprise a clock channel and a data channel; and the clock channels and the data channels in the master control module and the controlled module each comprise an error detection unit. According to the D-PHY circuit for the MIPI interface provided in the present invention, an error detection circuit is used to perform error detection on signals of the master control module and the controlled module, and high-speed serial-parallel and parallel-serial conversion is implemented by using a digital circuit, thereby reducing the area of the D-PHY circuit, and reducing the circuit complexity.
A multispectral image sensor and a method for manufacturing same. The multispectral image sensor comprises a front-end structure (10) used for photoelectric conversion and processing; and a pixel layer (20) provided on the front-end structure. The pixel layer comprises N pixel units (13), and N is greater than or equal to 4; the pixel units are arranged into multiple arrays (21); a photosensitive wavelength of each pixel unit in each array is different. Whereby, multiple spectrums can be detected simultaneously, and therefore, the efficiency is improved, costs are reduced, and miniaturization is achieved.
A method resolving brightness inconsistency between channels comprises the following steps: providing two images, and configuring, at the seam between the two images, a width range, wherein the seam is covered by the configured width range (01); computing the brightness of each column of pixels in the configured width range (02); employing coordinates of each column of pixels in the configured width range as horizontal and vertical coordinates to obtain a pixel set (03); according to an optimal solution of a RANSAC algorithm, fit the pixel set into a straight line, to obtain an optimal solution model of the pixel set (04); and determining, in the optimal solution model, fitted values of all pixels on one side of the seam, and adjusting, according to the fitted values, the brightness of pixels at corresponding locations on the other side of the seam (05). The method can be utilized to automatically compensate for brightness inconsistency between channels, optimizing the resulting image.
The invention discloses a full-frame image sensor system comprising read circuits, channel selection circuits, and interface circuits arranged symmetrically with respect to a pixel array. A pair of the read circuits are electrically connected to two sides of the pixel array, respectively. The channel selection circuit and the read circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, and the center of the pixel array is aligned with that of the entire chip, facilitating subsequent packaging and applications, reducing sizes of circuits such as PGAs and ADCs located at either side of the pixel array, and overcoming an issue in which the heights of circuits such as PGAs and ADCs cannot exceed the height of a pixel array, resulting in limited capacities of the circuits such as PGAs and ADCs in the prior art.
A device structure for reducing parasitic resistance of a FinFET, and a manufacturing method therefor. The method comprises: manufacturing a conventional FinFET device structure, comprising the sub-steps of manufacturing a FinFET silicon fin structure and a gate stack structure which consists of a gate electrode and a gate dielectric layer, and defining source and drain areas of the FinFET device, the gate stack structure that consists of the metal gate electrode and the gate dielectric layer and is comprised in the conventional FinFET device structure wraps the FinFET silicon fin structure from the sides and the surface so as to form a three-dimensional channel of an MOSFET; preparing a catalyst layer in the source and drain areas; growing a carbon nanotube to form a strip-shaped contact hole layer MO, the lower end of the strip-shaped contact hole layer MO covering and being connected to the source and drain areas of the FinFET device, and the carbon nanotube comprising a single-wall carbon nanotube material and a multiwall carbon nanotube material; and leading out the source and drain of the FinFET device, and implementing a back-end-of-line process, i.e., connecting the upper end of the strip-shaped contact hole layer MO to a metal layer M1.
Provided in the present invention are a global shutter CMOS pixel unit and an image collection method, the pixel unit comprising: a power source, a pixel generation unit, a signal sampling and holding unit and a signal output unit, the output terminal of the pixel generation unit being connected to the input terminal of the signal sampling and holding unit, the output terminal of the signal sampling and holding unit being connected to the input terminal of the signal output unit. By setting the logarithmic relationship between pixel output voltage and photo-induced current, the invention effectively improves the dynamic range of a signal output, and improves the dynamic range of image output signals in the case of high-speed reading; moreover, the pixel unit of the invention has the characteristic of eliminating process variations, effectively improving the consistency of image signals outputted by the pixel unit.
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
28.
SYSTEM AND METHOD FOR REGULATING TRANSFER CHARACTERISTICS OF INTEGRAL DIGITAL-TO-ANALOG CONVERTER
Disclosed are a system and method for regulating transfer characteristics of an integral analog-to-digital converter (ADC). The system is provided with a cascaded N-level integrator structure constituted by N integrators, an output end of each integrator is connected to an input end of the integrator adjacent thereto, the input end of the first integrator is connected to an input voltage, the output end of the N-th integrator is connected to an output node (VRAMP), where N is a positive integer greater than or equal to 2; and in the cascaded N-level integrators, changes in the voltage of the output node (VRAMP) are directly proportional to the N-th power of time. The present invention utilizes cascaded multilevel integrators of a simple implementation scheme, facilitates subsequent digital signal processing, reduces the conversion time of the ADC, and increases the conversion rate of the ADC; compared with an existing polyline approach, the present invention is of an improved linearity and is easy to expand to cascaded multilevel integrators.
A TFET-integrated FINFET device and a preparation method therefor. An N type drain region (01) and a source region (02) which is formed by a top P type doped region (021) and a bottom N type doped region (022) are formed on two end regions of a fin structure (Q), respectively, so that the bottom N type doped region (022) on the source region (02), the drain region (01), a channel region (05), a high-K dielectric layer (03) on the side wall of the fin structure (Q), and a gate (04) positioned on the side wall of the fin structure (Q) jointly form an MOS FINFET device; and the top P type doped region (021) on the source region (02), the drain region (01), the channel region (05), the high-K dielectric layer (03) on the top of the fin structure (Q), and the gate (04) positioned on the top of the fin structure (Q) jointly form a TFET device. Integration of a TFET and a FINFET is realized, so that the costs are lowered.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A method and system for testing optimization for a semiconductor component and for molding optimization. The method and system for testing optimization: constructing, on the basis of a testing structure for testing a specific non-direct current parameter, an auxiliary structure for the testing structure and testing the non-direct current parameter, calculating a parasitic parallel resistance and a parasitic series resistance of the testing structure on the basis of a parasitic network model of the auxiliary structure and of the testing result (S1); performing a linear fitting to acquire a direct current parasitic resistance of the testing structure (S2); executing a direct current testing with respect to the testing structure to acquire direct current test data, and correcting the direct current test data on the basis of a direct current equivalent sub-circuit model (S3). The method and system directly use the testing structure for the non-direct current parameter and eliminate the impact that parasitic elements of the testing structure have on the direct current test data, thus allowing a semiconductor component expressed by the direct current test data and that by test data of the non-direct current parameter to converge, increasing the accuracy in estimating semiconductor component features, and also providing reliable data for molding.
A median filter device is provided with a reordered circuit, a comparison circuit and a data refresh circuit on the basis of the conventional data buffer circuit and data register circuit. The reorder circuit re-sorts the signal data stored in the data buffer circuit in a preceding clock cycle according to their numerical values. The comparison circuit compares the new signal datum entered in the current clock cycle with the signal data already stored to generate a median. The data refresh circuit updates the signal codes stored in the data register circuit with the signal codes corresponding to the new signal data, for calculation of the median in a following clock cycle. The length of the data buffer circuit and data register circuit can be reduced from N signal data to N−1 signal data, which achieves less data storage capacity, smaller circuit area, easier data processing and higher operation efficiency.
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
32.
Test structure and method for judging de-embedding accuracy of RF devices by using an introduced device
The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.
patents
