Disclosed in the present invention is a semiconductor device. The semiconductor device comprises an epitaxial structure, a first dielectric layer, a gate, an air-gate field plate, and a second dielectric layer, wherein the first dielectric layer covers the epitaxial structure; the gate is arranged on the side of the epitaxial structure where the first dielectric layer is provided; the air-gate field plate is arranged on the side of the gate away from the epitaxial structure, and makes contact with the gate; the second dielectric layer covers all the surfaces of the first dielectric layer, the gate and the air-gate field plate facing away from the epitaxial structure; and the thickness of the portion of the gate exposed by the first dielectric layer is greater than twice the thickness of the portion of the second dielectric layer covering the first dielectric layer and overlapping with a gate field plate, and/or greater than twice the thickness of the portion of the second dielectric layer located on the surface of the air-gate field plate close to the epitaxial structure. The present invention can reduce the parasitic capacitance of the semiconductor device and prolong the service life of the semiconductor device.
A semiconductor device, comprising: a substrate; an epitaxial structure, located on one side of the substrate, and a two-dimensional electron gas being provided in the epitaxial structure; an electrode structure, located on the side of the epitaxial structure away from the substrate, part of the electrode structure being located in a first active area, and the other part of the electrode structure being located in a passive area; and at least one odd mode resistor, located outside the first active area and electrically connected to the electrode structure, wherein each odd mode resistor among the at least one odd mode resistor comprises a first resistor electrode and a second resistor electrode, and at least part of the first resistor electrode and at least part of the second resistor electrode are both located in a second active area; and in a same odd mode resistor, the first resistor electrode and the second resistor electrode are both in ohmic contact with the two-dimensional electron gas of the second active area, and a two-dimensional electron gas conductive channel exists between the first resistor electrode and the second resistor electrode along the arrangement direction of the first resistor electrode and the second resistor electrode. A first odd mode resistor is provided to suppress odd mode oscillation, thereby improving the stability of the semiconductor device.
A gate structure includes a gate portion and a field plate portion, a projection of a tail end point on a lower surface of the lower field plate sub-portion is located on a side, close to the first plane, of a projection of a start end point on a lower surface of an upper field plate sub-portion, and the start end point on the lower surface of the upper field plate sub-portion is coincidence with an end point where an upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. In the gate structure of the present disclosure, the two adjacent field plate sub-portions are non-perpendicularly connected to each other, thereby achieving an effect of optimizing electric field distribution, thus improving reliability and stability of semiconductor devices.
Embodiments of the present disclosure disclose a semiconductor device including a plurality of sources, a plurality of gates, and a plurality of drains located in an active area. In the active area, the sources, the gates, and the drains are alternately arranged along a first direction, and along the first direction, the sources include two sources respectively closest to ends of the arrangement, and any one of the gates is located between one of the sources and one of the drains, a length of at least a source located at the center along the first direction is greater than lengths of sources located at both ends along the first direction. The semiconductor device further includes a plurality of rows of through holes extending through a substrate and a multilayer semiconductor layer, a plurality of rows of the through holes are arranged along the first direction, and an orthographic projection.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/82 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components
5.
EPITAXIAL STRUCTURE OF SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
The disclosure discloses an epitaxial structure of a semiconductor device, as well as a manufacturing method thereof, and a semiconductor device. Therein, the epitaxial structure includes a substrate and an epitaxial layer located on one side of the substrate, and a surface roughness of one side the substrate close to the epitaxial layer is Ra, wherein 0
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
6.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Embodiments of the present disclosure disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a multi-layer semiconductor layer located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, for forming an electric field or a zero electric field of the active region pointing toward the passive region.
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
7.
COMPOSITE PASSIVE COMPONENT AND PREPARATION METHOD THEREFOR
A composite passive component includes: a substrate, an epitaxial structure and a passive component body. The epitaxial structure is set on the substrate, and a two-dimensional electron gas with a specific pattern is formed in the epitaxial structure. The passive component body is in ohmic contact with the two-dimensional electron gas.
An epitaxial structure of a semiconductor device includes a substrate, a nucleation layer and a buffer layer. The nucleation layer is located at a side of the substrate, the nucleation layer includes a plurality of nucleation units, surfaces, close to the substrate, of the plurality of nucleation units are communicated with each other, and surfaces, away from the substrate, of the plurality of nucleation units are separated from each other; and the buffer layer is located at a side, away from the substrate, of the nucleation layer, the buffer layer includes a 3D buffer layer, and the 3D buffer layer is formed on a surface, away from the substrate, of the nucleation layer. In the technical solutions of the present disclosure, quality of an epitaxial structure may be improved, ensuring quality of a semiconductor device.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
9.
SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR
Disclosed in the embodiments of the present invention are a semiconductor device and a preparation method therefor. The semiconductor device comprises: a substrate; an epitaxial structure, which is located on one side of the substrate; and a plurality of gates, which are located on the side of the epitaxial structure that is away from the substrate, wherein the gates extend in a first direction, and the plurality of gates are arranged in a second direction; the first direction and the second direction intersect with each other, and are both parallel to the plane where the substrate is located; the plurality of gates include a first gate and a second gate, and in the second direction, the first gate is located on the side of the second gate that is close to an edge of the semiconductor device; and the highest temperature of the first gate is T1, and the highest temperature of the second gate is T2, where (T2-T1)/T1≤20%. By using the technical solution, the temperature of a semiconductor device can be uniformly distributed, degradation of the radio frequency performance of the device can be reduced, and the output power can be increased.
Disclosed in the present application is a semiconductor device. The semiconductor device comprises: a substrate; an epitaxial structure, which is located on one side of the substrate; a gate, which is located on the side of the epitaxial structure that is away from the substrate, wherein the gate extends in a first direction, the first direction is parallel to the plane where the substrate is located, and the gate is in Schottky contact with the epitaxial structure; and a gate connecting structure, which comprises a first gate connecting part and a second gate connecting part that are connected to each other, wherein the second gate connecting part is electrically connected to at least part of the gate. In the semiconductor device, by providing a gate connecting structure, the effect of the resistance of a gate can be reduced, thereby increasing a switching speed and increasing the gain.
Disclosed in the present application is a preparation method for a semiconductor device. The preparation method comprises: providing a substrate; preparing an epitaxial structure on one side of the substrate; and preparing a gate and a gate connecting structure on the side of the epitaxial structure that is away from the substrate, wherein the gate connecting structure is electrically connected to at least part of the gate. In the present application, the gate connecting structure is prepared and is electrically connected to at least part of the gate, such that the effect of the resistance of the gate can be reduced, the gain can be improved, and electric leakage is reduced.
Provided in the embodiments of the present invention are a semiconductor device and a preparation method therefor. The semiconductor device comprises a field-plate main body portion, and at least one field-plate tail end portion which extends into a passive area. The extension width of a first field-plate tail end portion and/or a second field-plate tail end portion of a field plate that are at least located in a passive area are set to be greater than the extension width of the field-plate main body portion, thereby facilitating an improvement in the reliability and stability of the field plate; in addition, a certain distance is set to be reserved between the active area and a first boundary line position of the first field-plate tail end portion and/or the field-plate tail end portion, such that capacitive problems between gate and source electrodes are reduced while the distribution of an electric field near a gate electrode at the boundary of the active area is adjusted; and the difference between the extension width of the field-plate tail end portion and the extension width of the field-plate main body portion is set to satisfy a certain relationship to reduce the stress between structures, thereby improving the reliability and stability of a chip.
A semiconductor device includes an active region; a substrate; an epitaxial structure; an electrode structure, and the electrode structure including a plurality of ohmic contact electrodes; a first dielectric layer; an electrode connection line, the electrode connection line including an ohmic contact electrode connection line, and the ohmic contact electrode connection line being electrically connected to the ohmic contact electrode; an second dielectric layer; an electrode bonding pad, the electrode bonding pad including an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line, and at least a part of the ohmic contact electrode bonding pad being located in the active region, reducing a parasitic capacitance between the ohmic contact electrode bonding pad and the substrate, and further satisfying high requirements on an input capacitance and an output capacitance of the semiconductor device.
Embodiments of the present invention relate to an epitaxial structure of a semiconductor device and a manufacturing method thereof, and a semiconductor device. The epitaxial structure of the semiconductor device comprises: a substrate; and an epitaxial layer located on one side of the substrate, the epitaxial layer comprising at least a first sub-epitaxial layer group, the first sub-epitaxial layer group comprising a first sub-epitaxial layer and a second sub-epitaxial layer arranged in stack; wherein, a surface of one side of the first sub-epitaxial layer away from the substrate comprises a plurality of first dislocation pits, and sidewalls of the first dislocation pits intersect both a plane where the first sub-epitaxial layer is located and a first direction; and the second sub-epitaxial layer covers at least the sidewalls of the first dislocation pits. In the embodiments of the present invention, most of the dislocations in the second sub-epitaxial layer that originally extended upward along the first direction will change their extension direction at the first dislocation pit, and the dislocations bend, thereby reducing most of the dislocations extending upward along the first direction, improving the uniformity of the epitaxial layer, improving crystal quality and product yield, and reducing costs.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
15.
GATE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE
Disclosed in the present application are a gate structure, a semiconductor device, and a method for preparing a semiconductor device. The gate structure comprises a gate portion and a field plate portion, wherein the field plate portion comprises at least two field plate sub-portions; in a direction from the gate portion to the field plate portion, the gate portion and the field plate portion are each divided into two parts by a first plane; and in the two adjacent field plate sub-portions, on a plane where the bottom face of the gate portion away from a lower field plate sub-portion is located, the projection of a tail end point of a lower surface of the lower field plate sub-portion is located on the side of the projection of a start end point of a lower surface of an upper field plate sub-portion that is close to the first plane, and the start end point of the lower surface of the upper field plate sub-portion coincides with an end point where an upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. In the gate structure of the present application, two adjacent field plate sub-portions are non-perpendicularly connected to each other, thereby achieving the effect of optimizing electric field distribution, and thus improving the reliability and stability of a semiconductor device.
Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a source, a gate and a drain located on one side of a substrate, the gate being located between the source and the drain, the gate includes a first end portion and an intermediate portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion being located in the passive region, the first end portion includes a first sub end portion and a second sub end portion. In a first direction, an extension width of the first sub end portion is greater than that of the intermediate portion, and an extension width of the second sub end portion is greater than that of the first sub end portion.
The present disclosure relates to an epitaxial structure of a semiconductor device, a device, and a method of manufacturing the epitaxial structure. The epitaxial structure includes a substrate, and a first semiconductor layer, located on the substrate, the first semiconductor layer including buffer layers, the buffer layers at least including a first buffer layer, a second buffer layer, and a third buffer layer which are arranged in layers, and the second buffer layer being located between the first buffer layer and the third buffer layer, wherein the second buffer layer is doped with iron impurities, and the first buffer layer and the third buffer layer are not actively doped with iron impurities, and concentration of iron impurities of the second buffer layer satisfies a first preset range.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C30B 25/18 - Epitaxial-layer growth characterised by the substrate
Disclosed in embodiments of the present invention is a semiconductor device, comprising multiple sources, multiple gates, and multiple drains located in an active area. In the active area, the sources, the gates, and the drains are arranged alternately in a first direction; two sources respectively closest to arrangement ends are comprised in the first direction; each gate is located between a source and a drain; at least the length of the source located at the center in the first direction is greater than the length of the sources located at two ends in the first direction; the semiconductor device further comprises multiple rows of through holes penetrating through a substrate and multiple semiconductor layers; the multiple rows of through holes are arranged in the first direction; an orthographic projection of the source on the substrate overlaps orthographic projections of the through holes on the substrate; and in the first direction, at least the number of rows of through holes corresponding to the source located at the center is twice the number of rows of through holes corresponding to the sources located at two ends. The technical solution of the embodiments of the present invention can ensure the radio frequency characteristics of the semiconductor device while enhancing the heat dissipation capability of the central area of the semiconductor device.
Provided in the present disclosure is a composite passive component. The composite passive component comprises: a substrate, an epitaxial structure and a passive component body, wherein the epitaxial structure is arranged on the substrate, and a two-dimensional electron gas having a specific pattern is formed on the epitaxial structure; and the passive component body is in ohmic contact with the two-dimensional electron gas. The composite passive component comprises a metal capacitor structure, wherein the metal capacitor structure comprises a first metal polar plate and a second metal polar plate, the second metal polar plate is located on the side of the first metal polar plate that is away from the substrate, and the first metal polar plate is insulated from the two-dimensional electron gas. The passive component body comprises an inductor structure. The inductor structure comprises: a first connecting metal layer, which is in ohmic contact with a first end of the two-dimensional electron gas; an inductor metal line, which is arranged on the side of the epitaxial structure that is away from the substrate, wherein the inductor metal line is in a second planar spiral shape; and a first connecting metal, wherein a first end of the first connecting metal is electrically connected to the first connecting metal layer, and a second end of the first connecting metal is electrically connected to a first end of the inductor metal line.
H10K 10/00 - Organic devices specially adapted for rectifying, amplifying, oscillating or switchingOrganic capacitors or resistors having potential barriers
20.
EPITAXIAL STRUCTURE OF SEMICONDUCTOR DEVICE, PREPARATION METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
Embodiments of the present invention discloses an epitaxial structure of a semiconductor device, a preparation method therefor, and a semiconductor device. The epitaxial structure comprises a substrate, a nucleation layer and a buffer layer. The nucleation layer is located on one side of the substrate. The nucleation layer comprises a plurality of island-like nucleation units. The surfaces of the nucleation units on the sides close to the substrate are communicated with each other, and the surfaces of the nucleation units on the sides away from the substrate are separated from each other. The buffer layer is located on the side of the nucleation layer away from the substrate. The buffer layer comprises a 3D buffer layer, and the 3D buffer layer is formed on the surface of the side of the nucleation layer away from the substrate. By means of the technical solution of the embodiments of the present invention, the quality of the epitaxial structure is improved, and thus the quality of the semiconductor device is ensured.
Disclosed in the present invention are an epitaxial structure of a semiconductor device, a preparation method for an epitaxial structure, and a semiconductor device. The epitaxial structure comprises a substrate and an epitaxial layer, which is located on one side of the substrate, wherein the surface roughness of the side of the substrate that is close to the epitaxial layer is Ra, and 0 < Ra ≤ 5 nm. According to the epitaxial structure of a semiconductor device, the preparation method for an epitaxial structure, and the semiconductor device provided in the present invention, by setting the surface roughness Ra of an epitaxial growth side of a substrate to satisfy 0 < Ra ≤ 5 nm, direct epitaxial growth of a high-quality epitaxial layer on the substrate is realized, such that there is no need to provide a relatively thick buffer layer, and the thermal resistance is thus reduced, thereby improving the working performance of the semiconductor device.
Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a substrate, a multilayer semiconductor layer, and a source, a gate and a drain, the gate being located between the source and the drain, wherein, in a first direction, the gate includes, in turn, a first end portion, an intermediate portion and a second end portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion and/or the second end portion extending into the passive region, and in a second direction, an extension width of a portion at least located in the passive region of the first end portion and/or the second end portion is greater than an extension width of the intermediate portion.
Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Embodiments of the present application disclose a semiconductor device and a manufacturing method therefor. The semiconductor device comprises an active region, and further comprises: a substrate; an epitaxial structure; an electrode structure which comprises multiple ohmic contact electrodes; a first dielectric layer; an electrode connection line which is arranged on the side of the first dielectric layer away from the substrate and comprises an ohmic contact electrode connection line, the ohmic contact electrode connection line being electrically connected to the ohmic contact electrode; a second dielectric layer; and an electrode bonding pad which is arranged on the side of the second dielectric layer away from the substrate and comprises an ohmic contact electrode bonding pad. The ohmic contact electrode bonding pad is electrically connected to the ohmic contact electrode connection line, and at least a part of the ohmic contact electrode bonding pad is located in the active area. According to the semiconductor device provided in the present application, at least a part of the ohmic contact electrode bonding pad is arranged in the active region to reduce the parasitic capacitance generated between the ohmic contact electrode bonding pad and the substrate, thereby meeting the high requirements on input and output capacitors of the semiconductor device.
Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate; a multilayer semiconductor layer located on a side of the substrate; and a source, a gate, a drain and a field plate structure located on a side, away from the substrate, of the multilayer semiconductor layer. The field plate structure includes a main body portion and a first extension portion; the main body portion is located between the gate and the drain; the first extension portion is connected to the main body portion and is located on a side, away from the multilayer semiconductor layer, of the gate; and the first extension portion at least partially overlaps the gate. By adopting the above technical solution, the probability of the breakdown, which occurs at the side of the gate near the drain, may be reduced, thereby increasing the reliability of semiconductor devices.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Disclosed in embodiments of the present invention are an epitaxial structure of a semiconductor device, a preparation method therefor, and a semiconductor device. The epitaxial structure of the semiconductor device comprises: a base substrate; an epitaxial layer located at one side of the base substrate, the epitaxial layer at least comprising a first sub-epitaxial layer group, and the first sub-epitaxial layer group comprising a first sub-epitaxial layer and a second sub-epitaxial layer in a layered arrangement; a surface of one side of the first sub-epitaxial layer away from the base substrate comprises a plurality of first dislocation pits, side walls of the first dislocation pits intersecting both a plane where the first sub-epitaxial layer is located and a first direction; and the second sub-epitaxial layer at least covers the side walls of the first dislocation pits. In an embodiment of the present invention, a large portion of dislocations in the second sub-epitaxial layer originally extending along the first direction change a direction of extension at first dislocation pits, and dislocations are bent, and thus a large portion of dislocations extending along the first direction are reduced, the uniformity of an epitaxial layer is improved, crystal quality and product yield are improved, and costs are reduced.
An embodiment of the present disclosure provides a new integrated package electronic device structure, including a packaging component, including a packaging frame and a packaging substrate, and at least two circuit modules, being packaged on one side of the packaging substrate within the packaging frame, wherein the packaging frame including a merge point for the at least two circuit modules. In the present disclosure, by setting the merge points of at least two circuits packaged within the packaging frame on the packaging frame, the problem of occupying a large area when the integrated electronic device is applied due to setting the merge points on the packaging substrate is avoided, the utilization rate of the integrated electronic device is improved, and the integration and industrialization of the electronic device is facilitated.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
29.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The embodiments of the present invention disclose a semiconductor device and a manufacturing method therefor. A semiconductor device comprises an active region and a passive region; the semiconductor device further comprises: a source electrode, a gate electrode and a drain electrode which are located on one side of a substrate, the gate electrode being located between the source electrode and the drain electrode; the gate electrode comprises a first end portion and a middle portion, the middle portion, the source electrode and the drain electrode all being located in the active region, and the first end portion being located in the passive region; the first end portion comprises a first sub-end portion and a second sub-end portion; in a first direction, the extending width of the first sub-end portion is greater than the extending width of the middle portion, and the extending width of the second sub-end portion is greater than the extending width of the first sub-end portion; and the first direction is parallel to a direction of the source electrode pointing to the drain electrode. By increasing the extending width of an end portion of a gate electrode, a contact area between a metal of the end portion of the gate electrode and a substrate is increased, thereby improving the device packaging efficiency, ensuring the stability of the structure and the performance of the gate electrode, further improving the operating stability and reliability of a semiconductor device.
Disclosed in embodiments of the present invention are an epitaxial structure of a semiconductor device, a preparation method, and a semiconductor device. The epitaxial structure comprises a substrate and a semiconductor layer located on one side of the substrate; the semiconductor layer at least comprises a buffer layer on one side of the substrate; along a direction from a preset source area to a preset drain area, the buffer layer comprises a first buffer portion and a second buffer portion which are connected to each other; the vertical projection of the first buffer portion on the substrate overlaps with the vertical projection of the preset source area on the substrate; the vertical projection of the second buffer portion on the substrate overlaps with the vertical projection of a preset gate area and the preset drain area on the substrate. Ions are implanted into the buffer layer, and the ion implantation concentration in the second buffer portion is greater than or equal to the ion implantation concentration in the first buffer portion. A semiconductor device applying the epitaxial structure has a high breakdown voltage, low leakage and high electrostatic protection capability.
Disclosed are a semiconductor device and a preparation method therefor. The semiconductor device comprises an active area and a non-active area surrounding the active area. The semiconductor device further comprises: a substrate; a plurality of semiconductor layers located on one side of the substrate; and at least one shielding structure located on one side of the substrate, wherein the shielding structure is electrically connected to a preset potential, and is used for forming an electric field or a zero electric field, which points to the non-active area, of the active area. By means of the technical solution of the embodiments of the present invention, a shielding structure is provided, and the shielding structure is electrically connected to a preset potential, such that an electric field or a zero electric field, which points to a non-active area, of an active area can be formed, thereby effectively blocking silver ions and inhibiting same from migrating to the front center area of a semiconductor chip, so as to obtain a semiconductor device having the stable performance.
H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
32.
EPITAXIAL STRUCTURE OF SEMICONDUCTOR DEVICE, DEVICE, AND PREPARATION METHOD FOR EPITAXIAL STRUCTURE
The present disclosure relates to an epitaxial structure of a semiconductor device, a device, and a preparation method for an epitaxial structure. The epitaxial structure comprises: a substrate; and a first semiconductor layer located on the substrate, wherein the first semiconductor layer comprises a buffer layer, the buffer layer at least comprising a first buffer layer, a second buffer layer and a third buffer layer, which are arranged in a stacked manner, with the second buffer layer being located between the first buffer layer and the third buffer layer; and the second buffer layer is doped with iron impurities, the first buffer layer and the third buffer layer are not actively doped with the iron impurities, and the concentration of the iron impurities in the second buffer layer satisfies a first preset range. By means of the above-mentioned epitaxial structure, both the quality of crystal and the subthreshold characteristic of a device can be taken into consideration while a high-resistance buffer layer is realized.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, a multilayer semiconductor layer, a dielectric layer, a source and a drain. A gate trench is formed in the multilayer semiconductor layer and the dielectric layer. A gate is formed in the gate trench, and the gate trench includes a first sub-portion of the gate trench formed in the multilayer semiconductor layer and a second sub-portion of the gate trench penetrating the dielectric layer. The second sub-portion of the gate trench includes a second opening located on the surface of the dielectric layer close to the substrate and a third opening on the surface of the dielectric layer away from the substrate. The vertical projection of the third opening on the substrate covers the vertical projection of the second opening on the substrate.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
The embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a preparation method therefor. The epitaxial structure comprises a substrate; and an epitaxial layer located at one side of the substrate, the epitaxial layer comprising a nucleating layer located at one side of the substrate and a buffer layer located at the side of the nucleating layer away from the substrate, wherein the thickness of the buffer layer is inversely proportional to the thickness of the nucleating layer. By using the technical solution, the thickness of an nucleating layer is set to be inversely proportional to the thickness of a buffer layer, improving the crystal quality of the nucleating layer while ensuring that the thermal resistance of the nucleating layer in an epitaxial structure is not high, so as to improve the quality of the epitaxial structure and the quality of a semiconductor device.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
The present application provides an electrode manufacturing method, an electrode, and a semiconductor device, pertaining to the technical field of semiconductor manufacturing. The method comprises: forming an etch layer on a surface of a semiconductor layer, and forming an etch pattern on the etch layer, the etch pattern comprising a first aperture located at a surface of the etch layer away from a semiconductor side and communicated with a surface of the semiconductor layer; etching the surface of the semiconductor layer via the first aperture, so as to form a depression on the surface of the semiconductor layer; etching the corresponding first aperture above the depression, and etching two opposite edges of the first aperture in a width direction thereof, so as to increase the width of the first aperture; and filling, via a second aperture, the depression with a metal material until the metal material completely covers the depression. In this way, the invention enables the depression to be completely covered by the metal material in the width direction, and the metal material provides corrosion resistance to electrodes, thereby improving electrical properties.
A semiconductor device (20) and a preparation method therefor. The semiconductor device (20) comprises an active region (aa) and an inactive region (bb). The semiconductor device (20) further comprises a substrate (21), a multilayer semiconductor layer (22), a source (23), a gate (24) and a drain (25), the gate (24) positioned between the source (23) and the drain (25). The gate (24) comprises, sequentially along a first direction, a first end (241), an intermediate part (242) and a second end (243), wherein the first direction is parallel to the extending direction of the source (23), the gate (24) and the drain (25), the intermediate part (242), the source (23) and the drain (25) are all positioned in the active region (aa), and the first end (241) and/or second end (243) extend into the inactive region (bb). Along a second direction, the extension width of at least the parts of the first end (241) and/or the second end (243) positioned in the inactive region (bb) is larger than the extension width of the intermediate part (242), wherein the second direction is parallel to the direction in which the source (23) points to the drain (25). By means of setting large extension widths of at least the portions of the first end (241) and/or the second end (243) positioned in the inactive region, the distortion of the gate (24) between the corners of the source and the drain due to light diffraction is reduced or eliminated, the structural stability of the gate (24) is ensured, the effects of gate (24) deformation on the power and frequency of the semiconductor device are avoided, and the stable performance of the semiconductor device (20) is ensured.
Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.
The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.
An integrated package electronic device structure, comprising: packaging components that comprise a packaging frame (1) and a packaging substrate (2); and at least two circuit modules that are packaged on one side of the package substrate (2) in the package frame (1), the packaging frame (1) comprising a junction point of the at least two circuit modules, so that the problem of large-area occupation by the integrated electronic device in application caused by providing the junction point on the packaging substrate (2), thereby improving the utilization rate of the integrated electronic device and facilitating the integration and industrialization of electronic devices.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A semiconductor device and a preparation method therefor. The semiconductor device comprises a substrate (10), a multilayer semiconductor layer (20), a dielectric layer (40), a source electrode (51) and a drain electrode (53), wherein a gate trench is formed in the multilayer semiconductor layer (20) and the dielectric layer (40); a gate (52) is formed in the gate trench; the gate trench comprises a first gate trench branch (31) formed in the multilayer semiconductor layer (20) and a second gate trench branch (32) penetrating through the dielectric layer (40); the second gate trench branch (32) comprises a second opening (321) located in the surface of the side, close to the substrate (10), of the dielectric layer (40), and a third opening (322) located in the surface of the side, away from the substrate (10), of the dielectric layer (40); a vertical projection of the third opening (322) on the substrate (10) covers a vertical projection of the second opening (321) on the substrate (10); and the opening area of the third opening (322) is larger than the opening area of the second opening (321). The semiconductor device of the present application is favorable for achieving high-frequency characteristics, reducing gate resistance, suppressing the short channel effect of the semiconductor device, and improving the reliability of the semiconductor device.
Embodiments of the present application disclose a semiconductor device and a preparation method thereof, wherein, the semiconductor device comprises a substrate; a multi-layer semiconductor layer arranged on one side of the substrate; a source, a gate, a drain and a field plate structure, which are arranged on one side, away from the substrate, of the multi-layer semiconductor layer, wherein the field plate structure comprises a body part and a first extension part; the body part is arranged between the gate and the drain; the first extension part is connected with the body part, and is arranged on one side, away from the multi-layer semiconductor layer, of the gate, and the first extension part and the gate are at least partially overlapped. According to the described technical solution, by arranging the first extension portion and the gate to be at least partially overlapped, the field plate structure extends towards the gate side, the modulation effect of the field plate structure on the electric field can be increased, the electric field accumulation on the side, close to the drain, of the gate is reduced, the probability of breakdown on the side, close to the drain, of the gate is reduced, and the reliability of the semiconductor device is improved.
The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/765 - Making of isolation regions between components by field-effect
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
43.
Semiconductor device and method of manufacturing the same
A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate.
Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer.
Provided in the embodiments of the present invention are a semiconductor device, a semiconductor chip, and a method for manufacturing the semiconductor device, the semiconductor device comprising a substrate and a semiconductor layer manufactured on the substrate; a plurality of gate electrodes, a plurality of drain electrodes, and a plurality of source electrodes are manufactured on the side of the semiconductor layer furthest from the substrate, the gate electrodes being positioned between the source electrodes and the drain electrodes, and the gate electrodes, the source electrodes, and the drain electrodes being positioned in an active region of the semiconductor device; a gate interval is formed between any two adjacent gate electrodes, the formed gate intervals comprising at least two unequal gate intervals, the biggest gate interval amongst the gate intervals being positioned in a first preset range determined on the basis of the interval in the gate length direction of the two gate electrodes at the outermost two ends of the semiconductor device and the total number of gate electrodes of the semiconductor device. The embodiments of the present invention can effectively improve the temperature distribution gradient in the semiconductor device, increasing the heat dissipation efficiency in the centre of the device.
The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A semiconductor device (100) and a manufacturing method thereof relating to the field of semiconductor technology. The semiconductor device (100) comprises a substrate (110), a semiconductor layer (120), a dielectric layer (130), a source (140), a gate (160), and a drain (150). The side of the gate (160) adjacent to the drain (150) and adjacent to a first face of the semiconductor layer (120) is a first curved face (180). A gate groove (161) corresponding to the gate (160) is provided on the dielectric layer (130), and a material of the gate (160) is filled in the gate groove (161). At least a portion of a second face of the gate groove (161) in contact with the gate (160) is a second curved face (162). The second curved face (162) extends from the dielectric layer (130) surface, which is opposite to the semiconductor layer (120), in a direction of the semiconductor layer (120). By means of the semiconductor device structure the potential gradient of the semiconductor device (100) can be made more gradual.
A semiconductor device, comprising: a semiconductor substrate; a source, a gate, and a drain formed on one side of the semiconductor substrate; a through-hole area reserved in an area where the source is located, and an etching barrier layer formed in the through-hole area; and a through-hole located below the etching barrier layer and running through the semiconductor substrate.
A semiconductor device (100) and a manufacturing method therefor, which relate to the technical field of semiconductors. The semiconductor device (100) comprises an active region (10) and a passive region (20) located outside the active region (10). The semiconductor device (100) comprises a substrate (110), a semiconductor layer (120), a source electrode (130), a drain electrode (140) and a gate electrode (150), wherein the semiconductor layer (120) comprises a first semiconductor layer located in the active region (10) and a second semiconductor layer (121) located in the passive region (20). Below the source electrode (130), a through hole (131) penetrating through the substrate (110) and the semiconductor layer (120) below the source electrode (130) is provided. Part of the through hole (131) is located in the second semiconductor layer (121) of the passive region (20), and penetrates through at least part of the second semiconductor layer (121). When a device of small size is fabricated, even if the distance between through holes (131) is reduced due to a reduction in the device size, the size requirements of the device can still be satisfied, and the device size can be reduced without increasing the process difficulty, moreover, the heat dissipation of the device is not affected, and the grounding inductance is also not increased, and the performance of the device can also be improved.
The present invention provides a semiconductor device heat dissipation structure and semiconductor device, relating to the field of semiconductor technology. The heat dissipation structure of a semiconductor device according to one embodiment comprises: a first heat dissipation window, formed on the upper surface of said heat dissipation structure adjacent to one end of said semiconductor device; and at least one heat dissipation passageway, said heat dissipation passageway comprising an inflow passageway and an outflow passageway, and by way of the inflow passageway, a thermally conductive medium being caused to flow toward a first heat dissipation window; the inflow passageway comprises a first opening and a second opening, said first opening being away from said first heat dissipation window; said second opening being adjacent to said first heat dissipation window, and the opening area of the first opening being larger than the opening area of the second opening.
The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a source and a drain located on one side of the semiconductor layer, a blocking layer located on one side of the semiconductor layer, the blocking layer including silicide, wherein the distance between an interface at one side of the blocking layer close to the semiconductor layer and the semiconductor layer is equal to or more than 10 nm, and a gate located between the source and the drain, the gate penetrating through the blocking layer, the gate including a first conductive layer and a second conductive layer, the first conductive layer being close to the semiconductor layer, the second conductive layer being located on one side of the first conductive layer away from the semiconductor layer, and the first conductive layer including nickel.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A semiconductor device and a method for manufacturing same. The semiconductor device (10) comprises: an active area (11), a testing area (12), and an inactive area located outside the active area and the testing area. A standard device (100) is manufactured in the active area, and a testing device (200) used for testing a property parameter of the standard device is manufactured in the testing area. By manufacturing a testing device around a standard device and testing an electrical property of the testing device, a corresponding electrical property of the standard device may be estimated in a wafer level test, so that a qualified standard device can be obtained by screening according to the testing result, without the need of cutting and packaging a standard device with a larger size to perform testing, and thus the problem in the art that standard devices cannot pass a wafer level test is avoided, testing processes are saved, and a production cycle is shortened.
A semiconductor device (100) and a manufacturing method therefor. The semiconductor device (100) comprises: a semiconductor layer (110); a source (130) and a drain (140) located on one side of the semiconductor layer (110); a barrier layer (150) located on a side away from the semiconductor layer (110), the barrier layer (150) comprising a silicide, the distance from an interface of the side, close to one side of the semiconductor layer (110), of the barrier layer (150) to the semiconductor layer (110) being 10 nm or more; and a gate (160) located between the source (130) and the drain (140), the gate (160) extending through the barrier layer (150), the gate (160) comprising a first conductive layer (161) and a second conductive layer (163), the first conductive layer (161) being close to the semiconductor layer (110), the second conductive layer (163) being located on the side, away from the semiconductor layer (110), of the first conductive layer (161), the first conductive layer (161) comprising nickel. The semiconductor device (100) reduces, by increasing the distance from the interface of the silicide barrier layer to the semiconductor layer (110), the electric field strength at the position where nickel-silicide is generated, has low gate leakage and high reliability, and does not cause the current collapse and deterioration, being suitable for communication systems.
The present invention relates to the technical field of semiconductors, and provides a semiconductor device and a method for manufacturing same. According to an embodiment, the semiconductor device (100) comprises: a substrate (101); a semiconductor layer (102) located at one side of the substrate; a source (103), a drain (104) and a gate (105) located between the source and the drain which are located at one side, distant from the substrate, of the semiconductor layer; and an isolation structure (106) provided at one side, distant from the substrate, of the semiconductor layer. One end of the isolation structure is provided close to one side of the source, and the other end thereof is provided close to one side of the drain and is in direct contact with the surface of the semiconductor device. The isolation structure covers the gate or a part of the gate. The isolation structure is of an integrated structure, and forms a cavity with the semiconductor layer. At least a part of the gate is located in the cavity. An opening is formed in the cavity along a gate extending direction. The opening is sealed by a sealing structure (107) to form a sealed cavity.
The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.
Provided are a semiconductor chip, a semiconductor wafer (1), and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises a base (11), a device (12) provided at one side of the base, a through hole (13) extending through the base, an electrically conductive material (14) filled in the through hole and in contact with the device, and a back metal layer (15) provided at the other side of the base away from the device. The back metal layer is in contact with the electrically conductive material so as to be electrically connected to the device by means of the electrically conductive material. The semiconductor chip, the semiconductor wafer, and the method for manufacturing a semiconductor wafer of the present invention reduce ground resistance of a device and mitigate a heat dissipation problem of a device having a through hole structure in an operating state.
A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
58.
Semiconductor device having source field plate and method of manufacturing the same
A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 23/373 - Cooling facilitated by selection of materials for the device
60.
Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
61.
Semiconductor device and method of manufacturing the same
A semiconductor device includes: a substrate having a rear side on which a grounded electrode is disposed; a semiconductor layer disposed on a front side of the substrate and including an active region and an inactive region; a plurality of source electrodes disposed in the active region; a drain electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; a gate electrode including a plurality of first portions disposed in the active region and a second portion disposed in the inactive region; and a plurality of source electrode pads having the same number as the plurality of source electrodes and disposed in the inactive region and each being connected to a corresponding source electrode directly. A plurality of through holes electrically connecting the plurality of source electrodes and the grounded electrode respectively are disposed in the plurality of source electrode pads.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
62.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a ground electrode being disposed on the rear side of the substrate; and a semiconductor layer located on the front side of the substrate; the semiconductor layer comprises a active region (5) and a passive region, the active region (5) being closed, and an area outside the active region (5) being the passive region, and a source (11) located in the active region (5) and a source pad (13) located in the passive region, the source pad (13) being electrically connected to the source (11) directly, and each source (11) in the active region is grounded separately through the source pad (13) that is directly connected thereto and a via hole(4). The problem caused by the arrangement of via hole positions in the existing semiconductor device is solved, and in addition, by using the advantage of via holes, the grounding inductance of the source of a device is reduced as much as possible, and performance such as gain and power of the device is improved.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
63.
Isolated gate field effect transistor and manufacture method thereof
An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/201 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
64.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and manufacturing method thereof, said device comprising: a substrate; a multilayer semiconductor layer located on said substrate; a source and a drain located on said multilayer semiconductor layer, as well as a gate located between the source and the drain; a dielectric layer located on at least one part of the surface of said multilayer semiconductor layer between the gate and the drain, and a recess being present on said dielectric layer; a source field plate located on said dielectric layer, said source field plate being electrically connected, by means of at least one conductive path, to said source, and said source field plate covering all or part of the recess on the dielectric layer. Thus full play is given to the effect of the source field plate, while gate-source capacitance Cgs is also reduced; the peak electric field of the gate edge is reduced, the breakdown voltage of the device is increased, the gate leakage current of the device is reduced, the frequency characteristics of the device are increased, giving full play to the advantage of high output power of the device.
Disclosed is a radio frequency device; the nitride potential barrier layer (14) of the radio frequency device has two layers of aluminum enriched nitride, wherein the content of aluminum exceeds 75%. The second nitride layer (142) is a silicon-containing nitride; by having sufficiently high silicon content, the metal electrodes in the drain electrode and the source electrode form ohmic contacts with the second nitride layer (142), which not only reduces the contact resistance of the drain and source electrodes, but also further increases the concentration of the two dimensional electron gas due to the fact that the silicon-containing nitride can provide more free electrons, thus improving the radio frequency performance of the devices. At the same time, a medium layer is produced in situ on the above silicon-containing nitride (142), and used as a passivating layer of the nitride, thus reducing the surface state density and the release of stress. During the manufacture of a gate electrode (161), the passivating layer (15) in the gate area is etched away, and the exposed nitride potential barrier layer (14) is treated by oxidization. The oxide produced at the gate electrode (161) can greatly reduce the leakage current of the gate electrode (161) and the leakage current between the source electrode (162) and drain electrode (163). In addition, also provided is a method for manufacturing the above radio frequency device.
An isolated gate field effect transistor and the manufacture method thereof. Through the method of introducing metal when a dielectric layer (6, 8) is grown on a nitride transistor structure, the chemical properties of the dielectric layer (6, 8) are changed, and the effects of controlling etching speed and depth can be played. A groove structure (H1) is formed in a grid region in a partially thinned manner, and the semi-conductor contact is reserved at the grid, and meanwhile, the groove (H1) is used for forming a field plate structure. Since the surface of a semi-conductor is protected by the dielectric layer (6, 8) during the entire technological process, damage to the surface of nitride, stress releasing and staining on the surface of the nitride can be greatly reduced, and the current collapsing effect of a device can be reduced greatly. Furthermore, since MISFET or MOSFET structure composed of high-quality dielectric layer, current leakage of the grid can be reduced greatly.
A semiconductor device and a fabrication method thereof are provided. The semiconductor device comprises: a semiconductor layer on a substrate; an insulation layer on the semiconductor layer; a source (41) and a drain (42) which are in contact with the semiconductor layer, wherein the source (41) has multiple fingers (41A), the drain (42) has multiple fingers (42B), and the multiple fingers (41A) of the source (41) intersect the multiple fingers (42B) of the drain (42); a gate (43) on the insulation layer, which is located between the source (41) and the drain (42), and the gate (43) includes a closed ring structure which encircles the multiple fingers (41A) of the source (41) and the multiple fingers (42B) of the drain (42).
A HEMT device and a manufacturing of the HEMT device, the HEMT device includes: a buffer layer (14) on the substrate (12); a semiconductor layer on the buffer layer (14); an isolation layer (16, 17) on the semiconductor layer; a source electrode (22) and a drain electrode (23) contacted with the semiconductor layer; a gate electrode (24,104,114) between the source electrode (22) and the drain electrode (23); the channel, which is located in the semiconductor layer below the gate electrode (24,104,114), is pinched off.
patents
