Abstract

A semiconductor device comprises: a SiC epitaxial layer and a first recess. The SiC epitaxial layer has: a p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The first recess is formed in the heavily doped p-type region and the heavily doped n-type region, wherein a depth of the first recess exceeds a depth of the heavily doped n-type region.

IPC Classes  ?

• H10D 30/66 - Vertical DMOS [VDMOS] FETs
• H10D 12/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes

Abstract

A biochip is configured for detecting biological materials in a solution and includes at least one detection unit, which includes a substrate, a first insulation layer disposed on the substrate, a semiconductor layer, a second insulation layer, a first metal layer, a second metal layer and a protection layer. The semiconductor layer is disposed on the first insulation layer and includes multiple reaction regions. The second insulation layer is disposed on the semiconductor layer and includes a first part, a second part surrounding the first part and a first opening. The first opening exposes the reaction regions. The first metal layer is disposed on the second part and includes source electrode, drain electrode, gate electrode and first wall structure. The protection layer includes a flat part defining a second opening, a first protruding part defining a third opening and a second protruding part defining a fourth opening.

IPC Classes  ?

• G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors

Abstract

A biochip includes a substrate, an insulating layer, a semiconductor layer, a dielectric layer, a metal layer, and a protective layer. The semiconductor layer is disposed on the insulating layer and has a reaction region. The dielectric layer is disposed on the semiconductor layer and has a first opening. The metal layer is disposed on the dielectric layer and includes a source, a drain, and a wall structure. The wall structure surrounds the first opening, the source, and the drain. The protective layer is disposed on the metal layer and has a flat part, a protruding part, a second opening, and a third opening. The flat part surrounds and defines the second opening. The protruding part is disposed corresponding to the wall structure, and the protruding part surrounds and defines the third opening. The second opening connects the third opening and the first opening to expose the reaction region.

IPC Classes  ?

• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers

Abstract

A semiconductor device comprises: a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has: a p-type buried layer; and a junction field effect region in contact with the p-type buried layer in a gate region. The semiconductor device further comprises: a gate oxide layer on the silicon carbide epitaxial layer; a poly silicon layer on the gate oxide layer; an interlayer dielectric layer on the poly silicon layer; a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device comprises: a SiC epitaxial layer and a first recess. The SiC epitaxial layer has: a p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The first recess is formed in the heavily doped p-type region and the heavily doped n-type region, wherein a depth of the first recess exceeds a depth of the heavily doped n-type region.

IPC Classes  ?

• H10D 12/01 - Manufacture or treatment
• H10D 30/66 - Vertical DMOS [VDMOS] FETs
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

A structure for suppressing current leakage and a semiconductor device including the same are provided. The structure for suppressing current leakage includes a substrate of a first conductivity type, a well region of the first conductivity type, an isolation structure and a PN junction diode. The well region is disposed in the substrate. The isolation structure is disposed on the well region. The PN junction diode is disposed on the isolation structure and configured to suppress current leakage of the semiconductor device.

IPC Classes  ?

• H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/861 - Diodes
• H01L 29/40 - Electrodes

Abstract

A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 21/311 - Etching the insulating layers
• C23F 1/00 - Etching metallic material by chemical means
• B29D 11/00 - Producing optical elements, e.g. lenses or prisms
• B23P 15/00 - Making specific metal objects by operations not covered by a single other subclass or a group in this subclass
• C25F 3/00 - Electrolytic etching or polishing

Abstract

A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched